Analog Peak Detector and Derandomizer

G. De Geronimo, A. Kandasamy, P. O’Connor

Brookhaven National Laboratory

IEEE Nuclear Sciences Symposium, San Diego

November 7, 2001

Multichannel Readout Alternatives

Direct digitization Track-and-Hold+ Analog Multiplex

Analog Memory+ Analog Multiplex

• most flexible

• requires many fast ADCs

• expensive, high power

• requires trigger

• has deadtime

• timing uncertainty

• requires sparsification

• requires trigger

• can be deadtimeless (complex control)

• requires sparsification

A DC

P /S

A DC

A DC

CK

...

A DC

P /S

A DC

A DC

CK

...

T/H

A DC

P /S

T/H

T/H

S A M P LE

CK

...

A NLGM UX

T/H

A DC

P /S

T/H

T/H

S A M P LE

CK

...

A NLGM UX

A DC

P /S

CE LL A DDR

CK

...A NLGM UX

A DC

P /S

CE LL A DDR

CK

...

A NLGM UX

Ideal Self-triggered, Self-sparsifying, Deadtimeless Readout

C H 1

C H 2

C H 3

C H N

A D C

A1 A2 A3 A4 A5

S1 S2

S3

S4 S5

D A Q...

...

P K H T

A D D R

R E A D R E Q

P K T IM E

P /S

T 1 T 2 T 3 T 4 T 5

Peak Detector (PD)

+-

in

CH

out

Advantages

• self-triggering

peakheld

• self-sparsifying

• timing output

reset

• deadtime until reset

Drawbacks

• accuracy impaired by op-amp offsets, CMRR, slew rate

• poor drive capability

Improved CMOS PD Using Two-Phase Configuration

Write phase

• conventional peak detector

• M1: unidirectional current source

• voltage on CH includes op-amp errors (offset, CMRR)

+-in

CH

M 1

out

voff

+-in

CH

M 1

out

voff

Read phase

• same op-amp re-used as unity-gain buffer

• same CM voltage

• op-amp errors cancel

• enables rail-to-rail sensing

• provides good drive capability

+-in

CH

M 1

out

voff

+-in

CH

M 1

out

voff

Two-Phase Peak Detector in 0.35 m CMOS

PD loop with switches

Switch control logic (data driven)

245 m

50 m

340 m

50 m

LAYOUTSCHEMATIC

+-

Vg

Vref

V CK

D

RST

Q

QB

rese t

R

W

Two-Phase CMOS Peak Detector - Results

0 1 2 3 40.0

0.2

0.4

0.6

0.8

1.0

Vip

(b)

Vo

Vh

Vg / V

DD

Vi

Sig

nal [

V]

Time [µs]

0 1 2 3 40.0

0.2

0.4

0.6

0.8

1.0

Vip

(b)

Vo

Vh

Vg / V

DD

Vi

Sig

nal [

V]

Time [µs]

Waveforms Absolute accuracy

0.00 0.02 0.04 0.06 0.08 0.100.95

0.96

0.97

0.98

0.99

1.00

Vo

Sig

nal

[V

]

Time [s]

0.00 0.02 0.04 0.06 0.08 0.100.95

0.96

0.97

0.98

0.99

1.00

Vo

Sig

nal

[V

]

Time [s]

Time walkDroop rate

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Peak Amplitude (V)

-15

-10

-5

0

5

Err

or in

pea

k he

ight

(m

V)

0.2 us0.5 us5 us15 us

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Peak Amplitude (V)

-15

-10

-5

0

5

Err

or in

pea

k he

ight

(m

V)

0.2 us0.5 us5 us15 us

20

24

28

32

36

40

0 1 2 3

Peak amplitude (V)

Del

ay (

ns) Tp=200ns

Tp=500ns

± 2.3ns

20

24

28

32

36

40

0 1 2 3

Peak amplitude (V)

Del

ay (

ns) Tp=200ns

Tp=500ns

± 2.3ns

• Self-triggering• 2-phase operation eliminates op-amp errors

• High absolute accuracy independent of process, supply, temperature variation• Rail-to-rail input and output

• Strong drive capability• No switch charge injection into hold node• Timing output

Parameter Value Technology 0.35 m CMOS DP4M Supply voltage 3.3 V Input voltage range 0.3 – 3 V Absolute accuracy 0.2 %, tp 500ns

0.7%, tp =200ns Time walk 2.3 ns, Vin < 2.5 V

± 5 ns, Vin < 3 V Droop rate 0.25 V/s Power dissipation 3.5 mW Cell area 0.03 mm2

Two-Phase CMOS Peak Detector - Summary

Peak Detector and Derandomizer

• Combine the peak detect and analog hold functions of the PD with additional analog storage and control logic to create a Peak Detector– Derandomizer (PDD).

• PDD behaves like a data driven, analog FIFO memory.

• Topologies:

P D

R S T P K

IN O UT

P D

R S T P K

IN O UT

C ON TR OL

P D

R S T P K

IN O UT

V IN V O U T

HIT

S in S out

R D R E Q

R E S E T

P D

R S T P K

IN O UT

P D

R S T P K

IN O UT

C ON TR OL

P D

R S T P K

IN O UT

V IN V O U T

HIT

S in S out

R D R E Q

R E S E T

A: Array of PD with ping-pong control

P D

R S T P K

IN O UT

C ON TR OL

HIT

R S T

C A P A D D RR D R E Q

R E S E T

S C A(A NA LO G B UF F E R )

V IN V O U T

P D

R S T P K

IN O UT

C ON TR OL

HIT

R S T

C A P A D D RR D R E Q

R E S E T

S C A(A NA LO G B UF F E R )

V IN V O U T

B: PD plus SCA as analog buffer

P D

R S T P K

IN

O UT

V h

C ON TR OL

HIT

R S T

C A P A D D RR D R E Q

R E S E T

S C A(MULT IP LE HO L D C A P S )

V INV O U T

P D

R S T P K

IN

O UT

V h

C ON TR OL

HIT

R S T

C A P A D D RR D R E Q

R E S E T

S C A(MULT IP LE HO L D C A P S )

V INV O U T

C: PD with multiple hold capacitors

Topology A with two parallel PDs has been fabricated and tested.

Multichannel Readout System with PDD

C ZTA R R A Y

P /S

P /S

S S M P D D A D C

LOGICA N A L.

16

16

16

16

32

5

12

A D D RP E A K

P ULS E R

R E A D R S TS O UR C E

C NV T

P K F ND

SSM: self-switched multiplexer; custom chip that detects above-threshold inputs and routes them to PDD input.

In response to a READ request from the DAQ system (pulser), the next peak sample stored in the PDD is presented to the 12-bit ADC.

After a fixed delay the pulser RESETs the PDD that was read out, freeing it to process next input pulse.

Multichannel PDD Readout System: First Results

0 20 40 60Time, us

READ

PDD OUT

PDD IN

PK FND

• Input pulses from source occur randomly

• READ process is synchronous 200 kHz

• READ rate matches average input rate

• Simultaneous readout and acquisition of new data

• 2-sample buffer absorbs rate fluctuations

Multichannel PDD Readout System

0

0.5

1

20 25 30 35 40 45 50 55 60 65 70

Energy (keV)

FWHM 4.2 keV

Spectra

Solid line: commercial MCA.

Points: PDD, single channel.

Circles: PDD, 16 channels gain-adjusted.

Resolution limited by CZT detectors.

Source Profile241Am source centered over channel 2.

0

50

100

150

Kco

un

ts

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Channel No.

Summary

• New 2-phase peak detector in submicron CMOS:• High absolute accuracy (0.2%) and linearity (0.05%)

• Rail-to-rail input and output

• ± 2.3 ns time walk

• Low power (3.5 mW)

• Extremely compact (0.03 mm2)

• A building block for compact, efficient multichannel readout system:– Self-triggered

– Self-sparsifying

– Deadtimeless

• Peak detector – derandomizer (PDD) with 2-event buffer demonstrated:– First step towards data-driven analog FIFO readout