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Small Signal Equivalent circuits: diodes, BJTs, MOSFETs and analog CMOS. Simple diode circuits: clipping, clamping, rectifier. Biasing and bias stability: BJT and FET amplifiers. Amplifiers: single-and multi-stage, differential and operational, feedback, and power. Frequency response of amplifiers. Simple op-amp circuits. Filters. Sinusoidal oscillators; criterion for oscillation; single-transistor and op-amp configurations. Function generators and wave-shaping circuits, 555 Timers. Power supplies.

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Characteristics of diodes, BJT, FET; amplifiers– biasing, equivalent circuit and frequency response; oscillators and feedback amplifiers; operational amplifiers–characteristics and applications; simple active filters; VCOs and timers

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Characteristics of diode, BJT, JFET and MOSFET. Diode circuits. Transistors at low and high frequencies, Amplifiers, single and multi-stage. Feedback amplifiers. Operational amplifiers, characteristics and circuit configurations. Instrumentation amplifier. Precision rectifier. V-to-I and I-to-V converter. Op-Amp based active filters. Oscillators and signal generators.

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1. OPERATIONAL AMPLIFIER

1.1 Introduction 01 1.2 Inverting & Non-Inverting Amplifier 02 1.3 Summing & Difference Amplifier 04 1.4 Voltage Follower 04 1.5 Current to Voltage Converter 05 1.6 Voltage to Current Converter 05 1.7 Instrumentation Amplifier 05 1.8 Integrator & Differentiator 06 1.9 Log & Antilog Amplifier 06 1.10 Filters 08 1.11 Comparators 10 1.12 Zero Crossing Detector 10 1.13 Schmitt Trigger 11 1.14 Multivibrators 12 1.15 Slew Rate 14 1.16 CMRR 14 1.17 Parameters Related To Op-Amp 15

Gate Questions

2. DIODE APPLICATIONS

2.1 Introduction 67 2.2 Rectifiers 67 2.3 Clippers 72 2.4 Clamper 75 2.5 Voltage Doubler 76 2.6 Voltage Regulator 77

Gate Questions

3. BJT BIASING

3.1 Introduction 101 3.2 Operating Regions of Transistor 101 3.3 Modes of Operation of BJT 104 3.4 Load Line 105 3.5 Biasing 106

Gate Questions

CONTENTS

16

81

110

4. SMALL SIGNAL ANALYSIS OF BJT

4.1 Introduction 122 4.2 Transistors at Low Frequency 122 4.3 Transistors at High Frequency 129 4.4 T-Model of BJT 132

Gate Questions

5. FET ANALYSIS

5.1 Introduction 137 5.2 JFET Common Source Amplifier 137 5.3 JFET Self Bias Configuration 138

Gate Questions

6. MULTISTAGE AMPLIFIERS

6.1 Introduction 163 6.2 Lower Cut-Off Frequency 164 6.3 Cascode Amplifiers 166 6.4 Current Mirror 167 6.5 Darlington Amplifier 167

7. FEEDBACK AMPLIFIERS

7.1 Introduction 169 7.2 Types of Amplifiers 171 7.3 Types of Negative Feedback 172 7.4 Oscillators 175 7.5 Audio Frequency Oscillators 175 7.6 Radio Frequency Oscillators 176

Gate Questions

8. POWER AMPLIFIERS

8.1 Introduction 190 8.2 Classification of Power Amplifiers 190 8.3 Collector Efficiency 191 8.4 Distortions 191

9. 555 TIMER

9.1 Introduction 193 9.2 Astable Multivibrator 194 9.3 Monostable Multivibrator 195

Gate Questions

10. ASSIGNMENT

133

141

181

196

203

1. 1 INTRODUCTION

The name “op-amp” is the standard abbreviation for operational amplifier. This name is given because the basic amplifier can be used with few external components to perform various mathematical “operations”. It is most commonly used in amplifier and analog signal processing circuits in the frequency band from 0 to 100 kHz. High-frequency op-amps are used in applications that require a bandwidth into the MHz range.

If voltage 1V is applied at the inverting input & voltage 2V is applied at the non-inverting input, then the OP-AMP generates a differential output whose polarity depends on the magnitude of voltages applied at the inputs.

0 OL 2 1i.e. V A (V V )= − If 2 1V V> 0V ve= +If 2 1V V< 0V ve= −

1.1.1 BLOCK DIAGRAM OF OP-AMP

An op-amp is a high quality amplifier. It contains four stages, which are connected in cascaded manner.

The first stage of an op-amp is a double ended differential amplifier. This stage provides maximum voltage gain. This stage should employ a current source at the common emitter node for good common mode rejection. The second stage is an intermediate gain stage called single ended differential amplifier. It does not require a current source in the emitter. Normally the second stage is needed only to provide some additional gain. Its input resistance should be relatively high to prevent excessive loading of the first stage. The third stage is an emitter follower, which produces unity gain. It has high input resistance and also low output resistance. It matches the output of amplifier stage and the input of output stage. The fourth stage is a level translator and output driver. This stage is used for preventing any undesired dc current in the load and increasing the permissible output voltage swing. Hence it supplies large output voltage or current.

1.1.2 FREQUENCY RESPONSE

The “frequency response” of any circuit is the magnitude of the gain in decibels (dB) as a function of the frequency of the input signal.

1 OPERATIONAL AMPLIFIER

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1.1.3 CHARACTERICS OF OP-AMP An OP-AMP has the following characteristics: 1) The input resistance inR is around

610 Ω & for ideal OP-AMP it is infinite. 2) The output resistance oR is very small

& ideally it is zero. 3) The open-loop voltage gain is around

610 Ω & ideally it is infinite. 4) The bandwidth (how quickly the output

will follow the input) would be infinite. 5) As the input resistance is very high, the

currents entering the input terminal are negligibly small & ideally the currents are zero.

1.2 INVERTING & NON-INVERTING AMPLIFIER 1) Inverting amplifier: The figure below shows a basic

inverting amplifier. It is called inverting amplifier because it inverts the polarity of the voltage applied at the input.

As the non-inverting input is grounded, ∴ pV 0V= By virtual ground concept the inverting

& non-inverting voltages must be same, i. e. n pV V 0V= = Now, applying KCL at Vn we get, 1 f b0 I I I= + +

n on i

1 f

V VV V0R R

−−∴ = +

b( I 0A)=Q Solving the above equation considering

nV 0V= we get,

fo i

1

RV VR

= −

This equation is the basic output equation for an inverting amplifier. The gain of the inverting amplifier is

o f

i 1

V RAV R

= = − .

2) Non-inverting amplifier: The figure below shows a basic non-

inverting amplifier.

As the input source is applied at the

non-inverting input, ∴ p iV V= By virtual ground concept the inverting

& non-inverting voltages must be same, i.e. n p iV V V= = Now, applying KCL at nV we get, 1 f b0 I I I= + +

n onb

1 f

V VV 00 ( I 0A)R R

−−∴ = + =Q

Solving the above equation considering n pV V= we get,

fo p

1

RV 1 VR

= +

This is the general expression for output of a non-inverting amplifier. The gain of the non-inverting amplifier is

o f

p 1

V RA 1V R

= = + .

In this circuit the voltage Vpis equal to the input iV ,

∴ fo i

1

RV 1 VR

= +

© Copyright Reserved by Inspiring Creativity & Enedavour Gate Institute No part of this material should be copied or reproduced without permission

Operational Amplifier

2

Example Find the expression for output

Solution The above circuit is a non-inverting amplifier. We know the general expression for its output as

fo p

1

RV 1 VR

= +

Like the standard non-inverting amplifier, in this circuit p iV V≠ . The voltage at the non inverting input can be found out using the potential divider network

A/c to potential division rule, 4

p i4 3

RV VR R

=+

f 4o i

1 4 3

R R V 1 VR R R

∴ = + × +

Example: In the circuit shown in the figure, find the expression for output.

Solution:

1) In the circuit pV 0V= , therefore a/c to virtual ground concept nV 0V= .

2) As the potential at both the ends of Rare zero, the current through R i.e. Iwould be zero. Hence this resistor Rwould have no significance in theinverting amplifier.

3) Also the load resistance in the invertingand non inverting amplifier does notaffect the output

∴ fo i

1

RV VR

= −

Example Find the expression for output of an inverting amplifier with a T network in feedback.

Converting the T network into a delta network we get,

Where, ' 2 43 2 4

3

R RR R RR

= + +

' 3 42 3 4

2

R RR R RR

= + +

' 2 34 2 3

4

R RR R RR

= + +

We know that the resistors ' '2 3R &R do not

affect the output,

∴ '

f 4o i i

1 1

R RV V VR R

= − = −



3

1.3 SUMMING & DIFFERENCE AMPLIFIER 1) Summing amplifier: A basic inverting summing amplifier is

shown in the figure below. The output will be due to the effect of all the input voltages.

Applying KCL at nV we get, 4 1 2 3i i i i= + + Substituting for all the currents we get,

n o 3 n1 n 2 n

f 1 2 3

V V V VV V V VR R R R− −− −

= + +

A/c to virtual ground process nV 0V= , solving for oV we get,

f f fo 1 2 3

1 2 3

R R RV V V VR R R

= − + +

If 1 2 3R R R R= = = we get,

fo 1 2 3

RV (V V V )R

= − + +

2) Difference amplifier:

A differential amplifier generates an

output which is difference between the outputs due to both the inputs. The above difference amplifier can be analyzed using superposition principle i.e. by considering only 1 source in the circuit at a time.

1) Considering only 1V (deactivating 2V )

When only 1V is considered, the circuit reduces to an inverting amplifier & its output is given by

fo1 1

1

RV VR

= −

2) Considering only 2V (Deactivating 1V )

When only 2V is considered, the circuit reduces to a non-inverting amplifier & its output is given by

3fo2 2

1 2 3

RRV 1 VR R R

= + × +

Now, the total output will be the sum of individual outputs in the 2 cases

o o1 o2V V V= +

3f fo 1 2

1 1 2 3

RR RV V 1 VR R R R

∴ = − + + × +

1.4 VOLTAGE FOLLOWER A voltage follower is a special case of a non-inverting amplifier. In voltage follower there is maximum negative feedback hence the voltage is minimum.



4

For a non-inverting amplifier, the equation for output is given by

fo i

1

RV 1 VR

= +

From the circuit, fR 0=

( )o i iV 1 0 V V∴ = + =

As o iV V= hence it is called as voltage follower whose output voltage follows input voltage.

Note: For a voltage follower the voltage gain is 1 hence it is also called as unity gain non-inverting amplifier.

1.4.1 CHARACTERISTICS

1) Voltage gain is 12) Input resistance is around 410 MΩ

1.4.2 APPLICATION

1) It is used as a buffer2) It is used as an impedance matching

device3) It is used in Butter worth filters4) It is used in sample & hold circuit

1.5 CURRENT TO VOLTAGE CONVERTER

In some application it is needed to convert output current into voltage. For this purpose the OP-AMP can be used as a current to voltage converter as

A/c to virtual ground concept nV 0V= , applying KCL at nV we get,

1 2i i=

n o os

f f

V V Vi.e. iR R−

= = −

o s f V i R∴ = −

1.6 VOLTAGE TO CURRENT CONVERTER

1) In the figure 1, the circuit is a voltage tocurrent converter with floating load

f(R ) . The load current 2i for this circuitis given by

i2

1

ViR

=

2) In the figure 2, the circuit is a voltage tocurrent converter with grounded load( )LZ . The load current Li is given by

iL

ViR

= −

1.7 INSTRUMENTATION AMPLIFIER

Instrumentation amplifier is a kind of differential amplifier with additional input buffer stages. The addition of input buffer stages makes it easy to match (impedance matching) the amplifier with the preceding stage. Instrumentation amplifiers are commonly used in industrial test and measurement application. The instrumentation amplifier also has some useful features like low offset voltage, high



5

CMRR (Common mode rejection ratio), high input resistance, high gain etc. The circuit diagram of a typical instrumentation amplifier using op-amp is shown figure

In the instrumentation amplifier, the OP-AMPs 1 2A & A are buffers (note that gain is not unity for 1 2A & A ) while the OP-AMP 3Ais a differential amplifier. The output equation for this instrumentation amplifier is

( )4 2o 2 1

3 1

R 2RV 1 V VR R

= + −

1.8 INTEGRATOR & DIFFERENTIATOR 1) Integrator: If the feedback resistor fR is replaced by

a capacitor, it works like an integrator.

The expression for output can be found

out by 2 methods a) By solving in s domain In s domain the impedance of capacitor

is written as c1X

Cs= . The expression

for output of an inverting amplifier is given by

o i

1

1CsV VR

= −

o i

1

1V VR Cs

∴ = −

The s in the denominator will converted into integration in time domain

o i

1

1V VdtR C

∴ = − ∫

b) By solving in time domain Applying KCL at nV we get,

1 fI I= Substituting for 1 fI & I we get,

Ci n

1

dVV V CR dt−

=

Where c n o oV V V V= − = − n( V 0V)=Q

i.e. oi

1

d( V )V CR dt

−=

o i

1

1 V VdtR C

∴ = − ∫

2) Differentiator: If resistor 1R is replaced with a

capacitor, an inverting amplifier can be used as a differentiator.

Solving for 𝑉𝑉𝑜𝑜 in s domain we get,

fo i

RV V1Cs

= −

i.e. o f iV R Cs V= − × The s in numerator will be converted

into differentiation in time domain,

io f

dVV R Cdt

= −∴

1.9 LOG & ANTILOG AMPLIFIER 1) Log amplifier The given circuit can be used as a logarithmic amplifier provided the diode should be used in forward bias. Hence it is limited only to +ve values of input voltage.



6

The forward current of diode is given by, d

T

vV

f oI I e 1η

= −

The positive exponentiald

T

vVe 1η ? ,

d

T

vV

f o I I eη

∴ ≈

Now, applying KCL at nV

1 fI I=d

T

vVi n

o1

V V I eR

η−=

From the circuit d n ov V V= −

i.e. d ov V= − ( )nV 0V=Qo

T

VVi

o1

V I eR

−η∴ =

Solving the equation we get, i

o T e eo 1

VV V log logI R

= −η

The equation for output indicates that the output voltage is proportional to the input voltage. Note: The log amplifier can be designed using BJT in place of diode as

Here the base to emitter voltage BE B 0 0 0V V V 0 V V= − = − = −

And the emitter current 𝐼𝐼𝐸𝐸is given by BE TV /V

E coI I e=2) Antilog amplifier

Again in this circuit the diode must be operated in forward bias in order to use it as a logarithmic amplifier.

Applying KCL at nV

f 2I I=

i.e. d

T

vV n o

oF

V VI eR

η −=

From the circuit d i nv V V= −

i.e. d iv V= ( )nV 0V=Qi

T

VV o

oF

VI eR

η −∴ =

Solving the equation we get, i

T

VV

o o FV I R eη= −

io o F

T

Vi.e. V I R anti logV

= − η

Example Assuming the OP-AMP in the circuit to be ideal, calculate the voltage gain & input impedance.

Solution The above amplifier is an inverting amplifier. We know that the resistor 20KΩhas zero volts on its both sides therefore the current through it is zero hence it will have no significance in the circuit.

fo i

1

R V VR

∴ = − o f

i 1

V RAV R

⇒ = = −

Here fR 200K= Ω

1R 20K= Ω



7

200K A 1020K

Ω∴ = − = −

Ω

Now, the current through the resistor 1R is

i ni

1

V VIR−

= ii

1

VIR

⇒ =

( )nV 0V=Q Now, the input resistance is

ii 1

i

VR R 20KI

= = = Ω

1.10 FILTERS A filter is a device that passes electric signals at certain frequencies or frequency ranges while preventing the passage of others. A Passive Filter uses inductors capacitors and resistors in combination to create the filter. An Active Filter uses amplifiers (usually operational amplifiers) along with resistors and capacitors to do the filtering. Inductors, which can be large and bulky, are not needed. Using operational amplifiers (or op-amps) allows you to easily make many different kinds of filters. The frequency response of a filter is shown in the figure below:

1) Bandwidth: It is the range of

frequencies for which gain of the filter is almost constant.

2) Cut-off frequency: It is the frequency at which gain of filter reduces to1/ 2times its maximum value. The cut-off frequency is also called as 3 dB frequency.

1.10.1 LOW PASS FILTER The low pass filter is one that allows low frequencies and stops (attenuates) higher frequencies, hence the name. The design of a low pass filter needs to take into consideration the maximum frequency that would need to be allowed through. This is called the cut off frequency (or the 3 dB down frequency).

1) 1st order low pass butter worth filter

The cut-off frequency is given by

H1f

2 RC=

π

2) 2nd order low pass butter worth filter


H1f

2 RC=

π

1.10.2 HIGH PASS FILTER A high-pass filter (HPF) is an electronic filter that passes high frequency signals but attenuates (reduces the amplitude of) signals with frequencies lower than the cut off frequency.



8

http://en.wikipedia.org/wiki/Frequency

http://en.wikipedia.org/wiki/Signal_(electrical_engineering)

1) 1st order high pass Butterworth filter


L1f

2 RC=

π

2) 2nd order high pass Butterworth filter


L1f

2 RC=

π

1.10.3 BANDPASS FILTER

The band pass filter takes advantage of the low pass configuration as well as the high pass configuration. The two of these combine to form a range of frequencies that is called the pass band. Below the lower cutoff frequency the signals are stopped as well as above the higher cutoff frequency. The difference between these two frequencies is called the bandwidth of the filter. The logic behind the cutoff frequencies is a little misleading. The lower cutoff frequency is controlled by the high pass filter part of the band pass filter. On the same type of idea, the upper cutoff frequency is controlled by the low pass filter part of the band pass filter. The

circuit shown in Figure is that of a basic pass band filter.

1.10.4 BAND REJECT FILTER

A band-stop filter or band-rejection filter is a filter that passes most frequencies unaltered, but attenuates those in a specific range to very low levels. It is the opposite of a band-pass filter. A notch filter is a band-stop filter with a narrow stop band.

Example Identify the type of filter.

Solution The type of filter can be identified by calculating the gain of filter at f 0 & f= = ∞ . 1) At f 0= ,the impedance offered by the

capacitor is

c1 1X i.e.Open circuit

2 fC 0= = = ∞

π

In this case, the output oV is given by,

fo i

1

RV VR

= −



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2) At f = ∞ , the impedance offered by the capacitor is

c1 1X i.e.Short circuit

2 fC 0= = = ∞

π

In this case the output oV is given by

oV 0V= As there is no output at higher

frequencies, it is a low pass filter. 1.11 COMPARATORS The basic comparator circuit is an op-amp arranged in the open-loop configuration as shown on the circuit of Figure.

The op-amp is characterized by an open-loop gain OLA and let’s assume that the output voltage oV can go all the way to

( )sat CCV V+ ≈ and sat EEV ( V )− ≈ .The output voltage is given by

0 OL 2 1V A (V V )= − If 2 1 0 V V V ve> = + If 2 1 0 V V V v e< = − The characteristics for this OP-AMP in open loop configuration are given by

In case of practical comparator the open loop gain is finite, hence the transfer characteristics are

1.12 ZERO CROSSING DETECTOR The zero crossing detector circuit is an important application of the op-amp comparator circuit. It can also be called as the sine to square wave converter. Anyone of the inverting or non-inverting comparators can be used as a zero- crossing detector. The only change to be brought in is the reference voltage with which the input voltage is to be compared, must be made zero ref(V 0V)= . An input sine wave is given as𝑉𝑉𝑖𝑖. These are shown in the circuit diagram and input and output waveforms of an inverting comparator with a 0V reference voltage.

As shown in the waveform, for a reference voltage 0V, when the input sine wave



10

passes through zero and goes in positive direction, the output voltage outV is driven into negative saturation. Similarly, when the input voltage passes through zero and goes in the negative direction, the output voltage is driven to positive saturation. The diodes 1D and 2D are also called clamp diodes. They are used to protect the op-amp from damage due to increase in input voltage. They clamp the differential input voltages to either 0.7Vor 0.7V+ − .In certain applications, the input voltage may be a low frequency waveform. This means that the waveform only changes slowly. This causes a delay in time for the input voltage to cross the zero-level. This causes further delay for the output voltage to switch between the upper and lower saturation levels. At the same time, the input noises in the op-amp may cause the output voltage to switch between the saturation levels. Thus zero crossings are detected for noise voltages in addition to the input voltage. These difficulties can be removed by using a regenerative feedback circuit with a positive feedback that causes the output voltage to change faster thereby eliminating the possibility of any false zero crossing due to noise voltages at the op-amp input. 1.13 SCHMITT TRIGGER A Schmitt trigger circuit is also called a regenerative comparator circuit. The circuit is designed with a positive feedback and hence will have a regenerative action which will make the output switch levels. Also, the use of positive voltage feedback instead of a negative feedback, aids the feedback voltage to the input voltage, instead of opposing it. The use of a regenerative circuit is to remove the difficulties in a zero-crossing detector circuit due to low frequency signals and input noise voltages. Shown below is the circuit diagram of a Schmitt trigger. It is basically an inverting comparator circuit with a positive feedback. The purpose of

the Schmitt trigger is to convert any regular or irregular shaped input waveform into a square wave output voltage or pulse. Thus, it can also be called a squaring circuit.

As shown in the circuit diagram, a voltage divider with resistors 1R and 2R is set in the positive feedback of the OP-AMP. The same values of 1R and 2R are used to get the resistance value 1 2R R || R= which is connected in series with the input voltage. R is used to minimize the offset problems. The voltage across 1R is feedback to the non-inverting input. The input voltage iV triggers or changes the state of output oVevery time it exceeds its voltage levels above a certain threshold value called Upper Threshold Voltage UTH(V ) and Lower Threshold Voltage LTH(V ) .

1UTH sat

1 2

RV VR R

= ++

1LTH sat

1 2

RV VR R

= −+

Let us assume that the inverting input voltage has a slight positive value. This will cause a negative value in the output. This negative voltage is fed back to the non-inverting terminal (+) of the op-amp through the voltage divider. Thus, the value of the negative voltage that is fed back to the positive terminal becomes higher. The value of the negative voltage becomes again higher until the circuit is driven into negative saturation sat( V )− . Now, let us assume that the inverting input voltage has a slight negative value. This will



11

cause a positive value in the output. This positive voltage is feed back to the non-inverting terminal (+) of the op-amp through the voltage divider. Thus, the value of the positive voltage that is fed back to the positive terminal becomes higher. The value of the positive voltage becomes again higher until the circuit is driven into positive saturation sat( V )+ .This is why the circuit is also named a regenerative comparator circuit. When o satV V= + , the voltage across 1R is

called Upper Threshold Voltage UTH(V ) . The input voltage iV must be slightly more positive than in order to cause the UTH(V )output oV to switch from satV+ to satV− . When the input voltage is less than UTH(V ) , the output voltage oV will be at satV+ . When o satV V= − , the voltage across 1R is called Lower Threshold Voltage ( )LTHV . The input voltage iV must be slightly more negative than ( )LTHV in order to cause the output oV to switch from satV− to satV+ . When the input voltage is less than ( )LTHV , the output voltage oV will be at satV− .

Note: If the value of UTHV and LTHV are higher than the input noise voltage, the positive feedback will eliminate the false output transitions. With the help of positive feedback and its regenerative behavior, the output voltage will switch fast between the positive and negative saturation voltages. 1.13.1 HYSTERESIS CHARACTERISTICS

Since a comparator circuit with a positive feedback is used, a dead band condition hysteresis can occur in the output. When the input of the comparator has a value higher than UTHV , its output switches from

satV+ to satV− and reverts back to its original state satV+ , when the input value goes below LTHV . This is shown in the figure below. The hysteresis voltage can be calculated as the difference between the upper and lower threshold voltages.

hysteresis UTH LTHV V V= −

1.14 MULTIVIBRATORS A multivibrator is an electronic circuit used to implement a variety of simple two-state systems such as oscillators, timers and flip-flops. It is characterized by two amplifying devices (transistors, electron tubes or other devices) cross-coupled by resistors or capacitors. 1.14.1 ASTABLE MULTIVIBRATOR

The non-sinusoidal waveform generators are also called relaxation oscillators. The op-amp relaxation oscillator (as table multi vibrator) shown in figure is a square wave generator. The circuit’s frequency of oscillation is dependent on the charge and discharge of a capacitor C through feedback



12

resistor R. The “heart” of the oscillator is an inverting op-amp comparator. The comparator uses positive feedback that increases the gain of the amplifier. In a comparator circuit positive feedback offers two advantages. First, the high gain causes the op-amp’s output to switch very quickly from one state to another and vice-versa. Second, the use of positive feedback gives the circuit hysteresis. In the op-amp square-wave generator circuit given in figure, the combination of R and C acting as a low-pass R-C circuit is used to integrate the output voltage oV and the capacitor voltage cV is applied to the inverting input terminal in place of external signal. The differential input voltage is given as

in c 2V V V= −Where, inV is the difference in voltages at the input terminals.

2V is the voltage at non-inverting input

2V may be either UTHV or LTHV . The time period, T, of the output square wave is determined using the charging and discharging phenomena of the capacitor C.

The frequency 1fT

= , of the square-wave

is independent of output voltage oV . This circuit is also known as free-running or as table multi vibrator because it has two quasi-stable states.

1.14.2 MONOSTABLE MULTIVIBRATOR

A mono stable multi vibrator (MMV) has one stable state and one quasi-stable state. The circuit remains in its stable state till an external triggering pulse causes a transition to the quasi-stable state. The circuit comes back to its stable state after a time period T. Thus it generates a single output pulse in response to an input pulse and is referred to as a one-shot or single shot multi vibrator. Mono stable multi vibrator circuit illustrated in figure is obtained by modifying the as table multi vibrator circuit by connecting a diode D across capacitor C so as to clamp CV at

dV during positive excursion. Under steady-state condition, this circuit will remain in its stable state with the output o satV V= + and the capacitor C is clamped at the voltage dV (on-voltage of diode dV 0.7V)= . The circuit can be switched to the other state by applying a negative pulse to the non-inverting (+)input terminal. When a trigger pulse is applied, output goes to satV− . The capacitor C now charges exponentially with a time constant fR Cτ =toward satV− (diode Dl being reverse-biased). When capacitor voltage CV becomes more negative than LTHV , output swings back to satV+ . The capacitor now charges towards satV− till CV attain dV and capacitor C becomes clamped at dV . The width of the trigger pulse PT must be much smaller than the duration of the output pulse generated i.e. PT «T . For



13

reliable operation the circuit should not be triggered again before T.

1.15 SLEW RATE The Slew Rate of an op amp describes how fast the output voltage can change in response to an immediate change in voltage at the input. The higher the value (in V/µs) of slew rate, the faster the output can change and the more easily it can reproduce high frequency signals. e.g. If a square wave is applied to the input of the op amp, the output should also be a square wave. However the fast rising and falling edges of the square wave can tend to cause the amplifier to oscillate for a short time after the rise or fall. The slew rate also affects sine wave (and audio) signals as well as square waves. The rate of change of voltages in a sine wave is continually varying, it is changing at its fastest rate as the signal voltage crosses zero, and the rate of change falls momentarily to zero (no change) at both the positive and negative peaks of the wave. If the slew rate of theamplifier cannot keep up with the fastest rate of change of the signal, some distortion will be produced. Therefore, to be sure of amplifying large amplitude signals that are most likely to produce large (and fast) rates of voltage change, an op amp needs to have

a sufficiently high value of slew rate to cope with the greatest possible rate of voltage change. If the largest possible voltage swing and the highest frequency of the signal are known, the minimum required slew rate for the op amp can be calculated using the formula:

PVSlew rate 2 fVsec

= π µ

Where f = the highest signal frequency (Hz) and

PV = the maximum peak voltage of the signal. For example if an op amp is to amplify a signal with peak amplitude of 6 volts at a frequency of 40 kHz, an op amp with a slew rate of at least 32 40 10 6 1.5V / µsπ× × × = would be required. 1.16 CMRR In the previous analysis we considered that an OP-AMP generates only a differential output but in practice the output is sum of differential & common mode output.

Where,

dA is differential gain

cA is common mode gain

d 2 1V (V V )= −

1 2c

(V V )V2+

=

CMRR of op-amp is the ratio of the differential mode gain and common mode gain.

d

c

i.e. MRR ACA

=

For ideal operational amplifier cA 0→ , hence CMRR →∞



14

Note:

For an emitter coupled differential amplifier, the differential gain s independent of ER while the common mode gain is inversely proportional to

E dE

1R i.e.AR

∝ . For high CMRR, the value of

ER must be high. Sometimes a constant current source is used in place of ER .

1.17 PARAMETERS RELATED TO OP-AMP

1) Input offset voltage:Ideally the output of the op amp shouldbe at zero volts when the inputs aregrounded. In reality the input terminalsare at slightly different dc potentials.The input offset voltage is defined asthe voltage that must be appliedbetween the two input terminals of theop amp to obtain zero volts at theoutput.

2) Input offset current:

The input offset current ioI is the difference between the currents into inverting and non-inverting terminals of a balanced amplifier.

io B1 B2I | I –I |=

1) Input bias current:The input bias current BI is the averageof the current entering the inputterminals of a balanced amplifier i.e.

( )B1 B2B

I II

2+

=

2) Output offset voltage:The voltage difference between outputterminal of OP-AMP & ground whenboth the inputs are grounded is calledoutput offset voltage.

a) The output offset voltage due to inputoffset voltage is given by oo OL ioV A V= ×

b) The output offset voltage due to inputbias current is given by

oo B fV I R= ×



15

Q.1 The ideal OP –Amp has the following characteristics. a) i 0R ,A ,R 0= ∞ = ∞ =b) i 0R 0,A ,R 0= = ∞ =c) i 0R ,A ,R= ∞ = ∞ = ∞d) i 0R 0,A ,R= = ∞ = ∞

[GATE –2001]

Q.2 The inverting OP-AMP shown on the figure has an open- loop gain of 100. The closed loop gain 0 sV /V is

a) -8 b)-9 c)-10 d)-11

[GATE –2001]

Q.3 In the figure assume the OP- AMPs to be ideal. The output 0V of the circuit is

a) 10cos(100 )t

b) ( )t

0

10 cos 100 dτ τ∫

c) ( )t

4

0

10 cos 100 d− τ τ∫

d) ( )4 d10 cos 100tdt

−

[GATE –2001]

Q.4 A 741-type op-amp has a gain- bandwidth product of 1 MHz . A non –inverting amplifier using this op-amp and having a voltage gain of 20 dB will exhibit a- 3-dB bandwidth of a) 50 kHz b) 10kHz

c) 1000 kHz17

d) 1000 kHz7.07

[GATE –2002]

Q.5 An amplifier using an op-amp with a slew rate SR=1V/μsec has a gain of 40dB. If this amplifier has to faithfully amplify sinusoidal signals from dc to 20 kHz without introducing any slew- rate induced distortion, then the input signal level must not exceed. a)795 mV b) 395mVc)79.5mV d) 39.5mV

[GATE –2002]

Q.6 If the input to the ideal comparator shown in the figure is a sinusoidal signal of 8V (Peak to peak) without any DC component, then the output of the comparator has a duty cycle of

a)1/2 b)1/3 c)1/6 d)1/12

[GATE –2003]

Q.7 If the differential voltage gain and the common mode voltage gain of a differential amplifier are 48dB and 2dB respectively, then its common mode rejection ratio is a) 23dB b) 25dBc)46dB d)50dB

[GATE –2003]

GATE QUESTIONS(EC)

© Copyright Reserved by Inspiring Creativity & Enedavour Gate Institute No part of this material should be copied or reproduced without permission 16

Q.8 If the op- amp in the figure is ideal, the output voltage Vout will be equal to

a)1V b) 6Vc)14V d)17V

[GATE –2003]

Q.9 Three identical amplifiers with each one having a voltage gain of 50, input resistance of 1kΩ and output resistance of 250Ω , are cascaded. The open circuit voltage gain of the combined amplifier is a) 49 dB b) 51 dBc)98 dB d)102dB

[GATE –2003]

Q.10 The circuit in the figure is

a) low pass filterb)high- pass filter c) band-pass filterd)band –reject filter

[GATE –2004]

Q.11 In the op- amp circuit given in the figure, the load current Li is

a) s

2

V-R

b) s

2

VR

c) s

L

V-R

d) s

1

VR

[Gate–2004]

Q.12 The input resistance iR of the amplifier shown in the figure is

a) 30 kΩ4

b)10kΩ

c) 40kΩ d) infinite[GATE –2005]

Q.13 The voltage 𝑒𝑒0 indicated in the figure has been measured by an ideal voltmeter. Which of the following can be calculated?

a) Bias current of the invertinginput only

b) Bias current of the inverting andnon- inverting inputs only

c) Input offset current onlyd) Both the bias currents and the

input offset current[GATE –2005]

Q.14 The OP-amp circuit shown in the figure is a filter. The type of filter and its cutoff frequency are respectively



17

a) high pass, 1000 rad/sec.

b) low pass, 1000 rad/sec c) high pass ,10000 rad/sec d) low pass, 10000 rad/sec

[GATE –2005] Q.15 For the circuit shown in the

following figure, the capacitor C is initially uncharged. At t=0, the switch S is closed. The voltage cV across the capacitor at t=1 millisecond is

In the figure shown above, the OP AMP is supplied with ±15V a)0 Volts b)6.3 Volts

c)9.45Volts d)10Volts [GATE –2006]

Q.16 For the Op- Amp circuit shown in

the figure 0V is

a) -2V b) -1V c) -0.5V d) 0.5V

[GATE –2007]

Q.17 In the Op- Amp circuit shown assume that the diode current follows the equation s TI=I exp(V/V ).For i 0 01V =2V,V =V and for

i 0 02V =4V,V =V . The relationship between 01V and 02V is

a) 02 01V = 2V b) 2

02 01V =e V c) 02 01V =V In2 d) 01 02 TV -V =V In2

[GATE –2007] Statement for linked Answer Questions 18 & 19 Consider the Op- Amp circuit shown in the figure.

Q.18 The transfer function 𝑉𝑉0(𝑠𝑠)/𝑉𝑉𝑇𝑇(𝑠𝑠) is

a) 1-sRC1+sRC

b) 1+sRC1-sRC

c) 1

1-sRC d)

11+sRC

[GATE –2007] Q.19 If,

( ) ( )i 1 0 2V =V sinsin ωt andV =V sinsin ωt+Φthen the minimum and maximum values of ϕ (in radians) are respectively

a) -π πand2 2 b) π0and 2

c) -πand0 d) -π and02

[GATE –2007]



18

Q.20 Consider the following circuit using an ideal OPAMP. The I-V characteristics of the diode is described by the relation

( )vvT

oI=I e -1 where

T oV =25mV,I =1μA and V is the voltage across the diode (taken as positive for forward bias)

For an input voltage iV =-1V, the output voltage 0V is a)0V b)0.1V c)0.7V d)1.1V

[GATE –2008]

Q.21 The OPAMP circuit shown above represents a

a)High pass filter b)Low pass filter c)Band pass filter d)Band reject filter

[GATE –2008]

Q.22 Assuming the OP-AMP to be ideal, the voltage gain of the amplifier shown below is

a) 2

1

R-R

b) 3

1

R-R

c) 2 3

1

R ||R-R

d) 2 3

1

R +R-R

[GATE –2010]

Q.23 The transfer characteristic of the precision rectifier circuit shown below is (assume ideal OP-AMP and practical diodes)

a) b)

c) d) [GATE-2010]

Q.24 The circuit below implements a filter between the input current 1 and the output voltage ov Assume that the opamp is ideal. The filter implemented is a

a)low pass filter b)band pass filter. c)band stop filter d)high pass filter

[GATE –2011]

Q.25 The circuit shown is a



19

a) low pas filter with

( )3dB1 2

1f = rad/sR +R C

b) High pass filter with

3dB1

1f = rad/sR C

c) Low pass filter with

3dB1

1f = rad/sR C

d) High pass filter with

( )3dB1 2

1f = rad/sR +R C

[GATE –2012] Q.26 In the circuit shown below the op-

amps are ideal .The outV in Volts is

a)4 b)6 c)8 d)10

[GATE –2013] Q.27 In the low-pass filter shown in the

figure, for a cut-off frequency of 5kHz, the value of ( )2R in kΩ is ____.

[GATE-2014]

Q.28 In the voltage regulator circuit

shown in the figure, the op-amp is

ideal. The BJT has BEV 0.7V=and 100β = , and the zener voltage is 4.7V. For a regulated output of 9 V, the value of R (inΩ) is ________.

[GATE-2014]

Q.29 In the circuit shown, the op-amp has

finite input impedance, infinite voltage gain and zero input offset voltage. The output voltage Vout is

a) ( )2 1 2—I R R+ b) 2 2I R

c) 1 2I R d) ( )1 1 2-I R R+ [GATE-2014]

Q.30 In the differential amplifier shown

in the figure, the magnitudes of the common-mode and differential-mode gains are cmA and d,Arespectively. If the resistance ER is increased, then

a) cmA increases



20

b) common-mode rejection ratioincreases

c) dA increasesd) common-mode rejection ratio

decreases[GATE-2014]

Q.31 Assuming that the Op-amp in the circuit shown is ideal, Vo is given by

a) 1 25 V 3V2

− b) 1 25ZV V2

−

c) 1 23 7V V2 2

− + d) 1 213V 1V2

− +

[GATE-2014]

Q.32 The circuit shown represents:

a) A bandpass filterb) A voltage controlled oscillatorc) An amplitude modulatord) A monostable multivibrator

[GATE-2014]

Q.33 In the op-amp circuit shown, the Zener diodes Z1 and Z2 clamp the output voltage 0V to 5V or 5V+ −The switch S is initially closed and is opened at time t 0.=

The time 1t t= (in seconds) at which

0V changes state is ___________. [GATE-2016]

Q.34 An op-amp has a finite open loop voltage gain of 100. Its input offset voltage ( )ios mV 5 V= + is modeled as shown in the circuit below. The amplifier is ideal in all other respects. inputV is 25 mV

The output voltage (in millivolts) is ___________.

[GATE-2016]

Q.35 For the circuit shown in the figure, R1=R2=R3=1Ω, L=1µH and C=1µF. If the input Vin=cos(106t), then the overall voltage gain (Vout/Vin) of the circuit is ______

[GATE-2016-02]

Q.36 For the operational amplifier circuit shown, the output saturation voltages are ±15V. The upper and lower threshold voltages for the circuit are, respectively,



21

a) +5V & -5Vb) +7V & -3Vc) +3V & -7Vd) +3V & -3V

[GATE-2017-01]

Q.37 The amplifier circuit shown in the figure is implemented using a compensated operational amplifier (op-amp), and has an open loop voltage gain, A0=105 V/V

[GATE-2017-01]

Q.38 In the voltage reference circuit shown in the figure, the op-amp is ideal and the transistors Q1 and Q2,…….,Q32 are identical in all respects and have infinitely large values of common-emitter current gain (β) . The collector current (Ic) of the transistors is related to their base-emitter voltage (VBE) by the relation IC=IS exp (VBE/VT), where IS is the saturation current. Assume that the voltage VP as shown in figure is 0.7 V and the thermal voltage VT=26mV

The output voltage VOUT (in volts) is _________

[GATE-2017-02]

Q.39 In the circuit shown below, the op- amp is ideal and Zener voltage of the

diode is 2.5 volts. At the input, unit step voltage is applied i.e.

( ) ( )inv t u t= volts. Also, at t = 0 thevoltage across each of the capacitors is zero.

The time t (in msec), at which the output voltage ( )outv t crosses -10volts is a)2.5 b) 5

c)7.5 d)10

[GATE-2018]

Q.40 An op-amp based circuit is implemented as shown below.



22

In the above circuit, assume the op- amp to be ideal. The voltage (in

volts, correct to one decimal place) at node A, connected to the negative input of the op-amp as indicated in the figure is _______.

[GATE-2018]

ANSWER KEY:

1 2 3 4 5 6 7 8 9 10 11 12 13 14 (a) (b) (a) (b) (c) (b) (c) (b) (c) (a) (a) (b) (c) (a) 15 16 17 18 19 20 21 22 23 24 25 26 27 28 (d) (c) (d) (a) (c) (b) (b) (a) (b) (d) (b) (c) 3.18 1093 29 30 31 32 33 34 35 36 37 38 39 40 (c) (b) (d) (d) 0.789 413.79 -1 (b) 44.4 1.145 (c) 0.5



23

Q.1 (a)

Q.2 (b) If open loop gain is not infinite, then

f

1

R1 10k=- =- =-10β R 1k

1β =10

f-A -100 100A = = =-11+Aβ 111+100×

10fA -9≅

Q.3 (a)

KCL at node 1, 2

s

V -ωL=V R

-3-100×10×10 1= =-10 10

s2

VV =- =-cos100t10

0

2

V -1/ωc=V 100

-6

1=- =-10100×10×10 ×100

0 2V =-10V =-10(-cos100t)

0V =10cos100t

Q.4 (b) 6Gain×BW=1×10

6 61×10 10BW= =Gain 10

5=100k=10 20logx=20dB x=10

Q.5 (c) Slew rate m=A.2πfV

mV=AV sinωt

mdV =AV ωcosωtdt

m mmax

dV =SR=AV 2πfdt

20logx=40 x=100=A

mm

S.RV =A.2πf

⇒

-6 3

1=10 ×100×2π×20×10

mV =79.5mV

Q.6 (b)

So, iV =4sinωtAt iV =2

1sinωt=2

⇒πωt=6

Another crossover at Duty cycle

on

4π5π π-T 166 6= = = =T 2π 2π 3

Q.7 (c) d cCMRR=20logA -20logA

=48dB-2dB=46dB

EXPLANATIONS



24

Q.8 (b)

F F0

1 1

R R 8V =- ×2+ 1+ . ×3R R 9

8=-5×2+6×3

0V =6V

Q.9 (c)

4v

1

VA =V

34 2v

3 2 1

VV VA = × ×V V V

⇒

Voltage across 1k after 1st stage 11000×50V= =40

1250

Similarly 3

2

V =40V

4vA =40×40×50=8×10∴

vA in ( )4dB=20log 8×10 =98dB

Q.10 (a)

At 0

in

Vω= , =0V

∞

And at 0

in

Vω=0, =1V

Q.11 (a)

0

2 L 2 2

VV V V+ + =R R R R

0

2 L 2

V2V V+ =R R R

--------(i)

s 0

1 1

V -V V-V=R R

s 0V -2V=-V ------- (ii) Putting 0V from (i)

s

2 2 L

-V +2V 2V V=+ +R R R

sL L

L 2 L

VV Vi = =- = =iR R R

Q.12 (b) Connect a sV voltage source across inverting terminal of op-amp

By virtual short AV =0V

S Ai

V -VI =10kΩ

= S SV -0 V=10kΩ 10kΩ

So, Si

i

VR =I

=10kΩ

Q.13 (c)

1 11 B 2 1 BV =-l ×1M,V =V =-l ×1M(due to virtual ground) Drop in feedback resistor

2B1M=l ×1M



25

20 2 Be =V +l ×1M

1 20 B Be =-l ×1M+l ×1M

( )2 10 B Be = l -l ×1M

here ( )2 1B Bl -l is offset current

Q.14 (a) Since output is taken across 10kΩ it is a high pass filter. Input is at non-inverting point . So,

Frequency 1=RC

3 -6

1=1×10 ×1×10

=1000rad/sec

Q.15 (d)

Voltage at inverting terminal - +V =V =10V

∴ Current through resistance,

R10i = =10mA1K

∴ Current through capacitor C Ri =i =10mA

∴ Capacitor voltage C1V = idtC ∫

-3 -3-6

1= ×10 ×10 ×1010

=10V

Q.16 (c) Using voltage division rule

( )0-2 1V = ×1+ × 1+2 =-0.5V1 1+1

Q.17 (d)

Current through diode invI=R

0T

-VV

0I=I e∴

When 01

T

-VV

i 02 2V =2,I= =I eR R⇒ ---(1)

When 02

T

-VV

i 04 4V =4,I= Þ =I eR R

-(2)

From equ (1) and (2) 02 01

T T

-V -V+V V2=e

T 01 02V In2=V -V⇒

Q.18 (a) i

0 i2VV =-V +

CSR+1

i1-CSR=V1+CSR

0

i

V (S) 1-CSR=V (S) 1+CSR

∴

Q.19 (c) Phase shift -1Φ=-2tan ωRC So minimum phase when

minω=0,Φ =0Max phase when maxω= ,Φ =-π∞

Q.20 (b)

( )vvT

oI=I e -1

Where 1I= =10μA100K

and oI =1μA

⇒ Voltage across diode =60mV0V =4K×10μ+60m∴

=0.04+60mV =0.1V

Q.21 (b) At low frequency, capacitor is open

and inductor short so, 20 i

1

-RV = VR

At

high frequency capacitor is short and inductor open so, 0V =0 so it is low pass filter

Q.22 (a)



26

i 1 1V =I ×R

i1

1

VI =R

⇒

Also 1 2 2 3I R +I R =0

2 i 22 1

3 1 3

R -V ×RI =-I × =R R R

⇒

So, 0 2 3V =I ×R 2i

1

R=-V ×R

o 2v

i 1

V -RA = =V R

⇒

Q.23 (b) When i 2V >-5=D if forward biased &

0V =0 When i 2V <-5V=D is off & 1D is ON So, at i 0V =-10V,V +5V

Q.24 (d) At Lω=0;X =ωL=0 Hence circuit can be redrawn as below

oV =0∴ At Lω= ;X =∞ ∞Hence circuit can be redrawn as below

o 1 LV =R i∴Hence given circuit is a high pass filter

Q.25 (b) TV=V =0

inin out

1

VI = =I1R +CS

⇒

2 inout 2 out

11

-R VV =-R I = 1R +C S

⇒

out 2 1

in 1 1

V -R C S=V 1+R C S

⇒

High pass Fitter with

3dB1

1f = rad/secR C

Q.26 (c)

Gain of stage II f

I

1+R 1+1= = =2R 1

0V =4V×2=8V∴

Q.27 (3.18) f 5KHz= Cut off frequency (LPF)

2

12 R C

5KHzπ

=

2 3 9

1R 3.18k2 5 10 10 10π −⇒ = =

× × × ×Ω

Q.28 (1093)



27

GivenBEV 0.7V, 100, Vz 4.7V,β= = =

0V , 9V=

RV 9 RR 1K

= ×+

R ZR V V

R 14.7 9 (

K)∴= =

+×

R 1093= Ω

Q.29 (c) Given, Zi =∞

L0A = ∞

0iV 0=

( )2 1 2 1V R / R I=

1 21 ..(1)

1 2

R R IR R ……+

=

KCL at inverting node 2 02

i1 2

V VV 0( Z )R R

−+ = ∴ = ∞

02

2 1 2

V 1 1VR R R

= +

0 1 2 2 11

2 1 2 1 2

V R R R RIR R R R R

+= +

0 1 2V =I R⇒

Q.30 (b) dA does not depend on ER

cmA . decreases as ER is increased

d

cm

ACMRR increasesA

∴ = =

Q.31 (d) Virtual ground and KCL at inverting terminal gives

2 02 1 2 V VV V V 0R 2R 3R

−−+ + =

0 2 2 2 1V V V V V3R R 3R 2R R

= + + −

0 1 211V 3V V2

= − +

Q.32 (d)

Q.33 (0.789) For t 0< switch is closed ( )V 10V− =

( )( )1 5 1VV

1 4+ =+

− = −

For t 0≥ the capacitor charges through 10kΩ the switching will occur. When ( )V 1− < − volt equivalently, the switching will occur. When cV becomes slightly more than 11V

( )t

RCcV t 20e

−

=1t

RC20e11−

=

( )120 20t RC ln9 9

1 In =

=

1 0.7 ct 89 se=

Q.34 (413.79) The gain of the practical op-amp

f

1out

in f

1

02

R1RV

V R1R

1A

+

=

+ +



28

f02

1

R1 16,A 100R

+ = =

[ ]

f

1out in ios

f

1

02

out

R1RV V V ]

R1R

1A

16V 25 5161100

413.79mV

+

= = + + +

⇒ = ++

=

Q.35 -1

( ) 011

i

VH sV

=

1R1sL

= +

1

11 sLR

= +

6

11s 10−= +×

( ) 02

01

VH sV

=

3

2

RR Cs 1

Cs

= −+

3

2

sR C1 sR C

= −+

Cs1 Cs−

=+

111

Cs

−=

+

( ) ( ) ( )1 2H s H s H s=6

6 6

1 s 1 101s 10 1 s 10

−

− −

− × × = + × + ×

1= −

Q.36 (b)

01

3 10 V 5V15

× + ×=

06 V3+

=

UT6 15V

3+

=

LT6 15V 3V

3−

= = −

Q.37 44.4

Feedback factor 1

1 2

R 1R R 80

β = =+

0of

0

AA 801 A

=+ β

( )'c c 0f f 1 A= + β

5108 1 Hz80

= +

10008Hz=

Gain at f 15kHz 15000Hz= = is

0ff 2

'c

AAf1f

=

+

2

80

15000110008

= +

Q.38 1.145 Figure

KCL at a 0 x xV V V 0.720 5− −

=

0 x xV V 4V 2.8− = −

0 xV 5V 2.8= −

1I 31I=x T P TV /V V /V

s sI e 31I e=

x P

T T

V Vln 31V V

= +



29

x P

T

V V ln 31V−

=

xV 0.789=

0V 5 0.789 2.8 1.145V= × − =

Q.39 (c) Given: Op-amp and zener are ideal.

zV 2.5V=

( ) ( )1 2C CV 0 V 0 0− −= =

At t =0 , unit step voltage is applied and we have to find time ‘t’ for which 0V 10V= −

At t =0 , when switch is closed, initially zener will be open circuited and remains same till the voltage Across 2C becomes greater than its breakdown voltage i.e. 2.5 volts.

If we write KCL at node A,

c1 0I I 1mA1K−

= = =

We can see that current through both the capacitors is constant and hence it is the case of linear charging of capacitors. As the initial voltage are zero, hence voltage across 1C and 2C for t 0> are given as,

( ) [ ]1

tt

C c 01 0

1V t I dt 1000 tC

= =∫

( ) [ ]2

tt

C c 02 0

1V t I dt 1000 tC

= =∫

We can write KVL equation starting from point A and ending at output

0V as,

1 2A c c 0V V V V 0− + + + =

[where AV 0= ]

( )1 20 c cV V V= − +

At t =2.5msec

( ) ( ) [ ]3

1 2

2.5 10c c 0

V t V t 1000 t 2.5V−×= = =

Hence, at t =2.5msec, breakdown of zener occurs and

2cV is now fixed at

2.5 volts.

Voltage across 1C will further increases linearly with time from 2.5 volts.

( )1 20 c cV V V= − +

( )10 c zV V V= − +

[As after t = 2.5msec, ( )2CV V z= ]

( )1c10 V 2.5= − +



30

1CV 7.5V=

Hence, output will be – 10 V when voltage across 1C will be 7.5 volts

As 1C is charging linearly with a rate of 1 V/sec, hence time taken by it to get charged upto 7.5 V is t =7.5msec is charging linearly with a rate of 1 V/sec, hence time taken by it to get charged upto 7.5 V is t =7.5msec

Q.40 0.5 Given: Op-amp is ideal and saturation value of output voltage is 15V.

We have to find potential at node A, which seems to be 0V according to vertical ground

To check validity of virtual ground concept for the given case, where output gets saturated, we find output of inverting amplifier as,

f0 in

RV VR

= − ×

031V 1 31V1

= − × = −

But from the given data, Maximum value of output

satV 15V= ± = ±

As 0 satV V>

Hence actual output will get saturated at

0V 15V= −

Hence, we can’t take potential at node A, AV 0= as op-amp is under saturation. As op-amp is under saturation. To find potential at A, writing KCL at node A :

A 0A V VV 1 01 31

−−+ =

( ) ( ) A A31 V 1 V 15 0− + − − =

A32V 31 15= −

A16V 0.5V32

= =



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ANALOG CIRCUITS · 2020. 1. 6. · 5. FET ANALYSIS. 5.1 Introduction 137 5.2 JFET Common Source...

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Transcript of ANALOG CIRCUITS · 2020. 1. 6. · 5. FET ANALYSIS. 5.1 Introduction 137 5.2 JFET Common Source...