Analog Baseband Implementation of a Wideband Observation ...

Master of Science Thesis in Electrical EngineeringDepartment of Electrical Engineering, Linköping University, 2016

Analog BasebandImplementation of aWideband ObservationReceiver for RFApplications

Gustaf Svensson

Master of Science Thesis in Electrical Engineering

Analog Baseband Implementation of a Wideband Observation Receiver for RFApplications

Gustaf Svensson

LiTH-ISY-EX--16/4987--SE

Supervisor: Malik Abdul RehmanEricsson, Lund, Sweden

Mathias DuppilsEricsson, Lund, Sweden

Examiner: Atila Alvandpour prof.isy, Linköpings universitet

Division of Integrated Circuits and SystemsDepartment of Electrical Engineering

Linköping UniversitySE-581 83 Linköping, Sweden

Copyright © 2016 Gustaf Svensson

Abstract

During the thesis, a two-staged analog baseband circuit incorporating a passiveanalog filter and a wideband voltage amplifier were successfully designed, im-plemented in an IC mask layout in a 65nm CMOS technology, and joined witha previously designed analog front-end design to form a wideband observationreceiver. The baseband circuit is capable of receiving an IF bandwidth up to 990MHz produced by the analog front-end using low-side injection. The final cir-cuit shows high IMD3 of at least 90 dBc. The voltage amplifier delivers a voltageamplification of 15 dB with around 0.08 dB amplitude precision over the band-width, while the passive filter is capable of a passband amplitude precision of0.67 dB over the bandwidth, while effectively suppress signal images created bythe mixer with at least 60 dBc. Both stages were realized in an IC mask layout, inaddition, the filter layout were simulated using an EM simulator.

iii

Acknowledgments

I would like to express my gratitude to the people at Ericsson in Lund and es-pecially to my supervisors Malik Abdul Rehman and Mathias Duppils for theirengagement and assistance in my master thesis work. I am grateful for the oppor-tunity to work together with you. I would also like to thank my family and mypartner for supporting me through this journey.

Lund, 2016Gustaf Svensson

v

Contents

Notation ix

List of Figures xi

List of Tables xiii

1 Introduction 11.1 Background of RF Design . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Objective of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . 21.3 Purpose of the Observation Receiver . . . . . . . . . . . . . . . . . 31.4 Report Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Background and Requirements 52.1 Workflow of the Observation Receiver . . . . . . . . . . . . . . . . 52.2 The Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2.1 Attenuation and the Linearity of the Front End . . . . . . . 62.2.2 Frequency, Bandwidth and LO Frequency . . . . . . . . . . 6

2.3 The Baseband Section . . . . . . . . . . . . . . . . . . . . . . . . . . 82.3.1 Suppression of the Signal Image . . . . . . . . . . . . . . . . 82.3.2 Output Signal Power . . . . . . . . . . . . . . . . . . . . . . 8

2.4 Target Specifications Summary . . . . . . . . . . . . . . . . . . . . 92.5 Some Relevant Concepts . . . . . . . . . . . . . . . . . . . . . . . . 10

2.5.1 Linear and Non-Linear Systems . . . . . . . . . . . . . . . . 102.5.2 The DPD-Algorithm . . . . . . . . . . . . . . . . . . . . . . 112.5.3 IP3 and Cascaded Stages . . . . . . . . . . . . . . . . . . . . 112.5.4 Impedance Matching . . . . . . . . . . . . . . . . . . . . . . 122.5.5 S-Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 Theory 153.1 Analog Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1.1 Evaluation of Analog Filters . . . . . . . . . . . . . . . . . . 153.1.2 Properties of Passive Analog Filters . . . . . . . . . . . . . . 163.1.3 Realization of Transmission Zeroes in Ladder Topology . . 17

vii

viii Contents

3.1.4 Component Values for Basic Passive Filter Structures . . . . 183.2 Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.2.1 Evaluation of Single Stage Transistor Amplifiers . . . . . . 223.2.2 Evaluation of Larger Structure Amplifiers . . . . . . . . . . 26

4 Baseband Design 314.1 Analog Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.1.1 Theoretical Solution and Workflow . . . . . . . . . . . . . . 314.1.2 MATLAB® Script . . . . . . . . . . . . . . . . . . . . . . . . 324.1.3 Realization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334.1.4 Filter Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 384.1.5 PEX Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404.1.6 Momentum Model . . . . . . . . . . . . . . . . . . . . . . . 40

4.2 Amplifier Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444.2.1 Evaluation of Preceding Stages . . . . . . . . . . . . . . . . 444.2.2 Amplifier Design Considerations . . . . . . . . . . . . . . . 474.2.3 Realization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484.2.4 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.3 Full Observation Receiver Chain . . . . . . . . . . . . . . . . . . . . 54

5 Results 555.1 IMD3 and Attenuator Settings . . . . . . . . . . . . . . . . . . . . . 555.2 Power Spectrum of Each Stage . . . . . . . . . . . . . . . . . . . . . 575.3 S-Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585.4 SNR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6 Discussion 616.1 Conclusions and Results . . . . . . . . . . . . . . . . . . . . . . . . 616.2 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

6.2.1 Linearity and Voltage Output . . . . . . . . . . . . . . . . . 626.2.2 In-Band Amplitude Precision . . . . . . . . . . . . . . . . . 626.2.3 Filter Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 636.2.4 Layout of Front-End . . . . . . . . . . . . . . . . . . . . . . 636.2.5 The Work In a Wider Perspective . . . . . . . . . . . . . . . 63

A Matlab Script 67

B ADE L Test bench 69

Bibliography 71

Notation

List of Notations

Notation Descrion

RF Radio FrequencyBB basebandLO Local OscillatorIC Integrated Circuits

ASIC Application Specific Integrated CircuitTDD Time-Division DuplexingFDD Frequency-Division DuplexingPA Power Amplifier

DPD Digital Pre-DistortionADC Analog-to-Digital ConverterOR Observation Receiver

dBm Decibel-milliwatts (reference 1 mW)dBV Decibel-Volts (reference 1V)dBc Decibel Relative to Carrier

Vp-p Voltage peak-to-peakIMD2 Second Intermodulation Distortion PointIMD3 Third Intermodulation Distortion Point

IP3 Third-Order Intercept PointSNR Signal-to-Noise Ratio

SFDR Spurious-Free Dynamic RangeCMFB Common Mode Feedback

NF Noise Figure

ix

List of Figures

1.1 An overview of the OR chain. . . . . . . . . . . . . . . . . . . . . . 21.2 An overview of the obsevation receiver setup. . . . . . . . . . . . . 3

2.1 The three different sections of the OR chain. . . . . . . . . . . . . . 62.2 A graphical view of how the RF, BB is mixed down using the LO. . 72.3 Example of a low pass filter attenuating the RF+LO band. . . . . . 82.4 Linear and non-linear system behavior, 1 dB compression point. . 102.5 Definition of IMD3 and IP3. . . . . . . . . . . . . . . . . . . . . . . 112.6 Reflection caused by impedance mismatch. . . . . . . . . . . . . . 12

3.1 Example of a single ended ladder network. . . . . . . . . . . . . . . 163.2 Conversion from single ended structure to balanced structure with

common mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173.3 Example of parameters of a low pass filter. . . . . . . . . . . . . . . 193.4 Common source amplifier and its equivalent small signal schematic. 233.5 Common drain amplifier and its equivalent small signal schematic. 243.6 Common gate amplifier and its equivalent small signal schematic. 263.7 A differential and a fully-differential amplifier setup. . . . . . . . . 273.8 A common mode feedback circuit. . . . . . . . . . . . . . . . . . . . 283.9 Long tailed pair with resistors and with a current mirror and an

ideal current source. . . . . . . . . . . . . . . . . . . . . . . . . . . . 283.10 Differential common gate amplifier with cross-coupled capacitors

and gate DC bias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.1 Overview of the workflow to find the optimal filter. . . . . . . . . . 324.2 The single 9th order filter schematics (no transmission zeroes) in

Cadence Virtuoso. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354.3 The single 9th order filter schematics (with transmission zeroes) in

Cadence Virtuoso. . . . . . . . . . . . . . . . . . . . . . . . . . . . 364.4 Section cut of the conductors and ground rail. . . . . . . . . . . . 384.5 MIM capacitors replaced with custom made metal plate capacitors. 394.6 The layout view of the filter. Area: 1258x679 µm2. . . . . . . . . . 394.7 VIA simulation models; Lumped, 2D and 3D distributed. . . . . . 404.8 Thick conductor simulation models; Sheet, 2D and 3D distributed. 414.9 Optimization of momentum model for L1. . . . . . . . . . . . . . 42

xi

xii LIST OF FIGURES

4.10 Momentum model layout view with updated capacitors and induc-tors. Area: 1110x614 µm2. . . . . . . . . . . . . . . . . . . . . . . . 42

4.11 The test bench of the OR chain excluding the amplifier in CadenceVirtuoso. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.12 The final differential common gate amplifier. . . . . . . . . . . . . 494.13 The proposed multistage amplifier structure. . . . . . . . . . . . . 504.14 The common source amplifier stage structure. . . . . . . . . . . . 504.15 First layout version of the differential common gate amplifier. Area:

72x24 µm2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524.16 Final layout of the differential common gate amplifier. Area: 52x24

µm2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534.17 The full OR chain in Cadence Virtuoso. . . . . . . . . . . . . . . . 54

5.1 IMD3 in dBc versus attenuation in dB and input power in dBm. . 565.2 Power spectrum for each of the stage outputs. . . . . . . . . . . . . 575.3 1 dB compression point of the complete OR chain. . . . . . . . . . 585.4 S11 input matching for different input power. (7 GHz) . . . . . . . 595.5 S22 output matching for different input power. (7 GHz) . . . . . . 59

List of Tables

2.1 An overview of the RF, LO frequency and bandwidth. . . . . . . . 72.2 An overview of the input and output signal power, voltage and

gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.3 An overview of the input and output signal power, voltage and

gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.1 Explanation of input arguments for the function “maxflat_LP”. . 334.2 Input and output results of “maxflat_LP” using ‘n’. . . . . . . . . 334.3 Input and output results of “maxflat_LP”. . . . . . . . . . . . . . . 344.4 Output of first filter simulation. . . . . . . . . . . . . . . . . . . . 354.5 Optimized circuit simulation. (no transmission zeroes) . . . . . . 364.6 Final circuit simulation. (with transmission zeroes) . . . . . . . . 374.7 PEX model simulation results of passive filter. . . . . . . . . . . . 404.8 Momentum results of filter model in Section 4.1.4. . . . . . . . . . 414.9 Simulation with the custom lumped model components. . . . . . 434.10 Filter output power relative to RF input power and attenuator set-

ting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464.11 IP3 budget at -30 dBm input, 7 GHz data measurements. . . . . . 474.12 Differential common gate amplifier results. . . . . . . . . . . . . . 494.13 Differential multistage amplifier results. . . . . . . . . . . . . . . . 514.14 Comparison of the two amplifier structures. . . . . . . . . . . . . 514.15 Comparison of amplifier schematic and layout. . . . . . . . . . . . 53

5.1 Input power with lowest usable attenuation setting and IMD3. (7GHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5.2 Single-tone test results. . . . . . . . . . . . . . . . . . . . . . . . . 575.3 S-parameter overview results. . . . . . . . . . . . . . . . . . . . . . 58

6.1 The final results from Chapter 5 of the OR circuit at input of 7GHz. (worst case input) . . . . . . . . . . . . . . . . . . . . . . . . 62

xiii

xiv LIST OF TABLES

1Introduction

1.1 Background of RF Design

In recent years, digital systems have been ruling the market of electrical devices,mainly for their resilience to noise, simpler design process and their cost-effectivemanufacturing. However, analog systems are still essential if the digital devicesare to interact with the real world. To simply describe the characteristics of ana-log networks, they always operate at certain frequency bands and vary contin-uously. In RF transceiver applications, high speed data transmission is accom-plished using analog networks. To give an example, in mobile radio applications,the analog transmission channels consist of electromagnetic waves propagatingthrough a medium.

As of present day the use of high speed data transmission, not least in mobilecommunication, has skyrocketed with the information and communication ageand is one of the fastest growing markets today. As the demands of data trans-mission in RF applications increases, operating frequencies and bandwidths in-creases with it in order to meet the requirements of future standards. Existingsolutions on the market need to be updated and research must be made to be ableto improve these designs. Analog systems are in many cases harder to design be-cause of inexact and sensitive components that cause a lot of trouble. They haveto be designed by hand, discrete values aren’t used and they are more sensitive tothe surroundings of the real world and therefore show unpredictable behavior incertain situations. This makes analog design a complicated task.

Depending on the application, a transceiver RF ASIC design architecture haveone or several receivers and transmitters that work either half or full duplexmode, meaning that they either take turns sending and receiving (half duplex), orsend and receive simultaneously (full duplex). A great deal of research and effort

1

2 1 Introduction

is placed into the design of these systems as there are a lot of uncharted areas inthe field, not at least due to the continuous rush of the technical age and Moore’slaws forthcoming. This steady road forward forces new standards of communi-cation to form, one more superior than the other, and further broadens the un-explored areas. In recent years in the area of mobile communication, a bunch ofnew standards has been introduced to the industry, while the next generation ofstandards are planned next. The successor of 3G mobile communication releasedin 2009, 4G, has taken a big step towards supporting significantly more data loadas the use of the mobile communication network has evolved beyond voice com-munication [2]. Also, 3G has been upgraded from the WSCDMA standard to theTD-SCDMA standard, which is the first big scale commercial standard using theTDD duplexing method. Already, the scope is set on the next standard, 5G, al-though its specifications is not yet defined. Nonetheless, it is vital to be in a keyposition as to define and commercialize the 5G standard.

1.2 Objective of the Thesis

The objective of this thesis is to study and design a wideband observation receiverwith high linearity in CMOS technology, suitable for use in future base stationsutilizing the next generation of mobile communication like the 5G standard. Theobservation receiver has to handle a broad bandwidth, from 280 MHz to 990MHz, as the demands on channel bandwidth and number of channels increasealong with higher operation frequencies. It also needs to have high linearity, withIMD3 as high as 90 dBc.

The observation receiver basically consists of four stages; an attenuator, a mixer,a filter and a wideband amplifier. An overview of the receiver chain is shown inFigure 1.1. This thesis focuses on the baseband part of the observation receiver,which consist of the low pass filter and the amplifier located between the mixerstage and the ADC stage. During this thesis, these stages where to be designedand simulated by themselves and additionally as a part of the whole observerreceiver chain, with the goal of fulfilling the given specifications. The wholeobservation receiver chain and its technical specifications will be described closerin Section 2.1. Another thesis project has been done in parallel [3] which coverthe observation receiver front-end section.

Figure 1.1: An overview of the OR chain.

1.3 Purpose of the Observation Receiver 3

1.3 Purpose of the Observation Receiver

The observation receiver is a part of a transceiver design which has the sole pur-pose of receiving and transmitting high frequent RF signals. Transceivers usecomponents like PA: s to amplify their signals to desired power levels. This intro-duces problems to the linearity of the whole circuit if the PA is working near itssaturation point, and should be avoided, especially when using advanced modu-lation techniques. To be able to track the output signal and compensate for thenon-linearity caused by the PA, a feedback loop consisting of an observer receivercould be used [12]. An example of this setup is shown in Figure 1.2. For this appli-cation, it tracks the output signal of the transmitter chain and converts it back tothe digital domain were the information is used to steer a DPD algorithm, whichin turn improves the linearity of the transmitter’s PA as it can run less strained.Research into these designs gives better understanding of their capabilities andfunctionality, which in turn provides insight in how they potentially could con-tribute in future designs.

Figure 1.2: An overview of the obsevation receiver setup.

From here, the observation receiver will be abbreviated OR.

4 1 Introduction

1.4 Report Overview

The chapters in this thesis is briefly described in the following section. As twoseparate baseband components are investigated and implemented, the chaptersare divided into sub-chapters, each of them focusing on the individual compo-nents.

• Chapter 2: Background and Requirements

Goes over a detailed overview of each of the stages in the OR chain, whichincludes the target specifications that should be met for each of the circuits,as well as the whole OR. It also goes through some relevant aspects aboutlinearity, impedance matching and circuit design.

• Chapter 3: Theory

Starts with explaining some of the fundamental theory behind filter designand amplifier design, then moves on to describe and compare various am-plifier design solutions relevant to the thesis. The chapter form the corner-stones of which the method chapter builds upon.

• Chapter 4: Baseband Design

Describes how the circuit design and simulations was conducted in practice.It starts with describing the theoretical background of the design and theapproach that was used to reach the objective. Then it essentially describesthe design process in detail, reaching from creating a schematic to realizeand simulate it in a layout view.

• Chapter 5: Result

Presents the results from the method chapter in a clear and objective way.This includes simulation results for the complete OR circuit.

• Chapter 6: Discussion and Conclusion

This chapter reconnects back to the initial statements and analyzes the workby going through what has been done and what could have been done better.It further puts the work in a broader perspective and discusses the aspectsof the mobile communication expansion.

• Appendix A and B

Shows a detailed overview of the Cadence Virtuoso ADE L test bench usedfor the filter simulations, and the Matlab code of a function used in its de-sign.

2Background and Requirements

As the thesis aims at creating a specific product, some initial demands on itsfunctionality were given at the start of the project. This chapter explains the basicworkflow of the OR and the target specifications. These specifications describedhere are derived from initial conditions given by Ericsson at the beginning ofthe thesis work. They form a base of which the thesis work is built upon andreferenced and reflected back to. The last section of this chapter will also gothrough some relevant notions about RF and chip design.

2.1 Workflow of the Observation Receiver

As seen in the previous work [3] the analog front end of the OR is well definedwith an R2R attenuator and a mixer. As the OR is connected to the output of thetransmitter chain, it receives a large input power. The design of an RF mixer thatcan handle such high input power and still maintain a linear behavior is almostimpossible. A variable attenuator stage is therefore added in front of the mixerto successfully bring the input power of the mixer to the edge of the linear regionstill giving an accepted output. More detailed explanation of the analog front endcomponents is given in Section 2.2. The analog baseband, covered in this thesis,will essentially make sure that the signal coming from the analog front end canbe converted to the digital domain by the ADC. The low pass filter will filter outunwanted high frequency images of the signal that was generated in the mixerstage, while the amplifier stage will restore the signal power to a level the ADCcan handle. More on that in Section 2.3. Last, the analog signal will be convertedto the digital domain by the ADC stage at the end of the OR. The three sectionsof the OR can be seen in Figure 2.1.

5

6 2 Background and Requirements

Figure 2.1: The three different sections of the OR chain.

2.2 The Analog Front End

Commonly, the section of a receiver that handles RF signals is called the frontend of the receiver. It deals with the incoming RF signal from either an antenna,or in this case direct from a transceiver, and prepare it to be down-converted bya mixer.

2.2.1 Attenuation and the Linearity of the Front End

As the OR is part of a feedback loop of the transmitter chain, the input of theOR is connected directly to the output of the transmitter chain. Thus, the inputsignal will be very strong as the output signal of the transmitter is very strong.The OR also need to cover a wide input power signal bound, stretching from -30 dBm to 1 dBm. This calculates to about -43 dBV to -12 dBV with an inputimpedance of 50 ohms. Such high input power would compromise the linearityof the mixer, therefore an attenuator stage is needed before the mixer, makingsure that the input signal into the mixer always stay in bound so that the mixermeets the linearity target.

The attenuator developed in [3] is an analog step attenuator with a 5-bit digitalinput, capable of tuning the attenuation between 0 dB to -31 dB, using 1 dB steps.It is composed of five integrated stages. The input and output are differentialwith an input/output impedance of 100 Ohms.

2.2.2 Frequency, Bandwidth and LO Frequency

The whole purpose of the OR is to pass through all the channels in feedback to geta complete coverage. At three different RF frequencies from 2 GHz to 7 GHz, theOR has to handle a bandwidth of 280 MHz to almost 1 GHz of bandwidth. Thebandwidth is mixed down to the baseband frequency using low side injection bythe mixer in [3]. Low side injection means that the LO frequency at the mixer is

2.2 The Analog Front End 7

lower than the RF signal going into it. The topology is low IF and will mix downthe signal to baseband as seen in Figure 2.2. This also means that it will createan image of the signal at the RF+LO frequency which have to be suppressed lateron.

Figure 2.2: A graphical view of how the RF, BB is mixed down using the LO.

The abbreviations RF, LO and BB in Figure 2.2 can be compared to the initial spec-ification of the RF, BB and LO frequency in Table 2.1. The baseband frequencyrange is located between the LO frequency and RF.

The mixer designed and used in [3] is a double balanced voltage mode mixer.The mixer is passive and has a differential input and output with input/outputimpedance of 100 ohms.

Table 2.1: An overview of the RF, LO frequency and bandwidth.

RF (GHz) LO (GHz) BB (MHz) Image Band (GHz)

2.0 1.72 280 3.44-3.724.5 3.86 640 7.72-8.367.0 6.01 990 12.02-13.01


2.3 The Baseband Section

The analog baseband section of the OR handles the mixed down signals from theanalog front end and prepare them for the ADC. As Section 2.2.2 points out, thetopology is low IF, meaning that the mixed down signal resides between DC anda frequency fBB = fBW were fBB is the bandwidth of the signal.

2.3.1 Suppression of the Signal Image

One of the most destructive mixer products is the RF+LO image and cause highererror rate at ADC if not removed. High demands on the passband of the wantedbaseband signal makes a low pass filter suitable. The filter stage can be placedright after the mixer. An example is shown in Figure 2.3. The RF + LO band hasto be attenuated at least 90 dBc and the passband has to have less than 0.2 dBripple to fulfill the target specifications.

Figure 2.3: Example of a low pass filter attenuating the RF+LO band.

2.3.2 Output Signal Power

Looking at the output signal power at the analog baseband, the signal is differen-tial with the initial target bounds set to 0.25 Vp-p to 0.5 Vp-p, which calculatesto about -21 dBV to -15 dBV.

A ruff estimation of the total gain range for the whole chain can be calculatedlooking at the difference between the input and output power. The OR chain hasan input impedance of 100 Ohm. At an input of -9 dBV, -6 dB gain is needed toget -15 dBV at output, while at -40 dBV input, 25 dB gain is needed to get -15dBV at output.

2.4 Target Specifications Summary 9

Table 2.2: An overview of the input and output signal power, voltage andgain.

PRF (dBm) @ 100 Ohm VRF (dBV) Gain (dB) VBB (dBV)

1 -9 -12 to -6 -21 to -15-30 -40 19 to 25 -21 to -15

2.4 Target Specifications Summary

A summarize of the target specifications of the observation receiver is shown inTable 2.3.

Table 2.3: An overview of the input and output signal power, voltage andgain.

Parameter Target

Input Frequencies (RF) 2.0 GHz, 4.5 GHz, 7.0 GHzLO Frequency 1.72 GHz, 3.86 GHz, 6.01 GHz

Bandwidth 280, 640, 990 MHzInput Signal Power -30 dBm to 1 dBm

Output signal voltage (@ ADC input) 0.25 Vp-p to 0.5 Vp-pDifferential input impedance 100 Ohms

Differential Output impedance 1000 OhmsIn band amplitude ripple ≤ 0.2 dB

In band IMD3 > 90 dBcIn band SFDR > 90 dBcIn band SNR > 50 dB


2.5 Some Relevant Concepts

This section will go through some concepts relevant to the thesis work.

2.5.1 Linear and Non-Linear Systems

A system is considered linear when the output signal of the system is constant inreference to the input signal of the system. This means that the transfer functionVoutVin

is a constant, so that the output of the system can be described as

Vout = k ·Vin + m (2.1)

Now, a non-linear system shows similar behavior as the linear system at low inputvalues, however, at a certain input signal, the output signal starts to saturateto an upper limit and the transfer function is no longer constant. It is hard todo an exact model of non-linear systems, but the output of the system can beapproximated to

Vout = a1Vin + a2V2in + a3V

3in + ... (2.2)

were the coefficients an are complex numbers. The point where the signal startsto saturate is often measured with the 1 dB compression point, which is definedas the point where the output signal has dropped with 1 dB in reference to thelinear counterpart. The 1 dB point definition is shown in Figure 2.4.

Figure 2.4: Linear and non-linear system behavior, 1 dB compression point.

2.5 Some Relevant Concepts 11

2.5.2 The DPD-Algorithm

In Section 1.3, it is explained that the OR is part of a feedback loop with the pur-pose of steering a digital pre-distortion algorithm, which in turn would improvethe linearity of the transmitter [12]. A very simple model of this algorithm canbe described with

Vout,DP D = b1Vin + b2V3in (2.3)

And the output of the DPD is the input of the non-linear system of the transmitter(or PA), which is described by Equation 2.2, hence

Vout(b1Vin + b2V

3in

)= a1b1Vin + a2b1V

2in +

(a1b2 + a3b

31

)V 3in + O

(V 4in

)(2.4)

Higher order terms discarded by big O notation. The third order term representsthe third order harmonic and is eliminated when a1b2 + a3b

31 = 0 which gives

the solution b1 = 1, b2 = − a2a1

. The DPD will however affect the higher orderharmonics, although it is discarded here (Contained by the big O notation). Thehigher order harmonics also contributes to the third order harmonic and it cantherefore never be removed completely.

2.5.3 IP3 and Cascaded Stages

A common way to measure the third order harmonic of a circuit is to use the thirdorder intercept point, or IP3. It is a virtual point defined were the wanted signalintercept the third order harmonic on an input versus output power graph. Anexample is shown in Figure 2.5.

Figure 2.5: Definition of IMD3 and IP3.


The IMD3 is defined in Figure 2.5 using a two tone setup. The IMD3 is risingwith a 3 dB or 3:1 relative to the wanted signal. As the circuit in reality is non-linear, the third intercept point will never be reached as the signal will start tosaturate before that.

When connecting multiple stages, each with their certain IP3, the total effectiveinput IP3 of the resulting chain can be described as

1I IP 3tot

=1

I IP 31+

G1

I IP 32+G1G2

I IP 33+ ... +

G1G2...Gn−1

I IP 3nn = 1, 2, ..., k. (2.5)

were I IP 3n and Gn is the IIP3 respectively the gain for the nth stage.

2.5.4 Impedance Matching

The use of impedance matching is an important aspect when designing RF sys-tems. The goal of circuit matching is to minimize signal reflection and minimizethe power transfer loss between different circuits. Suppose there is a wave mov-ing from a source impedance Z1 towards a load impedance of Z2. The reflectioncoefficient of the load impedance is then described by

Γ =Z2 − Z1

Z1 + Z2(2.6)

Γ defines how much of the incoming wave that is reflected back to the sourceimpedance. Suppose there is a voltage wave Vin moving from Z1 to Z2, the reflec-tion of the wave is VR = Vin

Z2−Z1Z1+Z2

while the forwarded wave is

VF = Vin(1 + Z2−Z1

Z1+Z2

)= Vin

2Z2Z1+Z2

.

Figure 2.6: Reflection caused by impedance mismatch.

The formula used to calculate the forward voltage can be used to calculate whenthe maximum effective power transfer occurs. First, utilizing ohms’ law, the for-ward current is IF = VF

Z1+Z2= Vin

Z1+Z2

(2Z2Z1+Z2

), which gives

PF,rms =VF√

2·IF√

2=

12Vin

(2Z2

Z1 + Z2

)·

VinZ1 + Z2

(2Z2

Z1 + Z2

)=

2 ·V 2in ·Z2

2

(Z1 + Z2)3 (2.7)

2.5 Some Relevant Concepts 13

Now, the power PF is maximized when the impedances Z1 and Z2 is equal (ifreal), or are each other’s conjugate (if complex). This gives an upper limit on themaximum transferred power to

PF,rms =2 ·V 2

in ·Z2

(2Z)3 =V 2in

4 ·Z(2.8)

2.5.5 S-Parameters

S-parameters are used to describe port networks and are most commonly usedon two-port networks to describe their abilities to transfer power and how wellthey cancel out impedance reflection. They are defined using a set of variables,an and bn, were an is wave n propagating through port n, while bn is the reflectedwave at port n. A two-port network is described with[

b1b2

]=

[S11 S12S21 S22

]·[a1a2

](2.9)

The Sn1,n2 is called the S-parameters, and are constants. They are calculated withone port at a time as

S11 = b1a1

∣∣∣∣∣a2=0

S12 = b1a2

∣∣∣∣∣a1=0

S21 = b2a1

∣∣∣∣∣a2=0

S22 = b2a2

∣∣∣∣∣a1=0

(2.10)

Using this terminology, it is easy to see what each of the parameters correspondto. Parameter S11 describes the reflection relative to the forward power at port 1,which means that it describes the input impedance matching. Parameter S12 isthe reflection at port 1 relative to the forward power of port 2, or in other words,the reverse isolation ability of the network. Parameter S21 is the output powerat port 2 relative to the input power at port 1, and measures the power transferfunction. Parameter S22 is the same as S11, measuring the relative reflection atport 2, or the output impedance matching.

3Theory

To study and reflect over existing solutions is a crucial part of the work and a keyelement to understand the deeper meaning of different solutions of the problem.This section will go through the fundamental properties and building blocks ofthe filter and amplifier components, as well as more complex structures to solvethe problem.

3.1 Analog Filters

Analog filter circuits, and especially passive analog filter circuits, takes advantageof the frequency dependent impedances of components like resistors, inductorsand capacitances to manipulate signals. This allows to be selective and filter outunwanted signals while passing wanted frequency bands.

3.1.1 Evaluation of Analog Filters

The filter configuration considered in this application is a passive analog filter. Ithas some advantages to its counterpart, the active filter design, which makes thepassive filter design favored in this practice.

• Bandwidth - The passive filter has no theoretical limitation on the band-width as no active components are used. This means that the linearity ofthe filter is not compromised and the passband fluctuations can be held toa minimum.

15

16 3 Theory

• Noise - As the filter has no active components, the only thing adding to thenoise is the thermal noise, which can be modeled by

V 2rms

4f= 4kBT R (3.1)

• Power - Passive filters doesn’t need any power supply which makes themmore reliable as they are not affected by any fluctuations in power. This alsomeans that they do not consume any power, although no gain is possible.

Despite the positive properties, the passive filter also has some limitations interms of size, flexibility and design.

• Size - Inductors are used in the design of passive filters, and they are oftenbulky and take up big chip areas, which is usually not preferred.

• Flexibility - In order to design a passive filter that is able to cover multi-ple frequency setups, like in this project, could be a troublesome task as thecomponents of a passive filter are static. This would require variable compo-nents or multiple smaller filters with switches to choose between differentfilter setups, if not a high order filter could cover all the setups.

• Design - Higher order passive filter design can be a troublesome task andthe designer needs to spend a lot of time tweaking the component values.

3.1.2 Properties of Passive Analog Filters

Passive analog filters are designed using something called ladder topology orCauer topology. Their structures can be altered in a lot of ways, but the corestructure is the same. An example of a single ended ladder network is shown inFigure 3.1.

Figure 3.1: Example of a single ended ladder network.

3.1 Analog Filters 17

As long as the input and output impedance is equal, the structure is fundamen-tally symmetric. The impedances are exchanged for different capacitance, induc-tance or resistance values depending on the wanted filter design. The structurein Figure 3.1 can easily be converted into a balanced circuit and then convertedinto a balanced circuit with common mode. This is shown in Figure 3.2.

Figure 3.2: Conversion from single ended structure to balanced structurewith common mode.

The following basic types of ladder designs are the center of interest:

• Butterworth - The Butterworth design is often called maximally flat filteras it has no ripple in the passband or the stopband. It is basically the com-mon ground for the other three types. Its transfer function only containspoles.

• Chebyshev Type I - Chebyshev I filters are very similar to the Butterworthfilter as its transfer function only contains poles and no zeroes. However, ithas one big difference; it has ripple in the passband, making the transitionband steeper.

• Chebyshev Type II - Chebyshev II filter has, in contrast to Chebyshev I,ripples in the stopband instead. This is caused by transmission zeroes in itstransfer function that will cause the amplitude response to be zero at cer-tain frequencies. The passband is similar to the maximally flat Butterworthfilter passband.

• Elliptic - Elliptic filter, or Cauer filter, is a combination of the ChebyshevI and II, introducing ripple in both the passband and stopband. This givesthe transition band maximally steep.

3.1.3 Realization of Transmission Zeroes in Ladder Topology

To fully understand how these types can be realized in a ladder topology sense,each inductor and capacitance arrangement is analyzed. In [1], this is done bylooking at the transmission zeroes induced by these arrangements. There are intotal six ways to combine L (inductor) and C (capacitor) components (s = jωbeing the Laplace transform):

18 3 Theory

• A single series capacitor or a single parallel inductor will realize a transmis-sion zero at s = 0.

• A single series inductor or a single parallel capacitor will realize a transmis-sion zero at s→∞.

• An inductor and a capacitor connected in parallel and then in series or aninductor and a capacitor connected in series and then parallel will realizetransmission a transmission zero at s = j 1√

LC.

It should be said that arrangements of only capacitors or inductors can be simpli-fied as only one component and do not add additional zeroes.

For a simple high pass filter, it is just a matter of combining series capacitorsand parallel inductors as this will place transmission zeroes at low frequenciess = 0. The same goes for low pass filters, combining series inductors with parallelcapacitors instead, placing transmission zeroes at s→∞. Last, adding either a ca-pacitance in parallel or an inductance in series to one of the existing componentswill add transmission zeroes at s=j 1√

LC. If this is added, the filter is a Chebyshev

II or elliptic filter.

3.1.4 Component Values for Basic Passive Filter Structures

Generally, when talking about filter designs, the transfer function of a filter de-scribes the frequency response of the filter. They all have some parameters thatdefine their characteristics, like cutoff frequency, passband and stopband ripple,stopband attenuation etc. See Figure 3.3.


Figure 3.3: Example of parameters of a low pass filter.

Suppose a transfer function H (jω) describe a normalized low pass filter, whichmeans that the cutoff frequency of the filter is ωc = 1. Knowing that the fre-quency response of such filter would go from 1 → 0 when ω goes from 0 → ∞,the attenuation in dB of any given frequency ω could theoretically be describedas

AdB = −20log (H (jω)) (3.2)

Now, it is easy to see that H (jω) has to be as close to 1 as possible in the passbandand as close to 0 as possible in the stopband. In [11], a characteristic function ofthe filter is defined as

|K (jω) |2 =1

H (jω)H ∗ (jω)− 1 (3.3)

So if H(s) has n poles and no zeroes (for example a Butterworth), |K(s)| representsthe complex conjugate multiplication sn. Solving Equation 3.3 for |H(jω)| gives

√H (jω)H ∗ (jω) = |H (jω) | = 1√

1 + |K (jω) |2(3.4)

so that the transfer function is dependent on K(jω). But how is this functionrelated to the attenuation in Equation 3.2? As the function is non-linear, a lowerlimit of the attenuation is set that define when the transition band starts. Upto this point, an upper limit |K(jω)| ≤ ε making |K(jω)| = εωn, is set on thecharacteristic function. Combining Equation 3.4 with Equation 3.2 using thelimit gives

20 3 Theory

AdB = −20log(

1√

1 + ε2ω2n

)⇔ ε2ω2n = 10

Aω,dB10 − 1 (3.5)

The most common limit is the Butterworth limit at ε = 1, which gives the cutoffattenuation (at ω = ωc) of AdB ≈ 3.02 dB. In a similar manner, a limit on theattenuation when the transition band ends can be set, defining a lower line ofthe stop band δ ≤ |K(jω)|. Solving Equation 3.5 for the order n at the stopbandfrequency ωs and using the fact that ε is defined at ω = ωc = 1 so that ε2 =

10Ac,dB

10 − 1,

ω2ns =

10Aωs,dB

10 − 1

10Aωc,dB

10 − 1⇔ n =

log(10

Aωs,dB10 − 1

)− log

(10

Aωc,dB10 − 1

)2 · log (ωs)

(3.6)

With Equation 3.6, the order of a simple low pass filter can be calculated whenthe passband amplitude, cutoff amplitude and the normalized frequency limit ofthe stopband is known.

Moving on to the pole placement. For a fairly simple filter construction like theButterworth filter, the Cauer topology method of calculating the desired compo-nent values for doubly terminated filters is optimal [1] [11]. It takes advantageof the fact that the poles of a Butterworth filter are located uniformly on the lefthalve of the unit circle due to stability. The component values can be describedwith

gk = 2 · sin(

(2k − 1)2n

π

)k = 1, 2, ..., n. (3.7)

for ε = 1. This derives from the fact that the poles of the filter are placed with[11]

p (k) = eiπ( 2k+n−12n ) = ieiπ( 2k−1

2n ) (3.8)

With gk being the factored coefficients for the polynomial D(s) =∏k(s − p(k)).

This is easier seen if Equation 3.7 is written in exponential representation

gk = 2 · sin(

(2k − 1)2n

π

)= ie−iπ( 2k−1

2n ) − ieiπ( 2k−12n ) (3.9)

However, gk is only used for standard low pass Butterworth filter componentcalculations with doubly terminated input/output impedances. calculated valuescan easily be modified to match other types of filters.

As Section 3.1.3 points out, arrangements of only capacitors or inductors can besimplified into one component, and for that reason the components are placedstrategically so that a capacitor always is followed by an inductor and vice versa.


If the first component is a capacitor, odd numbers of k gives capacitor values,and if the first component is an inductor, odd numbers of k are inductor values.Still, the derived component values from Equation 3.7 are normalized values andneeds to be scaled. Scaling the components are easily understandable when look-ing at their units. We want to scale the cutoff frequency ωc and the input/outputimpedance R, which has the units Hertz [s−1] respectively Ohm [Ω]. Imagine g1(which has no unit) is to be scaled as a capacitance C1 which has the unit Farad[F] =

[s + ·Ω−1

], the only thing to do is to calculate

C1 = g11

ωc ·R(3.10)

Which has the unit[konst · 1

s−1 ·Ω]

=[s ·Ω−1

]= [F]. Instead, scaling g1 as an

inductor L1 which has the unit Henry [H] = [s ·Ω], the calculation is simply

L1 = g1Rωc

(3.11)

which has the unit[konst · Ω

s−1

]= [s ·Ω] = [H].

22 3 Theory

3.2 Amplifiers

As one of the targets of this thesis is to design a differential baseband amplifierused in the OR chain, this chapter first goes through an introduction to basicamplifier structures and then move into more complex amplifier structures.

There are a lot of different forms of amplifiers, and they can effectively be dividedinto four subcategories

• Current Amplifiers - Takes an input current and gives a related amplifiedcurrent output.

• Voltage Amplifiers - Takes an input voltage and outputs a related ampli-fied voltage.

• Transconductance Amplifiers - Takes an input voltage and gives a relatedamplified current output through mutual conductance.

• Transimpedance Amplifiers - Takes an input current and outputs a relatedamplified voltage.

The focus will be on field-effect transistor amplifiers. Before different solutionsof these amplifier arrangements are discussed, Section 3.2.1 will go through thebasics of transistor amplifiers to give a mutual ground.

3.2.1 Evaluation of Single Stage Transistor Amplifiers

There are three basic single stage transistor amplifiers that can be used by them-selves or combined to create multiple transistor amplifiers. Each of them havetheir own properties but share a common topology with each other. They arecalled common source, common drain and common gate depending on which ofthe terminals of the transistor the input and output nodes have in common. Bylooking at the most basic small signal characteristics of the circuits, the type ofamplification employed by a circuit can be determined. As per definition, thecurrent gain Ai and voltage gain Av of a certain circuit can be described as

Ai ,iINiOUT

Av ,vINvOUT

(3.12)

It is also interesting to consider the input and output impedance of these circuitsto get a proper analysis. Those formulas are direct derived from Ohms law andextended to impedances as

Zin ,VIN ,ef fIIN ,ef f

Zout ,VOUT ,ef fIOUT ,ef f

(3.13)

3.2 Amplifiers 23

The Common Source Amplifier

So, the first circuit to study is the common source amplifier. A variant of thisstructure is shown in Figure 3.4. The input vIN is connected via the gate ofthe transistor while the output vOUT is connected via the drain of the transis-tor. Hence, the input and output has the source terminal of the transistor incommon. As vIN is connected to the gate, there are in theory no current flowingat the input, which makes Ai →∞ and Zin →∞ as Iin → 0.

The output impedance can be derived supposed vout = i(R//r0) · (R//r0), and i(R//r0)has to be the output current flowing through the amplifier. Thus

Zout =VoutIout

=vouti(R//r0)

= (R//r0) (3.14)

Last thing to derive is the voltage gain. From the small signal circuit, vout =−gmvgs · (R//r0) and here, the input voltage is simply vin = vgs which gives avoltage gain

Av =voutvin

=−gmvgs · (R//r0)

vgs= −gm · (R//r0) (3.15)

Figure 3.4: Common source amplifier and its equivalent small signalschematic.

To give a summation of the common source amplifier; applications it can be usedfor is either as a voltage amplifier or a transconductance amplifier consideringthe input is connected to the gate, giving the amplifier a high input impedance.

24 3 Theory

The Common Drain Amplifier

Moving on to the common drain amplifier. As the common source, the inputis connected to the gate of the transistor, resulting in Ai → ∞ and Zin → ∞ asIin → 0. The output is now however connected to the source of the transistor. Thesetup is shown in Figure 3.5. Now vout = gmvgs · (R//r0) and vin = vout + vgs =gmvgs · (R//r0) + vgs derived in the same manner as for the common source. Thevoltage amplification is

Av =voutvin

=gmvgs · (R//r0)

gmvgs · (R//r0) + vgs=

gm · (R//r0)gm · (R//r0) + 1

≈ 1, gm · (R//r0) 1

(3.16)

For the output resistance, there are resistance contributions both from (R//r0)and the transistor. This can be derived from the fact that the current flowingthrough the transistor id = gmvgs ⇔

vgsid

= 1gm

. Accordingly,

Zout =(

1gm

)//(R//r0) =

(R//r0)gm(R//r0) + 1

≈ 1gm, (R//r0) 1 (3.17)

Figure 3.5: Common drain amplifier and its equivalent small signalschematic.

To summarize, this circuit is not fit for amplification as such. Even though thecurrent amplification is high, the output impedance is really low and is not fitfor a transconductance amplifier. It has however a vital feature. Even if it has novoltage amplification, the input impedance is high while the output impedanceis low – forming a voltage buffer that can transform impedance while in theorymaintaining the voltage.

3.2 Amplifiers 25

The Common Gate Amplifier

The last fundamental single transistor amplifier stage is the common gate ampli-fier. In contrast to the other two amplifiers, the input node is now connectedto the source terminal while the output node is connected to the drain termi-nal, making the gate terminal common to the two. The setup is shown in Figure3.6. As seen in the schematic, the input and output current would be identical,making the current amplification Ai ≈ 1. The input impedance can be looked atthe same way as the common drain output impedance. iin = −gmvgs + vin−vout

r0=

gmvin + vin−voutr0

and vout = −idR = iinR, giving

iin

(1 +

Rr0

)= vin

(gm +

1r0

)⇔ vin

iin= Zin =

r0 + Rgmr0 + 1

≈ 1gm

(3.18)

assuming r0 R. The exact same relationships define the voltage gain of thecircuit

iin =voutR

= gmvin +vin − vout

r0

⇔ vout

(1R

+1r0

)= vin

(gm +

1r0

)⇔ vout

vin= Av =

gmr0R + Rr0 + R

≈ gmR

(3.19)

The last thing to derive is the output impedance. This is a bit tricky in this case,as the output impedance is dependent on the load at the input. Adding a loadRs to the equation between vin and ground will set vin = −vgs = iinRs = −ioutRs.Now, the output impedance is solved with the equation

iin = gmvin +vin − vout

r0

⇔ −iout = +gmioutRs +ioutRs − vout

r0

⇔ iout

(1 + gmRs +

Rsr0

)r0 = vout

⇔ Zout =voutiout

= r0 + Rs(gmr0 + 1)

(3.20)

26 3 Theory

Figure 3.6: Common gate amplifier and its equivalent small signalschematic.

So similar to the voltage gain of the common drain, the current gain of the com-mon gate amplifier is Ai ≈ 1. As the input impedance is quite low while theoutput impedance is high, the circuit would be functional as a current buffer.The voltage gain of the circuit is however rendering the circuit usable for volt-age amplification. The input impedance is also not really high as the other two,making input matching a simpler task.

3.2.2 Evaluation of Larger Structure Amplifiers

When amplifiers are discussed as part of RF systems they are, in addition to lin-earity and stability, compared using their abilities to have wide bandwidth andlow noise. For example, it is common in RF circuits to use a differential signal toreduce noise. Amplifier stages can either be used as a single stage, but if the gainneeds to be increased further, multiple amplifier stages could be utilized. Differ-ential amplifiers and multiple cascaded amplifier structures is discussed furtherhere.

Fully-Differential Amplifiers

In contrast to single ended circuits that use ground as reference and introducesthings like common mode noise, differential signals make use of two signals that“float” with reference to ground and the voltage difference between these two sig-nals define the wanted signal [6]. The use of differential signals greatly eliminatescommon mode noise. When talking about differential amplifiers, the most com-mon reference is the operational amplifier, which can take differential input andhave a single ended output. Fully-differential amplifiers have however a differen-tial input as well as a differential output [6]. Often, operational amplifiers use

3.2 Amplifiers 27

a negative feedback to reduce distortion and increase linearity. Fully-differentialamplifiers have instead a multiple feedback system to control the output com-mon mode voltage [6]. They often utilize a separate common mode feedback am-plifier circuit for this case. A comparison of a differential and a fully differentialamplifier is shown in Figure 3.7.

Figure 3.7: A differential and a fully-differential amplifier setup.

Now, let’s look closer at the generation of the Vocm signals in Figure 3.7. these sig-nals control to the common mode output voltage of the amplifier. To ensure thatthe common mode voltage always is stable, a common mode error feedback cir-cuit could be used [6]. It basically consists of an averaging element and a voltagecomparator. The averaging element takes the differential output of the amplifierand transform it into a single ended version. The comparator the compares thissingle ended signal with a static common mode signal to successfully get an av-erage error, which is then used as the feedback to the Vocm signals to correct thecommon mode output voltage [6]. A simple common mode feedback circuit isshown in Figure 3.8, with resistors to obtain an average input signal. Either theVout+ or the Vout− can be used as feedback, depending on the application.

28 3 Theory

Figure 3.8: A common mode feedback circuit.

Long Tailed Pair

The long tailed pair amplifier structure is arguably the most common basic dif-ferential amplifier structure and can be used with different single or differentialconfigurations. It is simply described as a differential common source amplifier,using two transistors to amplify a signal.

Figure 3.9: Long tailed pair with resistors and with a current mirror and anideal current source.

Typically, the fully differential amplifier need the CMFB circuit to stabilize itsoutput operating point [6]. In [9], a long tailed pair is used as a part of a two

3.2 Amplifiers 29

stage operational amplifier together with a differential common drain amplifierusing a shared CMFB circuit. The operational amplifier is in [9] used as part ofa channel selection filter and amplifier in a baseband application, thus having anarrow bandwidth, but high linearity and gain.

The long tailed pair structure can easily be extended to a telescopic amplifierstructure, offering increased load resistance and in some cases gives higher fre-quency response [5]. It adds a pair of p-channel transistors below the voltagesupply and a pair of n-channel transistors above the input transistors. However,due to its structure, the telescopic amplifier has decreased output swing as theadded pairs of transistors limit the voltage span of the output. The output swingcan be improved by removing the tail of the telescopic amplifier (the ideal currentsource in Figure 3.9) increasing the voltage span.

Differential Common Gate Amplifiers

Talking about wide bandwidth amplifiers, some structures and techniques arepreferred over others in RF circuits. Differential common gate low-noise ampli-fiers are considered in [13], [10]. They are in terms of their wide bandwidthand low noise capabilities superior in comparison to a common source amplifier.Both amplifiers [13], [10] employ a technique called capacitor-cross-coupled ar-rangement which greatly reduces the noise figure of the circuit by enhancing thetransconductance gm of the transistors. The arrangement also shows decreasedpower consumption.

Figure 3.10: Differential common gate amplifier with cross-coupled capaci-tors and gate DC bias.

4Baseband Design

This chapter describes the method used to create the final product. As separatecomponents were created and then put together, the chapter is divided into sep-arate design sections that goes through each component design. Last, the finalobservation receiver design will be described.

4.1 Analog Filter Design

This section goes through the approach and implementation of the analog filterdeveloped in this thesis.

4.1.1 Theoretical Solution and Workflow

A single passive filter covering all target bands was developed. The idea was touse one big high-order passive filter that would cover 280/640/990 MHz bandswhile attenuating their respective image. For this cause, the filter needs to have apassband with 0.2 dB ripple over 1-990 MHz and then a stopband attenuation of> 90 dBc at 3.44-13.01 GHz.

The basic workflow used to reach the final result is shown in Figure 4.1.

31

32 4 Baseband Design

Figure 4.1: Overview of the workflow to find the optimal filter.

There is always an upper limit on the chip area when the design is to be manufac-tured. As an increased chip area cost a lot more to produce, designers often striveminimize the number of large area components as much as possible. Passive fil-ters have a major drawback in this manner as they are partly built with inductors,which are large and bulky as they are fundamentally constructed with big coils.

4.1.2 MATLAB® Script

A Matlab® function “maxflat_LP” was written to ease the calculations of com-ponent values for LC ladders. It applies the theory of Section 3.1.4 to extractdefinite values of a maximum flat filter, or a butterworth, for a given input ofarguments. The code of the function “maxflat_LP” is shown in Appendix A. Theworkflow is basically

• Check if filter order ‘n’ input argument is given. If ‘n’ is given, the ‘as’(attenuation at stopband) input argument will be ignored. If ‘n’ is not given,apply Equation 3.6 to calculate the order ‘n’ needed to match the otherarguments.

• Calculate the number of capacitances and inductors. If the filter order isodd, the code will always prioritize using capacitors over inductors as ca-pacitors are beneficial in terms of size.

• Extract component values using a combination of Equation 3.7 with Equa-tion 3.10 and Equation 3.11 and iterating through the capacitors and induc-tors.

• Display the frequency response of the created filter using Equation 3.4.

An explanation of the input arguments of the function is shown in Table 4.1.

4.1 Analog Filter Design 33

Table 4.1: Explanation of input arguments for the function “maxflat_LP”.

Input Argument Abbrevation Unit Explanation

fc Hz Passband cutoff frequencyfs Hz Stopband start frequencyac dB Attenuation at passband cutoffR Ω Input and output impedanceas dB Attenuation at stopband startn - Filter order (OPTIONAL)

Of course, the obtained values are the theoretically perfect values for the filter,and are not optimal when physically implemented. However, they make up areally good starting point to use for further iterations to find the optimum com-ponent values.

The values are also computed for a single ended circuit. As stated in Section3.1.2, to transform the values to fit a differential circuit, the computed values aredivided in two when implemented. This transformation from single ended todifferential common mode also leads to a doubling of the number of components,i.e. twice as many inductors for the differential case.

4.1.3 Realization

The “maxflat_LP” function was initially used without specifying the filter orderargument ‘n’. The input arguments and the output results are shown in Table4.2.

Table 4.2: Input and output results of “maxflat_LP” using ‘n’.

Input Argument Value Unit

fc 990 MHzfs 3.44 GHzac 0.2 dBR 100 Ω

as 90 dB

Output Value Unit

C [0.5030 2.274 3.176 2.865 1.460] pFL [14.60 28.65 31.76 22.74 5.030] nHn 10 -

Attenuation at stopband 95 dBc

The calculated filter has a filter order of 10 and an attenuation at the stopbandof 95 dBc, which would nicely meet the specification requirements. However,


implementing this filter would require 10 inductors, consequently the next stepwas to investigate if the number of inductors in the circuit could be reduced. Thefact that there are about 5 dB of headroom on the stopband attenuation and thattransmission zeroes are to be placed in the next step to further attenuating thestopband, a filter with lower order was calculated. If the filter order would bereduced to 9, two additional inductors could be removed resulting in a total of8 inductors in the final design. Further reducing the filter order to 8 would nowremove two capacitors, then again this wouldn’t affect the total area of the circuitin a way that removing inductors would. Therefore, a filter of order 9 was to beinvestigated further. The “maxflat_LP” function was now used with a specifiedn. The input arguments and output results are shown in Table 4.3.

Table 4.3: Input and output results of “maxflat_LP”.

Input Argument Value Unit

fc 990 MHzfs 3.44 GHzac 0.2 dBR 100 Ω

as - dBn 9 -

Output Value Unit

C [0.558 2.463 3.215 2.463 0.558] pFL [16.08 30.21 30.21 16.08] nH

Attenuation at stopband 84.1 dBc

These filter values were used with the components put together to create theschematics in Cadence Virtuoso shown in Figure 4.2. The placement is the basicladder or Cauer topology, although realized in a differential with common modecircuit. There are five capacitances on each chain of the differential lines whichcontributes to the phase shift by 45 each, resulting in a 225 phase shift in total.At this point, the phase error between the differential signals are 0 % as the chainis a perfect symmetry.


Figure 4.2: The single 9th order filter schematics (no transmission zeroes) inCadence Virtuoso.

Next, a symbol of the schematics was created. ADE L was used to simulate thefilter. The test bench is made up by the filter and four ports from the “analoglib”standard library in Virtuoso. No power source is used as all the components inthe filter are passive. In ADE L, a 4-port S-Parameter analysis was made and thedifferential S-parameter signals were used to check the various properties of thefilter. In Appendix B, the various output formulas used to analyze the filter aswell as the S-Parameter analysis specifications are shown. The first run was madeand the outputs are shown in Table 4.4.

Table 4.4: Output of first filter simulation.

Parameter RF 2 GHz RF 4.5 GHz RF 7 GHz Target

S21 In-band Ripple - - 0.4269 dB < 0.2 dBS21 In-band Loss - - -1.869 dB -

Worst In-band S11 - -8.726 dB -8.726 dB < -11 dBWorst In-band S22 - -8.726 dB -8.726 dB < -11 dB

S21 @ 2 · LO -27.84 dB -127.7 dB -207.8 dB < -90 dBS21 @ RF+LO -24.85 dB -144.3 dB -220.4 dB < -90 dB

Next, iterations of multiple parameter sweep of the component values was doneto find their optimal values. To successfully find an optimal solution, the goal ofthese first parameter sweeps was to minimize the passband ripple and increasethe input/output matching of the circuits to get within the bounds. With thenew optimized values, the values from Table 4.4 are improved. The optimized


outputs are shown in Table 4.5. In this stage, the filter could be described ashaving characteristics of a butterworth filter.

Table 4.5: Optimized circuit simulation. (no transmission zeroes)


S21 In-band Ripple 0.044 dB 0.05 dB 0.091 dB < 0.2 dBS21 In-band Loss -1.589 dB -1.598 dB -1.598 dB -

Worst In-band S11 -12.8 dB -12.01 dB -12.01 dB < -11 dBWorst In-band S22 -12.8 dB -12.01 dB -12.01 dB < -11 dB


The only targets not met are the attenuation of the 3.44-3.72 GHz band. Trans-mission zeroes were now added to the circuit and were strategically placed usingvariable sweeps. The transmission zeroes were realized using the existing induc-tors in parallel with added capacitances. To keep the symmetry of the circuit,identical capacitances were added at the 1st and 4th inductor pair. The resultingcircuit is shown in Figure 4.3. This means that in total, two transmission zeroeswere added to each of the differential lines.

Figure 4.3: The single 9th order filter schematics (with transmission zeroes)in Cadence Virtuoso.

Now, with the transmission zeroes moved into place, the transition band of thefilter was sharpened to be able to properly attenuate the 3.44-3.72 GHz band. Inother words, the transmission zeroes were placed directly on top of this band.This placement of the zeroes affected the rest of the variables, leading to a new


round of iteration sweeps that had to be done for the original components, tocompensate for the added transmission zeroes. The output is shown in Table4.6. The characteristics of the filter in this stage could now be described as aChebyshev II filter, due to the transmission zeroes moved down to the stopband,creating ripples in the stopband.

Table 4.6: Final circuit simulation. (with transmission zeroes)





The single passive filter approach meets all requirements given. The numberof inductors in the circuit was successfully decreased from 10 to 8 by addingtransmission zeroes in custom places.


4.1.4 Filter Layout

The layout itself represents the geometrical outlines of the mask layers that isto be printed onto wafers as the final product. Therefore, it is essential to planthe structure in beforehand and minimize the area. As the inductor componentstake up most of the area, these were placed first. The inductor models have portson one side and were therefore faced inwards to each other and placed as in theschematic view. The conductors were then placed parallel to each other, con-necting the inductors together. A ground rail was placed between the main con-ductors to reduce parasitic capacitance between them. Multiple metal layer railswere used, decreasing the resistance of the conductors while taking advantage ofthe skin effect.

Figure 4.4: Section cut of the conductors and ground rail.

The capacitor models used were initially small MIM capacitors, and were placedin between the inductors. To decrease the influence of parasitic capacitances be-tween the capacitor and the conductor, the conductor was shaped around the in-ductor with as much distance between them as possible. Some small changes tothe MIM capacitor values were made at this stage to correct the passband ripple.The MIM capacitors were later replaced with custom made metal plate capaci-tors due to lack of compatibility with the Momentum 3D planar EM simulator(more explained in Section 4.1.6). As metal plate capacitors take up a larger areathan the small MIM capacitors, they had to be custom made to fit in between theinductors.


Figure 4.5: MIM capacitors replaced with custom made metal plate capaci-tors.

The custom made capacitors were created iteratively by gradually expanding theplate area and extrapolating the capacitance to compare it to the MIM capacitor.The metal plate capacitor itself is made of three layers of metal. M4 (green) andM2 (light blue) are connected together with VIAs around the edges, and M3 (lightpink) is located in between M4 and M2. The layout of the filter is shown in Figure4.6.

Figure 4.6: The layout view of the filter. Area: 1258x679 µm2.

The conductors and ground rail are seen in the middle, connecting the eight largeinductors. Six of the custom metal plate capacitors are easily seen, connected tothe conductors and ground rail. The additional eight plate capacitors are smaller,and located at the inputs and outputs of the filter. The total area span is 1258x679µm2. The layout where done in a 65nm CMOS technology.


4.1.5 PEX Model

From the layout of the filter, a symbol was made and a PEX model was generated.It was generated with extraction type; transistor level, distributed resistors andcaps with coupling caps and self- & mutual inductance settings (worst case). Themodel was run in same test bench as for the schematic model.

Table 4.7: PEX model simulation results of passive filter.





4.1.6 Momentum Model

The Cadence-embedded version of Momentum 3D planar EM Simulator wasused to run electromagnetic simulations on the passive filter. It uses a numeri-cal solving method to compute Maxwell’s equations over multiple parts of thelayout called meshes. Depending on the complexity of the layout, different mod-eling techniques can be used on the VIAs and the mesh-parts [7]. VIA simpli-fication is often used, merging small VIAs into some larger ones, as each meshside contributes to the matrix equation. After the simulation, S-parameters areextrapolated and used within an NPORT.

Figure 4.7: VIA simulation models; Lumped, 2D and 3D distributed.

Lumped VIA model calculate the VIA current by itself and replaces it with alumped model. The 2D-distributed model meshes each side of the via and calcu-lates the vertical current, and the full 3D-distributed model include the horizon-tal current as well [7].


Figure 4.8: Thick conductor simulation models; Sheet, 2D and 3D dis-tributed.

The sheet model calculates horizontal current for each mesh. 2D-distributed con-ductor model expand the conductors and calculate the horizontal current for eachside. The 3D-distributed conductor model include the vertical side currents aswell [7].

As the passive filter layout contains a lot of VIAs, the 2D-distributed VIA modelwas used while the 3D-distributed conductor model was used for the metal layers.In the first iteration, the filter model from Section 4.1.4 was used.

Table 4.8: Momentum results of filter model in Section 4.1.4.


S21 In-band Ripple - - 1.772 dB < 0.2 dBS21 In-band Loss - - -2.729 dB -

Worst In-band S11 - -11.45 dB -11.45 dB < -11 dBWorst In-band S22 - -11.45 dB -11.45 dB < -11 dB


As seen in Table 4.8, none of the filter goals was met at first iteration. To re-matchnew filter component values, the capacitances and the inductor momentum mod-els were individually matched to the lumped model and then put together. As anexample, in Figure 4.9 the red line is the lumped model while the yellow is themomentum model. The left graph and the right graph shows the component L1S-parameter S21 before respectively after the optimization.


Figure 4.9: Optimization of momentum model for L1.

It was shown that in reference to the momentum simulations, the lumped modelvalues were underestimated for the capacitors and overestimated for the induc-tors, leading to larger capacitors and smaller inductors. The capacitors whereagain replaced with updated custom made versions, now using M6 layers asshown in Figure 4.10. This to making the capacitors also work as the conduc-tors between the inductors.

Figure 4.10: Momentum model layout view with updated capacitors andinductors. Area: 1110x614 µm2.


The new models were now used in a new EM simulation model. The resultsare shown in Table 4.9. Targets are still not met but the in-band ripple and in-put/output matching is improved. This is discussed further in Section 6.2.3.

Table 4.9: Simulation with the custom lumped model components.






4.2 Amplifier Design

The design of the filter in Section 4.1 was pretty straight forward, as there is adistinct model to design these type of filters and using pretty few componentsin the design. Amplifier design is however a bit more complex task, as thereare various sorts of approaches that could be used to reach different types ofresults. A lot more components are usually used to design amplifiers, for exampletransistors, forming larger and more composite structures.

For this particular case it is essential to evaluate the existing OR chain up to theamplifier input, in order to outline the exact operation of this stage. After that,an amplifier stage will be designed that in the end should correspond to what isexpected.

4.2.1 Evaluation of Preceding Stages

The purpose of the amplifier is to bring the power level back to a sufficient powerlevel that can be handled by the ADC. Therefore, it is important to know the out-put power level of the signal as it has gone through all the preceding stages of theOR. As the input power of the whole OR chain is known, and the specificationsof the output voltage was set at the beginning, a simulation using the attenuator,mixer and filter stages had to be done to identify the output voltage level, or theinput power level of the amplifier. As increased gain and decreased linearity ofthe amplifier goes hand in hand, the power level need to be as large as possibleat the input without compromising the linearity of the front end.

A test bench containing the attenuator and the mixer stages from [3], and thefilter layout momentum model derived from Section 4.1.6 was created. The testbench is shown in Figure 4.11.

Figure 4.11: The test bench of the OR chain excluding the amplifier in Ca-dence Virtuoso.

4.2 Amplifier Design 45

First, a differential signal is given by the first port and fed into the attenuator.The attenuator is tunable and require a digital input which is supplied by anideal ADC shown right above the attenuator. The mixer then down converts thesignal which is fed into the filter. Last, the differential signal is picked up by thesecond port.

The attenuation setting largely affect the linearity of the mixer, so a balance be-tween the different input signals (between 1 dBm and -30 dBm) and the attenua-tor settings has to be found that maximizes the output power and still fulfill thelinearity conditions of the front end. A large simulation was made with ADE L us-ing a harmonic balance analysis. The filter output signal power in dBm is shownin Table 4.10. The columns show the RF input power in dBm, while the rowsshow the attenuator setting where for example setting 5 means an attenuation of-5 dB and so on. The red cells represent settings were the IMD3 requirement of> 90 dBc is violated.


Table 4.10: Filter output power relative to RF input power and attenuatorsetting.

Att\Input -30 -25 -20 -15 -10 -5 -0

0 -43,96 -38,96 -33,96 -28,97 -24 -19,09 -14,391 -44,95 -39,95 -34,95 -29,96 -24,98 -20,05 -15,292 -46 -41 -36 -31,01 -26,03 -21,08 -16,263 -46,83 -41,83 -36,83 -31,84 -26,85 -21,9 -17,044 -47,92 -42,92 -37,92 -32,93 -27,94 -22,97 -18,085 -48,74 -43,75 -38,75 -33,75 -28,76 -23,79 -18,886 -49,54 -44,55 -39,55 -34,55 -29,56 -24,58 -19,657 -50,27 -45,27 -40,27 -35,27 -30,28 -25,3 -20,368 -51,33 -46,33 -41,33 -36,33 -31,34 -26,35 -21,49 -52,25 -47,25 -42,25 -37,25 -32,26 -27,27 -22,31

10 -53,19 -48,19 -43,19 -38,19 -33,19 -28,2 -23,2411 -53,98 -48,98 -43,98 -38,98 -33,98 -28,99 -24,0212 -54,93 -49,92 -44,93 -39,93 -34,93 -29,93 -24,9613 -55,73 -50,72 -45,72 -40,73 -35,73 -30,73 -25,7514 -56,48 -51,48 -46,48 -41,48 -36,48 -31,49 -26,515 -57,19 -52,19 -47,19 -42,18 -37,19 -32,19 -27,216 -58,37 -53,37 -48,37 -43,37 -38,37 -33,37 -28,3917 -59,34 -54,34 -49,34 -44,34 -39,34 -34,34 -29,3518 -60,34 -55,34 -50,34 -45,34 -40,34 -35,34 -30,3519 -61,16 -56,16 -51,15 -46,16 -41,16 -36,16 -31,1720 -62,25 -57,25 -52,25 -47,25 -42,25 -37,25 -32,2521 -63,07 -58,07 -53,06 -48,06 -43,06 -38,07 -33,0722 -63,85 -58,85 -53,85 -48,85 -43,85 -38,85 -33,8523 -64,57 -59,57 -54,57 -49,57 -44,57 -39,57 -34,5724 -65,77 -60,78 -55,77 -50,77 -45,77 -40,77 -35,7825 -66,7 -61,7 -56,7 -51,7 -46,7 -41,7 -36,726 -67,64 -62,64 -57,64 -52,64 -47,64 -42,64 -37,6427 -68,43 -63,43 -58,43 -53,43 -48,43 -43,43 -38,4328 -69,41 -64,41 -59,41 -54,41 -49,4 -44,4 -39,4129 -70,21 -65,21 -60,21 -55,21 -50,2 -45,21 -40,2130 -70,96 -65,96 -60,97 -55,97 -50,96 -45,96 -40,9631 -71,67 -66,67 -61,67 -56,67 -51,67 -46,67 -41,67

The maximum output power of the three first stages is defined for each of theinput powers and is retained in the -44 dBm to -40 dBm range.


4.2.2 Amplifier Design Considerations

Next step was to find a good overview of what is expected of the amplifier, andstart the design from there. First, let’s look at the input and output matching.The filter output impedance is about 100 ohms, which means that the amplifierinput impedance is very low. The input impedance of the ADC is a bit higher,about 1K ohms, which the output impedance of the amplifier has to match. Asfor the gain, a fixed gain amplifier is sufficient in this case, as the input powerdon’t span over a large range. The amplifier has to bring the signal to a rangebetween 0.25 Vp−p to 0.5 Vp−p. This is calculated to

0.25Vp−p = −21dBVrms = −21dBm@1kΩ

0.50Vp−p = −15dBVrms = −15dBm@1kΩ(4.1)

As the input signal range is -44 dBm to -40 dBm, the total power gain needed is atleast −21dB − (−44dB) = 23dB. Then we can calculate the voltage amplificationusing

Gp = 10log

v2outRout

v2inRin

= 10log(g2v ·

RinRout

)= Gv + 10log

(RinRout

)(4.2)

As RinRout

= 0.1, there is a 10 dB difference between them, so that Gv = 33dB.

As for linearity, the input referred IP3 can be calculated with the relation

I IP 3dB = Pin,dB −IMD3dB

2(4.3)

With Pin,dB between -44 dBm to -40 dBm and a constraint on IMD3dB < −90dBcgives the I IP 3dB target range between 1 dBm and 5 dBm. However, the precedingstages need to be considered. Table 4.11 shows an IP3 budget calculated at a -30dBm input at 7 GHz. It is using formulas from Section 2.5 and values from [3].

Table 4.11: IP3 budget at -30 dBm input, 7 GHz data measurements.

Component Power Gain (dB) Power Out (dBm) IIP3 (dBm) Total Gain (dB) Casc. IIP3 (dBm) Total IMD3 (dB)

Input - -30 1000 - 0 -Attenuator -4 -34 29 -4 33 -126

Mixer -6,8 -40,8 10,5 -10,8 21,0159 -102,0318Filter -2 -42,8 120 -12,8 21,3 -102,68

Amplifier 21,8 -21 24 -9 15 -90

For an output power of -21 dBm (which is the minimum target), an IP3 of 24dB is needed for the amplifier, which is very high and hard to achieve. As thelinearity of the OR is prioritized, the gain has to be lowered if the IMD3 target isnot met.


4.2.3 Realization

Due to its low input impedance, bandwidth and voltage gain abilities, a differen-tial common gate amplifier structure was investigated to be used as a single stageamplifier and in a multistage amplifier setup. The corresponding test bench op-erated both SP, PSS and HB analyses, with a periodic ac analysis measuring thebandwidth and voltage amplification and a harmonic balance AC analysis mea-suring the IP3 of various input powers. The amplifier was simulated with a com-mon mode input voltage of 0.4 V due to the mixer output in [3]. The filter layoutmodel from Section 4.1.6 was used frequent to fully match the two basebandcomponents together.

Common Mode Feedback Circuit

The common mode feedback circuit was built in the same manner as the circuit inSection 3.2.2, but replacing the resistors in the averaging element to transistors,using its gates as input. The transistors were matched to the reference voltagetransistor to give a balanced output.

Differential Common Gate

The differential common gate was structured similar to the common gate struc-ture in Section 3.2.2 with cross-coupled capacitors. The resistors were replacedwith transistors to minimize area. A current mirror was connected at the inputto provide proper biasing for the amplifying transistors while keeping the inputload. The DC bias for the gate terminals was created using resistors (non-ideal).The common gate uses a common mode feedback circuit to keep the output com-mon mode steady. As the common gate amplifier delivers a non-inverted polar-ization of the signal, the negative output of the CMFB circuit is used.


Figure 4.12: The final differential common gate amplifier.

The optimized results of the differential common gate amplifier are shown inTable 4.12. The current mirror at the bottom is shared with the current mirrorsupplying the CMFB circuit.

Table 4.12: Differential common gate amplifier results.

Description Value

Inband IP3 @ -39 dBm to -43 dBm input -1.9 dBInband Voltage Gain 15.63 dB

Inband Ripple @ 990, 640, 280 MHz 86.7m dB, 36.4m dB, 7.0m dBInband S11 / S22 @ 990 MHz -16.1 dB / -13.9 dB

Power Consumption 2.82m WPhase Shift @ 990, 640, 280 MHz 9.9 deg, 6.4 deg, 2.8 deg

Multistage Amplifier

In [8], an LNA for a RF front end is proposed, featuring a single-ended four-stageamplifier setup. The input stage is a common gate amplifier utilizing inductorsfor input matching and power supply. The two middle stages are cascode stagesand the last stage is a common drain amplifier to match their mixer load. Thecircuit proposed here was inspired by the multistage amplifier in [8], but insteadalter it to have a differential wide bandwidth VGA for the baseband. Similar, itemploys a common gate amplifier as input to match the output load from thefilter. Instead of the cascode stages, differential common source amplifiers with


common mode feedback stages are used, and the common drain stage is removedas the input load of the ADC is higher and better matched with the last commonsource amplifier. The final structure is shown in Figure 4.13.

Figure 4.13: The proposed multistage amplifier structure.

Each of the stages were built and optimized separately before combined, andthen optimized together. The common gate stage used the same structure as inthe single amplifier stage in Section 4.2.3, while the common source stages usedthe structure in Figure 4.14.

Figure 4.14: The common source amplifier stage structure.


Table 4.13: Differential multistage amplifier results.

Description Value

Inband IP3 @ -39 dBm to -43 dBm input -4.4 dB to 2.5 dBInband Voltage Gain 19.40 dB

Inband Ripple @ 990, 640, 280 MHz 250.3m dB, 92.3m dB, 16.6m dBInband S11 / S22 @ 990 MHz -19.9 dB / -22.6 dB

Power Consumption 6.75m WPhase Shift @ 990, 640, 280 MHz 24.9 deg, 16.3 deg, 7.2 deg

Comparison of Results

The overall trend in the design of these amplifier structures was the tradeoff be-tween voltage gain and linearity. The single stage amplifier shows good stabilityand delivers the maximum voltage gain relative to the allowed IP3. The band-width ripple is about 0.1 dB and it has a low power consumption. The multistageamplifier shows in contrary higher voltage gain (still not sufficient), but an insuf-ficient IP3 over the required input power range. The bandwidth ripple is morethan doubled and the power consumption is almost tripled. Due to the insuffi-cient IP3, the single stage amplifier structure was used in the final design.

Table 4.14: Comparison of the two amplifier structures.

Description Single Stage Amplifier Multistage Amplifier

Inband IP3 @ -39 dBm to -43 dBm input -1.9 dB -4.4 dB to 2.5 dBInband Voltage Gain 15.63 dB 19.4 dB

Inband Ripple @ 990 MHz 86.7m dB 250.3m dBInband S11 / S22 @ 990 MHz -16.1 dB / -13.9 dB -19.9 dB / -22.6 dB

Power Consumption 2.82m W 6.75m WPhase Shift @ 990 MHz 9.9 deg 24.9 deg


4.2.4 Layout

In similar manner as the filter, a layout of the differential common gate amplifierwas designed also. The base of the amplifier, the amplification transistors and thebiasing transistors, were placed in a symmetrical square with metal rails at topand bottom for supply. The CMFB circuit was then added along with the currentmirror supply for both the differential common gate and the CMFB circuit. Thecapacitor models used are MIM capacitors, the same sort that were used for thefilter at the beginning. Due to large capacitor values, the capacitor areas werelarger than the rest of the structure. They were initially placed at the sides of thestructure, shown in Figure 4.15.

Figure 4.15: First layout version of the differential common gate amplifier.Area: 72x24 µm2.

To minimize the total area of the structure, the MIM capacitors were moved inand placed over the rest of the structure. This could be done as the MIM ca-pacitors are built with high order metal layers. To make sure that the capacitorsweren’t interfering with the transistors, a ground shield was added between themin form of a large area metal layer connected to ground. The last thing was to re-inforce possibly weak connections between the transistors by adding multiplemetal layer conductors between them.


Figure 4.16: Final layout of the differential common gate amplifier. Area:52x24 µm2.

The final layout area was reduced with 20x24 µm2 by moving the MIM capacitorsover the rest of the structure, giving the amplifier a total area of 52x24 µm2. APEX model of the amplifier was used in the same test bench and compared to theschematic version. The results are shown in Table 4.15.

Table 4.15: Comparison of amplifier schematic and layout.

Description Schematic Layout

Inband IP3 @ -39 dBm to -43 dBm input -1.9 dB -1.8 dBInband Voltage Gain 15.63 dB 15.31 dB

Inband Ripple @ 990 MHz 86.7m dB 108.5m dBInband S11 / S22 @ 990 MHz -16.1 dB / -13.9 dB -16.8 dB / -13.61 dB

Power Consumption 2.82m W 2.82m WPhase Shift @ 990 MHz 9.9 deg 11.1 deg

The PEX model simulations showed a slight increase in IP3 (about 0.1 dB) andvoltage gain drop of about 0.3 dB. A simulation was run together with the mo-mentum model of the filter, and showed a total of 828.7m dB ripple for the wholebaseband circuit between 1 MHz and 990 MHz. The layout where done in a 65nmCMOS technology.


4.3 Full Observation Receiver Chain

The circuit chains were connected together, meaning the analog front end devel-oped in [3] together with the analog baseband developed in this thesis, to formthe final OR. For the baseband part, the momentum model of the filter was usedtogether with the PEX model of the voltage amplifier, while the schematic viewmodels were used for the analog front end. A source resistance of 100 ohms wasused at the OR chain input, while a load resistance of 1K ohms was used at theoutput. Initial simulations showed that the dc bias of the amplifier where toohigh, resulting in a power drop in the mixer of about 10 dB. This was compen-sated by slightly altering the biasing of the amplifier so that the biasing where inthe allowed level. The final chain is shown in Figure 4.17.

Figure 4.17: The full OR chain in Cadence Virtuoso.

5Results

This chapter presents the results of the simulations made on the full OR system.Last, a summary will be given, stating the overall performance of the complete cir-cuit. The model used for the analog filter is the momentum model implementedin Section 4.1.6 while the voltage amplifier model is the PEX model implementedin Section 4.2.4. The simulations in this chapter is executed on the test bench inFigure 4.17.

5.1 IMD3 and Attenuator Settings

Similar to Section 4.2.1, the IMD3 of the chain was measured between RF inputpower of -30 dBm and 0 dBm input using 5 dB steps, and adding one simulationfor the 1 dB input case. The measurements were done using a two-tone test witha harmonic balance analysis. The tones are placed with 10 MHz difference at 7GHz and 7.01 GHz so that they are mixed down by the 6.01 GHz LO frequencyto 990 MHz and 1 GHz (edge of the frequency band).

55

56 5 Results

0

10

20

30

40

50

60

70

80

90

100

110

120

0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728293031

IMD

3 (

dB

c)

Attenuation (dB)

-30 dBm

-25 dBm

-20 dBm

-15 dBm

-10 dBm

-5 dBm

0 dBm

Figure 5.1: IMD3 in dBc versus attenuation in dB and input power in dBm.

As seen in Figure 5.1, All input powers have corresponding attenuation settingsgiving an IMD3 over 90 dBc. To maximize the power output, the lowest possibleattenuation setting is used.

Table 5.1: Input power with lowest usable attenuation setting and IMD3. (7GHz)

Input Power Attenuation Setting IMD3

-30 dBm 0 96.13 dBc-25 dBm 3 90.31 dBc-20 dBm 9 93.21 dBc-15 dBm 15 90.44 dBc-10 dBm 19 91.88 dBc-5 dBm 25 91.60 dBc0 dBm 30 90.86 dBc1 dBm 30 89.84 dBc

5.2 Power Spectrum of Each Stage 57

5.2 Power Spectrum of Each Stage

A single-tone test at 990 MHz was used to get the power spectrum of each stagein the OR chain. It was used to measure the suppression of the mixer image andthe output voltage for each of the input power/attenuation settings. The resultsare shown in Table 5.2.

Table 5.2: Single-tone test results.

Input Power/att. setting Image Suppression Vp−p

-30 dBm / 0 61.78 dBc 24.10 mV-25 dBm / 3 63.96 dBc 31.04 mV-20 dBm / 9 63.67 dBc 29.90 mV

-15 dBm / 15 63.74 dBc 30.24 mV-10 dBm / 19 64.67 dBc 33.72 mV-5 dBm / 25 64.13 dBc 31.69 mV0 dBm / 30 64.87 dBc 34.49 mV1 dBm / 30 64.79 dBc 38.70 mV

As an example, the power spectrum after each stage measured with the 1dB set-ting is shown in Figure 5.2.

Figure 5.2: Power spectrum for each of the stage outputs.

The mixer power spectrum is clearly shifted down relative to the attenuator out-put power, and the high frequent filter outputs is suppressed relative to the at-tenuator power.

A single-tone test at 990 MHz with the power input swept was also used to cal-culate the 1 dB compression point of the complete OR chain. The result of thesweep is shown in Figure 5.3. The setting of the attenuator was at 0 (worst case –no attenuation).

58 5 Results

-15

-10

-5

0

5

10

-10 -8 -6 -4 -2 0 2 4 6 8 10

Ou

tpu

t P

ow

er

Input Power

Measured Extrapolation

1 dB Compression Point @ 2.865 dB

Figure 5.3: 1 dB compression point of the complete OR chain.

5.3 S-Parameters

The frequency was swept between 6.011 GHz to 7.0 GHz with a harmonic bal-ance s-parameter analysis in order to measure the passband ripple, input/outputmatching and phase shift over the 1 MHz to 990 MHz baseband. This was donefor each of the eight input power/attenuation settings. The phase shift was mea-sured over S21.

Table 5.3: S-parameter overview results.

Input Power/att. setting Passband Ripple Max S11 Max S22 Phase Shift

-30 dBm / 0 947.2m dB -10,14 dB -14.12 dB 145.4 deg-25 dBm / 3 961.1m dB -15.91 dB -14.09 dB 144.3 deg-20 dBm / 9 741.7m dB -19.95 dB -14.03 dB 144.4 deg

-15 dBm / 15 645.4m dB -14.69 dB -14.00 dB 144.5 deg-10 dBm / 19 570.8m dB -19.85 dB -14.02 dB 143.8 deg-5 dBm / 25 319.4m dB -20.68 dB -14.02 dB 142.3 deg0 dBm / 30 222.4m dB -18.32 dB -14.02 dB 142.2 deg1 dBm / 30 222.6m dB -18.32 dB -14.77 dB 142.2 deg

5.3 S-Parameters 59

-22

-20

-18

-16

-14

-12

-10

-8S1

1

Input Frequency

-30 input -25 input -20 input -15 input

-10 input -5 input 0 input 1 input

Figure 5.4: S11 input matching for different input power. (7 GHz)

-19

-18

-17

-16

-15

-14

-13

-12

S22

Input Frequency

-30 output -25 output -20 output -15 output

-10 output -5 output 0 output 1 output

Figure 5.5: S22 output matching for different input power. (7 GHz)

60 5 Results

5.4 SNR

NF measurements on the OR circuit using sp analysis in ADE L gave for the -30dBm power input case (worst case) an NF of 17.72 dB while for the 1 dBm powerinput an NF of 44.90 dB. The noise floor for a 990 MHz bandwidth in typicaltemperatures can be calculated with

− 174dBmHz

+ 10log(990MHz) ≈ −84dBm (5.1)

Then the SNR is calculated with

SNRdB = Pin,dB − Pnoise,dB (5.2)

And with Pnoise,dB = −84dBm + NF, the SNR results are −30dBm − (−84dBm +17.7dB) = 36.3dB and 1dBm − (−84dBm + 44.9dB) = 40.1dB

6Discussion

This chapter compile and discusses the results attained in Chapter 5, and thedesign approach described in Chapter 4.

6.1 Conclusions and Results

A two-staged analog baseband circuit incorporating a passive analog filter anda wideband voltage amplifier were successfully designed, implemented in an ICmask layout in a 65nm CMOS technology, and joined with a previously designedanalog front-end design to form an observation receiver. The final circuit showshigh linearity with an IMD3 measurement of at least 90 dBc and an SFDR of atleast 90 dBc over the defined input power range at the worst case input frequencyof 7 GHz. The baseband itself shows a worst case amplitude passband ripple of829m dB while the full OR chain shows a 947m dB passband ripple. As forthe output voltage, a mean of 31.7m Vp−p for the defined input power rangewere recorded at the output of the OR chain. The voltage amplifier showed avoltage amplification of 15 dB with around 0.08 dB amplitude precision over990 MHz, while the passive filter was capable of a passband amplitude precisionof 0.67 dB up to 990 MHz while effectively suppress signals with frequenciesabove 3.44 GHz at least 60 dBc. Both stages were realized and simulated in anIC mask layout, and in addition, the filter layout were simulated using an EMsimulator. An alternative amplifier design with 19.4 dB voltage amplification wasalso proposed, although discarded due to linearity issues. The compiled resultsof the OR chain with 7 GHz input are shown in Table 6.1.

61

62 6 Discussion

Table 6.1: The final results from Chapter 5 of the OR circuit at input of 7GHz. (worst case input)

Description Value (worst case) Value (best case) Target Met?

Inband ripple 0.947 dB 0.222 dB <0.2 dB XInMatching -10.14 dB -20.68 dB <-10 dB X

OutMatching -14.00 dB -14.77 dB <-12 dB XImage Rejection 61.78 dBc 64.79 dBc >90 dBc X

IMD3 89.84 dBc 96.13 dBc >90 dBc XSFDR >90 dBc - >90 dBc X

Vp-p output 24.1 m 38.7 m 250 m – 500 m XInband SNR 36.3 dB 40.1 > 50 dB XPlausible

As seen in Table 6.1, the OR don’t meet certain targets like amplitude precisionand voltage output for the worst case input at 7 GHz (giving a bandwidth of990MHz).

6.2 Discussion

This section debates the results and propose possible actions to improve or solvethe targets that were not met.

6.2.1 Linearity and Voltage Output

As previously stated, the tradeoff between the linearity and the amplification ofthe baseband over the target bandwidth was possibly the hardest task. The lin-earity is prioritized as the smaller voltage output theoretically can be taken careof by using an ADC stage with higher input sensitivity. With an Vp−p output ofaround 30mV, the ADC stage has to improve its sensitivity about ten times. Theamplifier is however contributing with 15 dB over 100 ohms to 1k ohms, takinga voltage input of about 7mV and amplifying it to 30mV. In future work, the useof bipolar transistors could be investigated as a possible enhancement. Bipolartransistors generally offer a wider bandwidth in counterpart to the MOSFET tran-sistors, so that the gain of the circuit can be enhanced. In [4], an ultra-widebanddifferential bipolar transistor amplifier is proposed, applying a bandwidth en-hancement by carefully placing the amplifier poles. This bandwidth enhance-ment could be used to relax the bandwidth requirement and linearity to furtherincrease the gain of the stage.

6.2.2 In-Band Amplitude Precision

The in-band ripple of the OR is off by about 0.75 dB for the full 990 MHz bandin the worst case, were the analog front-end is contributing with about 0.5 dBas stated in [3], while the analog baseband contributes with about 0.8 dB in

6.2 Discussion 63

the worst case. To further improve the baseband ripple contribution, the rip-ple caused by the filter could further be improved by moving the cutoff point tohigher frequency. The attenuation of the signal images could theoretically stillbe held down as the amplifier to a degree also contributes to the suppression inthe out-of-band region.

6.2.3 Filter Model

As seen in Section 4.1.6, the momentum model results of the filter are muchworse than both the schematic model and the PEX model of the filter, with onlya 60 dBc attenuation of the signal image. This is probably because when usingpassive filters with such high order, in a real implementation, the dependency ofthe value precision of the components is really high and is severely compromisedby the non-ideal behavior of the real-life components. A proper solution to thisproblem could be to design two smaller passive filters and strategically placethem for example before and after the voltage amplifier and combined be able toattenuate the signal image by 90 dBc.

6.2.4 Layout of Front-End

The layout of the front end components is yet to be done in order to be able tojoin it together and send the full OR circuit for manufacturing on silicon.

6.2.5 The Work In a Wider Perspective

As stated in Chapter 1, the work done here is just one of many contributions indefining and designing the next generation of mobile communications. Peopleand devices become even more connected to the global communication and moreinformation than ever before are being sent and stored all over the world. Theindustry itself is the biggest pusher due to the competition between large actorson the market and their market share. It is essential to be ahead and see the nexttrends, and be a part of the definition of new standards. The work applied in thislevel is probably one of the most important contributions to the industry.

Appendix

AMatlab Script

A Matlab® function calculating LC component values of a maximum flat passiveLC ladder filter.

67

68 A Matlab Script

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function [ C, L ] = maxflat_LP( fc, fs, ac, R, as, n )

%MAXFLAT_LP Maximum flat low pass filter LC component calculator

%

% [ C, L ] = maxflat_LP( fc, fs, ac, R, as, n )

%

% Returns LC component values that fulfill input specification targets.

% fc - Cutoff frequency in Hz

% fs - Stopband frequency in Hz

% ac - attenuation at cutoff in dB

% R - input/output impedance in Ohms

% as - attenuation at stopband frequency in dB

% n - (OPTIONAL) filter order

%

% If 'n' is used, 'as' will be ignored and the specified filter order

% will be used instead.

if nargin < 6

n = ceil( (log10(10^(0.1*as)-1)-log10(10^(0.1*ac)-1))/(2*log10(fs/fc)) );

end

fun_c =@(N, cutoff, comp, R) 2*sin(((2*(comp*2 + 1)-1)/(2*N))*pi)/(cutoff

*R);

fun_l =@(N, cutoff, comp, R) 2*sin(((2*(comp*2 + 2)-

1)/(2*N))*pi)*R/(cutoff);

n_C = ceil(n/2);

n_L = n_C - rem(n,2);

C=zeros(1, n_C);

for i = 1:n_C

C(i) = fun_c(n, 2*pi*fc, i-1, R);

end

L=zeros(1, n_L);

for i = 1:n_L

L(i) = fun_l(n, 2*pi*fc, i-1, R);

end

eps_sqr = 10.^(ac/10) - 1;

H =@(n, w) sqrt(1./(1+eps_sqr.*(w./(2*pi*fc)).^(2*n)));

whz = 0:1e6:2*fs;

plot(whz,20*log10(H(n,2*pi*whz)))

end

BADE L Test bench

Appendix B describes the ADE L test bench specifications of the single passiveanalog filter approach.

The S-parameter simulation was run with a frequency sweep from 1 MHz to 20GHz with a sample rate of 100 points per decade and with a logarithmic scale. Inthe table below, the output formulas of the simulation are defined.

69

70 B ADE L Test bench

Name Formula Comment

Sdd11 db((spm 'sp 1 1 ?port1 "d" ?port2 "d")) Differential input port voltage reflection.

Sdd12 db((spm 'sp 1 2 ?port1 "d" ?port2 "d")) Differential reverse voltage gain.

Sdd21 db((spm 'sp 2 1 ?port1 "d" ?port2 "d")) Differential forward voltage gain.

Sdd22 db((spm 'sp 2 2 ?port1 "d" ?port2 "d")) Differential output port voltage reflection.

InBandRipple (ymax(clip(db((spm 'sp 2 1 ?port1 "d" ?port2 "d")) 0 9.9e+08)) - ymin(clip(db((spm 'sp 2 1 ?port1 "d" ?port2 "d")) 0 9.9e+08)))

Passband Ripple.

InBandLoss ymin(clip(db((spm 'sp 2 1 ?port1 "d" ?port2 "d")) 0 9.9e+08))

The worst case attenuation in passband.

InMatching ymax(clip(db((spm 'sp 1 1 ?port1 "d" ?port2 "d")) 0 9.9e+08))

Worst case in band input matching.

OutMatching ymax(clip(db((spm 'sp 2 2 ?port1 "d" ?port2 "d")) 0 9.9e+08))

Worst case in band output matching.

[email protected] (value(db((spm 'sp 2 1 ?port1 "d" ?port2 "d")) 3.44e+09) - ymin(clip(db((spm 'sp 2 1 ?port1 "d" ?port2 "d")) 0 2.8e+08)))

Attenuation at 3.44 GHz frequency.











Bibliography

[1] A. J. Casson and E. Rodriguez-Villegas. A review and modern approach tolc ladder synthesis. J. of Low Power Electronics and Applications 2011, 1(1):20–44, 2011. Cited on pages 17 and 20.

[2] S. Chen, J. Zhao, and Y. Peng. The development of td-scdma 3g to td-lte-advanced 4g from 1998 to 2013. IEEE Wireless Comm., 21(6):167–176, 2014.Cited on page 2.

[3] H. Dafallah. "Highly Linear Attenuator and Mixer for Wide-Band TOR inCMOS". M.S. thesis, Dept. Elect. Eng., Lund Univ., Lund, Sweden, 1996.Cited on pages 2, 5, 6, 7, 44, 47, 48, 54, and 62.

[4] M. Ghasemzadeh, A. Akbari, M. Mousazadeh, K. Hadidi, and A. Khoei. Anovel technique for wideband bipolar amplifiers. 2013 21st Iranian Confer-ence on Electrical Engineering (ICEE), pages pp. 1–6, 2013. Cited on page62.

[5] K. Gulati and H. S. Lee. A high-swing cmos telescopic operational amplifier.J. of Solid-State Circuits, 33(12):2010–2019, 1998. Cited on page 29.

[6] J. Karki. Fully-differential amplifiers. Texas Instruments, Dallas, Texas,Tech. Report. SLOA054D, 2002. Cited on pages 26, 27, and 28.

[7] Keysight Technologies documentation. Advanced design system (ads) 2011documentation [e-doc.]. Keysight Tech., California, 2011, Chapt. “Conduc-tor Loss Models in Momentum, 2011. URL http://edadocs.software.keysight.com/. Cited on pages 40 and 41.

[8] H. P. Koringa, B. D. Joshi, and V. Shah. High power gain low noise amplifierdesign for next generation 1–7ghz wideband rf frontend rfic using 0.18µmcmos. VLSI Design and Test (VDAT), 2015 19th International Symposiumon, pages pp. 1–5, 2015. Cited on page 49.

[9] M. Lee, I. Kwon, and K. Lee. Optimization of low power cmos basebandanalog filter-amplifier chain for direct conversion receiver. J. of semicond.Tech. and science, 4(3):168–173, 2004. Cited on pages 28 and 29.

71

http://edadocs.software.keysight.com/

http://edadocs.software.keysight.com/

72 Bibliography

[10] C. Lin, T. S. Kalkur, and M. Morin. A 2.4ghz common-gate lna using on-chipdifferential inductors in a 0.18µm cmos technology. Electrical, Communica-tions, and Computers, 2009. CONIELECOMP 2009. Intern. Conf. on, pages183–188, 2009. Cited on page 29.

[11] R. Raut and M. N. S. Swamy. Modern Analog Filter Analysis and Design:A Practical Approach. Weinheim: WILEY-VCH Verlag & Co, first edition,2010. Cited on pages 19 and 20.

[12] G. C. Tripathi, P. Jaraut, M. Rawat, and L. N. Reddy. Digital predistortionof power amplifiers with diversity technique in 4g mimo transceivers. 2015IEEE MTT-S International Microwave and RF Conference (IMaRC), pages53–55, 2015. Cited on pages 3 and 11.

[13] S. Woo, W. Kim, C. H. Lee, K. Lim, and J. Laskar. A 3.6mw differentialcommon-gate cmos lna with positive-negative feedback. 2009 IEEE Intern.Solid-State Circuits Conf. - Digest of Tech. Papers, pages 218–219, 2009.Cited on page 29.

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