Analog and Telecommunication Electronics · 2011-05-12 · 12/05/2011 - 4 ATLCE - D3 - © 2010 DDC...
Transcript of Analog and Telecommunication Electronics · 2011-05-12 · 12/05/2011 - 4 ATLCE - D3 - © 2010 DDC...
12/05/2011 - 1 ATLCE - D3 - © 2010 DDC
Politecnico di Torino - ICT School
Analog and Telecommunication Electronics
D3 - A/D converters
» Error taxonomy» ADC parameters» Structures and taxonomy» Mixed converters» Origin of errors
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Lesson D3: ADC taxonomy and errors
• Analog to Digital converters– Transfer function and error taxonomy (linear, nonlinear,
dynamic)– Converter parameters: complexity and speed
• Examples of A/D converters– Flash, Tracking, Successive approximation– Residue, subranging, folding structures
• Pipeline structures
• Mixed structures– Performance tradeoff
• Text reference Sect. 4.3
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Errors in A/D converters
• Dual transfer function vs D/A– X axis: analog values (continuous)– Y axis: numeric values (discrete)
• Each ADi interval corresponds to a Di value– “stair” transfer function– If N large looks as a continuous line– Same error classification as D/A
» Linear: offset and gain» Nonlinearity: differential and integral» Dynamic parameters
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Ideal A/D transfer function
0 S
01
M
2
D(digital)
A(analog)
1 LSB
AD ADi
Di
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Static errors: two-steps analysis
• Linear approximation of actual transfer function
• Actual transfer function vs linear approximation– Nonlinearity errors: integral nonlinearity
• Linear approximation vs ideal transfer function– Linear errors: offset and gain
• Detailed quantization interval analysis– Differential nonlinearity
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Actual vs ideal transfer function
0
0
Actual transfer function
S
A
M
ideal
D
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Best linear approximation
0
0
Actual transfer function
Best approx.straigth line
S
D
A
M
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Linear approx. vs ideal transf. function
0
0
Best approx.straigth line
S
D
A
M
idealG
O
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Integral nonlinearity error
0
0
Actual transfer function
Nonlinearityband
Best approx.straigth line
integralintegralnonlinearitynonlinearityerror error inlinl
S
D
A
M
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Complete view
0
0
Actual transfer function
Nonlinearityband
Best approx.straigth line
integralintegralnonlinearitynonlinearityerror error inlinl
S
D
A
M
ideal
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Linear and nonlinear errors
• Offset error– shift of the output
• Gain errors– rotation of the transfer function
• Both can be compensated with gain and offset corrections in the signal chain
• Integral nonlinearity error inl– Position dependent; cannot be compensated
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0
AD
0 S
D
A
M
Ideal A/D transfer function
• Uniform quantization:– All quantization intervals AD have the same amplitude
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Integral nonlinearity error
• Actual quantization intervals: A’D ≠ AD
– Differential nonlinearity: DNL = AD - A’D
0
A’D
0 S
D
A
M
AD
Actual transfer function
Ideal transfer function
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Missing code error
• Wide intervals reduce adjacent ones • Very wide intervals can suppress adjacent ones
– Missing code error: DNL > 1 LSB
00 S
D
A
M
This code isnever generated
A’D1
A’D2
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Integral and differential nonlinearity
• Integral nonlinearity INL– How much the global transfer function deviates from a straight
line– Unique figure
• Differential nonlinearity DNL– Difference AD - A’D between ideal (AD) and actual (A’D)
amplitude of each quantization interval– Specific to each interval (but has a max!)
• INL = ∫(DNL) = ∑ (DNL)
• DNL = Der(INL)
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Relation Integral/differential nonlinearity
• εINL = ∫(DNL) = ∑ (DNL)
• εDNL = Der(INL)
• Example – Fixed polarity εDNL high εINL
– Alternate polarity εDNL low εINL
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Dynamic parameters
• Conversion from A to D requires some time:conversion time Tc
• Can be specified also as
conversion frequency Fc = 1/Tc
• In most cases – The ADC receives a “Conversion Start” (CS) command – After Tc the ADC raises a “End Of Conversion” (EOC) flag.
• Some ADC can follow a (slowly) changing signal:– tracking converters– Dynamic behavior specified by max track rate (Slew Rate)
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ADC error summary
• Linear errors:– Gain: G offset: O
• Nonlinearity errors:
– Integral NL: inl differential NL: dnl
• Dynamic parameters
– Conversion time: tC– Tracking rate: dV/dt
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Lesson D3: A/D converters
• Analog to Digital converters– Error taxonomy (linear, nonlinear, dynamic)– Converter parameters: complexity and speed
• Examples of A/D converters– Flash, – Tracking– Successive approximation,
• Residue/subranging
• Pipeline structures
• Performance tradeoff
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A/D converter architectures
• Various types of ADC, which can be classified from:
– Complexity» Number of comparators in the circuit» Better if few comparators
– Conversion time Tc» Or conversion rate Fc, inverse of Tc» Better if low Tc (high speed, high Fc)
• Linked parameters:– High speed converters are more complex– High speed and high resolution are expensive
.
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A/D converters classification
• Parallel (flash)• Pipeline• Residue• Successive approximation • Tracking, Ramp
Complexity: number of comparators.Conversion time: Tc = 1/Fc
(inverse of the number of conversion/s)
.
Complexity Conv time
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Parallel (flash) ADC
VR
-+
-+
-+
-+
A
thermometricor linear output coding
0
1
1
0
Analog input level (between 0 and VR)
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Flash ADC with coded output
VR
-+
-+
-+
-+
A
0
1
1
0
M N encoder
M = 2N - 1 N
M-Nenc.
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Flash converter parameters
• 2N comparators (2N -1)
• 1 comparison cycle for N bits
• Fast– all comparators operate in the same time slot
• Complex – requires many comparators
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Logic network-+A
D
A’
DAC - feedback converters
• A logic network builds an approximation A’ of the input A using results of A<--> A’ comparison
– A’ is obtained from D through a DAC– D is the numeric representation of A
DAC
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Feedback converters algorithms
• The logic network modifies D till A’ becomes the best approximation of A (within the N-bit resolution)
• Two procedures:
• Steps of one LSB:– tracking converters– 2N steps for full scale change; conversion time: TC = 2N TCK
• Start from MSB:– successive approximation converters– N steps for any conversion: TC = N TCK
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LSB steps: staircase converter
• Counter with enable– If A’ < A , EN = 1 (counter enabled)– If A’ > A , EN = 0 (counter disabled)
• M = 2N steps from 0 to S:TC = 2N TCK
EN counter-+A
D
A’
DAC
CK
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Signal acquisition with staircase ADC
– As long as A’ < A, EN = 1 and counter is enabled, – The feedback signal A’ goes up 1 LSB for each Tck– As A’ > A the comparator disables the counter; A’ stops– max conversion time: Tc max (0 to S change of A) = 2N Tck– For new conversion reset counter to 0
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LSB steps: tracking converter
• Up/Down counter– If A’ < A , D = D + 1– If A’ > A , D = D - 1
• M = 2N steps from 0 to S:TC = 2N TCK
U/D U/D counter-+A
D
A’
DAC
CK
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Acquisition of constant signal
– As long as A’ < A, counter goes UP on CK edges– The feedback signal A’ moves 1 LSB for each Tck– As A’ > A the counter reverses count direction– max conversion time: Tc max (0 to S change of A) = 2N Tck
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Tracking of changing signals
• The converter can track signals with dv/dt < AD/Tck
Tracking
Overload
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Tracking converter parameters
• 1 comparator
• 2N comparison cycle for N bits
• Slow – fully sequential decisions– limited dV/dt tracking capability
• Simple – requires a single comparator
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Start with MSB: succ. approx. ADC
• Input signal compared with S/2: result --> MSB– MSB = 0: next comparison with S/4– MSB = 1: next comparison with 3S/4– result --> MSB - 1– …..
Successive approximation
register (SAR) -+A
D
A’
DAC
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Approximation sequence - 2
• A is compared with S/2 – A’ = S/2 by setting MSB = 1
S
0
S/2
A’ = S/2
A
t
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Approximation sequence - 3
• Since A > S/2 , MSB = 1– 0 - S/2 excluded from possible A values
S
0
S/2
A’ = S/2A > A’MSB = 1
A
t
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Approximation sequence - 4
• A compared with mid-value of possible range– A’ = 3S/4 by setting MSB-1 = 1
S
0
S/2
3S/4
A’ = S/2A > A’MSB = 1
A
t
A’ = 3S/4
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Approximation sequence - 5
• Since A < 3S/4, MSB -1 = 0– 3S/4 - S range excluded from possible A values
S
0
S/2
3S/4
A’ = S/2A > A’MSB = 1
A
A’ = 3S/4A < A’MSB-1 = 0
t
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Approximation sequence - 6
• A is compared with mid-value of possible range– A’ = 5S/8 by setting MSB - 2 = 1
S
0
S/2
3S/4
A’ = S/2A > A’MSB = 1
A
A’ = 3S/4A < A’MSB-1 = 0
t
A’ = 5S/8
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Approximation sequence - 7
• Since A < 5S/8, MSB - 2 = 1– S/2 - 5S/8 range excluded from possible A values
S
0
S/2
3S/4
A’ = S/2A > A’MSB = 1
A
A’ = 3S/4A < A’MSB-1 = 0
t
A’ = 5S/8A > A’MSB-2 = 1
A’ = 11S/16
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Approximation sequence - 8
• Since A < 11S/16, MSB - 3 must be 0– 11S/16 - 3S/4 range excluded from possible A values
S
0
S/2
3S/4
A’ = S/2A > A’MSB = 1
A
A’ = 3S/4A < A’MSB-1 = 0
t
A’ = 5S/8A > A’MSB-2 = 1
A’ = 11S/16A < A’MSB-3 = 0
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Complete decision tree
S
0
S/2
3S/4
Sequence of possible output A’ from D/A which are compared with A
t
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Successive approx. ADC parameters
• Single comparator
• N comparison cycles for N-bit conversion
• Vs flash ADC– Simpler: 1 comparator vs 2N
– Slower: N steps vs 1
• Vs tracking ADC– Same complexity: 1 comparator– faster: N steps vs 2N
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Speed vs complexity
Complex Conv time
Parallel (flash) 2N 1??? (Pipeline) N 1??? (Residue) N NSuccessive Approx 1 NTracking 1 2N
Complexity: proportional to the number of comparators.Conversion time: the maximum number of comparator delay
(clock periods) to complete a conversion
the table suggest two new types of ADC
.
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Lesson D3: A/D converters
• Analog to Digital converters– Error taxonomy (linear, nonlinear, dynamic)– Converter parameters: complexity and speed
• Examples of A/D converters– Flash, – Tracking– Successive approximation,
• Residue/subranging
• Pipeline structures
• Performance tradeoff
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Comparison in SAR ADC
• Sequence of comparison in the SAR ADC:– MSB: A > S/2 ?
– MSB-1: A > S/4 + S/2 MSB ?A > S/4 if MSB = 0A > S/4 + S/2 if MSB = 1
A - S/2 MSB > S/4 ?2(A - S/2 MSB) > S/2 ?
• A - S/2 MSB = R1 (MSB residue)– MSB-1 decision becomes 2 R1 > S/2 ?
– Similar to MSB decision (comparison A – S/2)
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Comparison in SAR ADC
• Sequence of comparison in the SAR ADC:– MSB: A > S/2 ?
– MSB-1: A > S/4 + S/2 MSB ?A > S/4 if MSB = 0A > S/4 + S/2 if MSB = 1
A - S/2 MSB > S/4 ?2(A - S/2 MSB) > S/2 ?
• A - S/2 MSB = R1 (MSB residue)– MSB-1 decision becomes 2 R1 > S/2 ?
• The SAR algorithm can find bit(MSB-i) by comparing residue Ri with S/2
– MSB: i = 0; MSB-1: i = 1; ….
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Subranging/residue converter
• The residue (order M) is the difference between A and its M-bit approximation
– on each step the residue is amplified (x 2) and compared again with S/2
S
0
S/2
S = S/2MSB = 1
A
t
R1
S = S/2MSB-1 = 0
2 R1
R2
2 R2 R3
S = S/2MSB-2 = 1
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Subranging ADC procedure - 1
• At first step A is compared with S/2– Since A > S/2, MSB = 1
S
0
S/2
S = S/2A > S/2 ?
A
t
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Subranging ADC procedure - 2
• The MSB residue is R1– R1 is amplified (x 2) and compared with S/2
S
0
S/2
S = S/2MSB = 1
A
t
R1
S = S/22R1 > S/2 ?
2 R1
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Subranging ADC procedure - 3
• Since 2R1 < S/2, MSB-1 = 0– The MSB-1 residue is R2– R2 is amplified (x 2)and compared with S/2
S
0
S/2
S = S/2MSB = 1
A
t
R1
S = S/2MSB-1 = 0
2 R1
R2
2 R2
S = S/22R2 > S/2 ?
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Subranging ADC procedure - 4
• Since 2R2 > S/2, MSB-2 = 1– The MSB-2 residue is R3– R3 is amplified (x 2)and compared with S/2
S
0
S/2
S = S/2MSB = 1
A
t
R1
S = S/2MSB-1 = 0
2 R1
R2
2 R2 R3
S = S/2MSB-2 = 1
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Subranging ADC procedure - 5
• Ri = A – (i-bit approximation of A)– At each step the residue Ri is amplified (x 2) and compared with
S/2
S
0
S/2
S = S/2MSB = 1
A
t
R1
S = S/2MSB-1 = 0
2 R1
R2
2 R2
S = S/2MSB-2 = 1
R3
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Residue converter parameters
• The residue ADC uses, for each bit
– One comparator (for bit value decision)
– One 1-bit DAC(to build the approximation)
– One (analog) adder (to evaluate the residue)
– One amplifier (gain = 2) (to bring residue to full scale)
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Precision in subranging converters
• Any error in residue evaluation is propagated to the following stages
– residue must be evaluated with a resolution corresponding to the residual bit number
» ADC precision» DAC precision» Amplifiers and S/H (pipeline) precision
• Previous example– First stage ADC and DAC (1-bit) need 8-bit precision– precision decreases towards LSBs
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Subranging ADC parameters
• N comparators
• N comparison cycles for N-bit conversion
• Vs successive approximation ADC– Higher complexity: N vs 1 comparator– Same speed: N steps
• No benefit
• Useful as starting structure for pipeline ADC
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Lesson D3: A/D converters
• Analog to Digital converters– Error taxonomy (linear, nonlinear, dynamic)– Converter parameters: complexity and speed
• Examples of A/D converters– Flash, – Tracking– Successive approximation,
• Residue/subranging
• Pipeline structures
• Performance tradeoff
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Multistage pipeline converters
• Operate on different samples at the same time– Input sample 1– Input sample 2, processA 1– Input sample 3, processA 2, processB 1– ….– …. ProcessZ 1– …. Output sample 1
• Needs analog memory elements
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Pipeline sequence
• Input sample sequence:A, B, C, D, ...
• Processing – stage time t1 t2 t3 t4
1 A B C D2 X A B C3 X X A B4 X X X A
result of sample A conversion available
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Comparison with other techniques
• A N-bit pipeline A/D converter uses:– N comparators– N comparison cycles
(to complete the conversion of each sample)
• Conversion time:– N-cycle latency– 1-cycle conversion (throughput)
• Same speed as a flash with N comparators– (2N in the flash)
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Speed vs complexity
Complex Conv time Latency
Parallel (flash) 2N 1 1Pipeline N 1 NResidue N N NSuccessive Approx 1 N NTracking 1 2N 2N
Complexity: proportional to the number of comparators.Conversion time: the maximum number of comparator delay
(clock periods) to complete a conversionLatency: delay to get the result
.
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“Classic” 8-bit converters
• 8-bit Flash:– 28-1 = 255 comparators; TCT = TC
• 8-bit SAR:– 1 comparator; TCT = 8 TC + 7 TDA
• Limited choice
• No room for tradeoff
• Can we do something between?– Faster than SAR, slower than flash– Less expensive than flash (less comparators)
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Example: best cost/speed architecture
• Goal:– 8-bit ADC– Conversion time Tct < 60 ns– Devices available: comparators with Tc = 10 ns
• Suitable design– SAR: conversion time Tc = 8 x 10 = 80 ns too long– Flash: Tc = 10 ns, but
» Expensive: 255 comparators» Overkilling: 60 ns is enough
• Any other choice ?
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Multibit residue architectures
• First-stage conversion on 1, 2, 3, … M bits– Comparators are replaced by M-bit ADC– The approximation is built using M-bit DAC– Residue has a max value Ad = S/ 2M
– Gain required to bring residue up to S: 2M
• Multibit-residue provides various speed/complexity tradeoffs
– Higher speed, with the same number of comparators– Less comparators for the same speed– Better tuning of design to specifications
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Choices for 8-bit converters
• Comparators, conversion time (TCT), latency (TL)
• 8-bit Flash:– 28-1 = 255 comparators; TCT = TC TL = 1
• 8-bit SAR:– 1 comparator; TCT = 8 TC + 7 TDA TL = 8
• Something in the middle: multibit residue subranging converters
– Two cascaded 4-bit flash: 2(24-1) = 30 comparators; TCT = 2TC + TDA TL = 2
– Four cascaded 2-bit flash: 4(22-1) = 12 comparators; TCT = 4TC + 3 TDA TL = 4
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Multibit residue ADC: 2 4-bit cells
+
A/D - 4bit
D/A - 4bit
16
A/D - 4bit
MSB, …..(D7, 6, 5, 4)
D3, 2, 1, 0
8-bit residue ADC: 2 4-bit cells
Total conversion time:
Tc = 2 x Tc(A/D) + Ta(D/A)
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Multibit residue ADC: 4 2-bit cells
+
A/D - 2bit
D/A - 2bit
4
+
A/D - 2bit
D/A - 2bit
4
+
A/D - 2bit
D/A - 2bit
4
A/D - 2bit
MSB, MSB-1(D7, D6)
D5, D4
D3, D2
LSB+1, LSB(D1, D0)
8-bit residue ADC: 4 2-bit cells
Total conversion time
Tct = 4 x Tc(A/D) + 3 x Ta(D/A)
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Multibit residue ADC comparison
+
A/D - 2bit
D/A - 2bit
4
+
A/D - 2bit
D/A - 2bit
4
+
A/D - 2bit
D/A - 2bit
4
A/D - 2bit
MSB, MSB-1(D7, D6)
D5, D4
D3, D2
LSB+1, LSB(D1, D0)
+
A/D - 4bit
D/A - 4bit
16
A/D - 4bit
MSB, …..(D7, 6, 5, 4)
D3, 2, 1, 0
8-bit residue ADC: 2 4-bit cells
Tct = 2 x Tc(A/D) + Ta(D/A)
8-bit residue ADC: 4 2-bit cells
Tct = 4 x Tc(A/D) + 3 x Ta(D/A)
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Speed vs complexity with multibit
Complex Speed Conv time Latency
Parallel (flash) 2N 1 1Pipeline N 1 NResidue N N NResidue K bit N/K N/K NSuccessive Approx 1 N NTracking 1 2N 2N
.
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Mixed and multistage converters
• Application of subranging to bit groups (K-bit)– Comparator N bit ADC– Residue evaluation N bit DAC + differential amplifier– With K-bit groups N/K stages– Interstage amplifier gain 2N
• Basic ADC: FLASH– Complexity: Ps = 2K total: PT = N/K x 2K
– Conversion time TC = 1 total: TCT = N/K x TC
• Basic ADC: SAR– Complexity: Ps = 1 total: PT = N/K– Conversion time TC = K total: TCT = N x TC
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Pipeline converters
• Pipeline can be usd for any multistage– Reduces the equivalent conversion time TCT
– Faster equivalent conversion rate FS
– Same latency time
• Pipeline = Residue + Memory element (analog) at the input of each stage
– Change each amplifier into Sample/Hold + amplifier– Some added complexity
• Multibit residue pipeline– FLASH ADC: equivalent TCT = 1 (more precisely TC + TDA )– SAR ADC: equivalent TCT = K TC (more precisely K (TC + TDA ))– Additional design freedom
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Speed vs complexity with multibit
Complex Speed Conv time Latency
Parallel (flash) 2N 1 1Pipeline N 1 NResidue N N NResidue K bit Flash (2K)N/K N/K 1Residue K bit SAR N/K N NSuccessive Approx 1 N NTracking 1 2N 2N
.
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Speed vs complexity - graph
.
Complexity(log)
Conversion time (log)
SARSAR
1 N 21 N 2NN
22NN
N N
11
FlashFlash
TrackingTracking
ResidueResiduePipelinePipeline
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Choices for 12-bit residue ADC
.
Complexity(log)
Conv. time
<bit/stage>x<num stage><bit/stage>x<num stage>
1 2 3 4 6 121 2 3 4 6 12---->>
40954095
126126
45 45 282818181212
Residue 12x1 (Flash)Residue 12x1 (Flash)
Residue 6x2Residue 6x2
Residue 4x3Residue 4x3Residue 3x4Residue 3x4
Residue 2x6Residue 2x6Residue 1x12Residue 1x12
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Telecom applications ADC
• Direct RF or IF signal conversion
• Parameters
– dynamic range (resolution, bit number)
– conversion rate (1/Tc)
– linearity (THD)
– full power bandwidth
– spurious free dynamic range (SFDR)
– signal/(noise+distortion) ratio (SINAD)
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Lab experiment
• Operation and errors of a D/A converter– D/A converter with weighted resistors or ladder network, voltage
switches, voltage output.– Driving with CMOS logic circuits (counter)– Measurement of A(D)– Evaluation of approximating straight line– Gain, offset, nonlinearity errors
• Conversion in tracking ADC– Dynamic range and slew rate verification
• Text reference sect. 4.L1
12/05/2011 - 79 ATLCE - D3 - © 2010 DDC
Lesson D3 - final test
• Which is the effect of strong differential nonlinearity error?
• Describe the missed-code error.
• Which parameters can be used to classify ADCs?
• Draw the block diagram of a residue/subranging converter.
• Explain the difference between conversion time and latency.
• How many comparators are required for a 8-bit flash ADC?
• Which is the conversion delay (as number of comparator decision times) for a 8-bit SAR ADC?
• Draw the block diagram of a residue converter using 3 stages, with 3 bits each.