AN19 - Silicon Labs

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.comRev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 10, 2021

AN19

SILICON DAA LAYOUT GUIDELINES

1. Description

The Si3034/35/36/38/44/46/48 chipsets provide a veryhigh level of integration for modem designs. Integrationof the analog front end (AFE) and hybrid, and theremoval of the transformer, relays, and opto-couplersreduces the layout effort considerably. SkyworksSolutions’ DAA chipset consists of two devices—theDSP-side and the line-side. When designing with theSi3034/35/36/38/44/46/48, there are several layoutguidelines that will assist the designer in attainingtelecom, safety, and EMC approvals.

This document is divided into six main sections:operational items, analog performance related items,EMC items, safety items, assembly items, and thermalconsiderations. Operational items are defined as thoseitems that must be followed to ensure functionality of thesolution. Analog performance related items are layoutrecommendations that are pertinent to the analogperformance of the solution. EMC items are those itemsthat will affect the emissions/immunity performance ofthe solution. Safety items are layout issues that could

impact safety requirements of a particular modemsolution. Assembly items are items that should be notedto assist in assembly of the solution. Thermalconsiderations are those items that may affectoperational performance due to extreme temperatures.

2. Operational Guidelines

Figures 11–14, on pages 11–14, show the typicalapplication circuits for the DAA section. Figure 1 depictsthe placement of the chipset, some of the major discretecomponents, and the RJ11 connector. Note theplacement of the Si302x (DSP-side chip) and theSi301x (line-side chip). Aligning these devices so thatpins 9–16 of the DSP-side chip face pins 1–8 of the line-side chip will aid in following some of the more specificlayout guidelines. Utilizing this placement will also allowthe design to closely resemble the Skyworks Solutions’example layout, enabling the designer to directly followthese guidelines.

Figure 1. Chipset Diagram

DSPSide

Device

C4

C1

LineSide

Device

DiodeBridge

D1/D2

C24 C25

L1

L2

FB1

FB2

RJ11RV1

2.5 mm spacing requirement between TNV (line side)component and any SELV (digitally grounded) component.

Additional 2.0 mm spacingrequirement when using L1and L2 within TNV circuit.

+

–

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2 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.comRev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 10, 2021

2.1. Si3021/24/25 Layout RequirementsThe primary layout considerations for the DSP-side chip(U1) are the placement of the bypass capacitors (C3and C10) and, if implemented, the filter resistor (R3) forthe power supply pins. Capacitors C3 and C10 are thebypass capacitors for VA and VD, respectively. A 0.1 µFcapacitor provides sufficient bypassing. However, forimproved surge immunity the capacitor on VA should be0.22 F and be used in conjunction with the 5.6 V zenerdiode (Z4). If both VA and VD are derived from the same5 V supply, it is recommended that R3 be used toprovide a low-pass filter for VA. For separate supplies, itis assumed the VA supply is a low-noise supply. R3 maystill be used in this case to provide local filtering of theVA supply pin. The typical operating current of the VAsupply pin is 1 mA. A 10 resistor with C3 will provide alow pass corner frequency of 725 kHz, while onlyreducing the supply to VA by 10 mV. If the powersupplied to U1 is 3.3 V, the charge pump internal to U1must be used to power VA. In this case, R3 should beremoved, and the VA pin should only be connected toC3.

Figure 2 shows a typical placement of C3 and C10. Thehardware designer should focus on minimizing thelength of the C3 connection between the VA and GNDpins and the length of the C10 connection between theVD and GND pins on U1.

Figure 2. C3 and C10

2.2. Si3024/25 Crystal Layout Require-ments

The Si3024/25 incorporates a crystal interface forcreating a 24.576 MHz master clock. The Si3024/25uses the master clock when the device is configured forprimary mode. For designs that use a 24.576 MHzcrystal as shown in Figure 3, the following layoutguidelines should be followed:

The loop formed by XIN (pin 1), Y1, and XOUT (pin 2) should be minimized and routed on one layer of the PCB.

The loop formed by Y1, C34, and C35 should be minimized and routed on one layer of the PCB.

The route from GND (pin 12) to C34 and C35 should be as direct as possible and, if feasible, on one layer of the PCB.

These guidelines will also help minimize issues withemissions. An example layout is shown in Figure 4.

Figure 3. Crystal Circuit

Figure 4. Routing Y1 to U1

C34

C35

Si3024/25

XIN

XOUT

GND

1

2

12

Y1

AN19

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 3Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 10, 2021

2.3. Si3012/14/15 Layout RequirementsFor the line-side chip (U2), the primary layoutconsiderations are the placement and routing of C6, C9,C16, D1, D2, and RV2.

Capacitors C6 and C16 provide regulation of thesupplies powering U2. The loop formed by C6 to pins 3and 9 and the loop formed by C16 to pins 3 and 10should be made as small as possible. Figure 5 showsan example of how to minimize these loops. The traceback to pin 3 is thicker because multiple loops use thispath. The thicker trace has a lower impedance, whichlessens the effect of multiple currents in that trace.

Capacitor C9, dual diodes D1 and D2, and the MOVRV2 form a loop that should be minimized. C9 performsa low pass filter function on the transmit and receivesignals. The inductance in the loop from C9 to the diodebridge (D1 and D2) can affect the ability of C9 tosuppress out-of-band energy. See Figure 6 on page 4for a layout example.

2.4. Si3014/15 Layout RequirementsThe placement of capacitors C12 and C13 is importantbecause these components are in high gain loops.Noise in these loops may affect the signals at TIP andRING. The loop formed from pin 15 through C12 to pin 1(QE2) and the loop formed from pin 16 though C13 topin 1 should be routed as short as possible. Figure 5illustrates an example of these loops. Also, the tracefrom Q4 pin 3 (emitter) should connect directly to theQE2 pin and should not share the same route as theC12 and C13 capacitors to QE2.

Figure 5. Routing C6, C16, C12, C13, Q4, R2, and R11

3. Analog Performance

The components on the line side of the DAA arecomposed of a small digital interface section (capacitorbarrier interface, converters, and control logic), and theremaining components are used for either analogcircuits (hybrid, dc impedance, ac impedance, ringerimpedance, etc.) or safety and EMC (surge protector,ferrite beads, EMC capacitors, etc.).

Routing all traces in the DAA section with 15 mil orgreater traces when possible will ensure high overallanalog performance of the silicon DAA. Furthermore,the DAA section should not use a ground plane for theIGND signal; instead the IGND signal should be routedusing a 20 mil trace. Thermal considerations may alsobe affected by the size of the IGND trace. See "ThermalConsiderations" on page 6.

3.1. Si3014/15 Analog PerformanceAfter placing C6, C12, C13, and C16, the designershould focus on placing R11 and routing the trace fromQ4 pin 3 to U2 pin 1 using as small a loop as possible toensure good analog performance. Due to the relativelyhigh current that can flow in the trace from Q4 pin 3 toU2 pin 1, this trace should be routed separately from thetrace coming from C12 and C13 to pin 1. This willensure that the current from Q4 will not affect thesensitive C12 and C13 loops. Figure 5 illustrates anexample of the placement and routing of R11, Q4, andU2.

3.2. Si3012 Analog PerformanceAfter placing C6 and C16, the designer should focus onplacing R2. When the DAA is off-hook, excess dccurrent flows through R2. Due to high current, it isimportant that the IGND trace from R2 be sufficientlywide when other components are connected to the traceas shown in Figure 5.

4. EMC

Several sources conduct or radiate EMC from/toelectronic apparatus. Among these are the following:

Antenna loops formed by ICs and their decoupling capacitors

PC-board traces carrying driving and driven-chip currents

Common impedance coupling and crosstalk

To minimize EMC-related problems, all extraneoussystem noise and the effects of parasitic PC-board traceantennas must be reduced. Employment of an effectivesystem shielding may also be necessary. The followingsection discusses how to minimize the EMC problemsthat can occur on the DAA design.

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Capacitors C1, C2, C4, and C9 provide the path for theISOcap™ currents. The typical application schematicrecommends that C2 not be installed. If C2 is notinstalled, the ISOcap current flows in the followingmanner:

1. From pin 11 of the Si3021/24/25 (U1)

2. Across C1 to pin 4 of the Si3012/14/15 (U2)

3. From pin 4 to pin 3 of U2

4. To C9

5. Across C9 to C4

6. And finally, across C4 to pin 12 of U1

Because the ISOcap signal operates around 2 MHz, it isimportant to keep the path of the signal as small aspossible (see Figure 6).

Figure 6. ISOcap™ Interface and Diode Bridge

Short, direct routes using thick 20 mil minimum traces,should be used to connect the ISOcap capacitors totheir respective pins. The GND side of these capsshould be connected directly to the GND pin (pin 12) onthe Si3021/24. The IGND side of C2 should connectdirectly to the IGND pin of the Si3012/14/15. It isacceptable to use a long trace to connect C4 to the Q1pin 3 node, as long as there is an IGND trace thatfollows the C4 to Q1 trace.

For those designs that exhibit emission problemsrelated to the ISOcap interface, the C30 capacitor maybe installed. C30 will shunt some of the high frequencyenergy and reduce emissions due to the harmonics ofthe ISOcap link.

FB1, FB2, RV1, C24, C25, C31, and C32, and ifimplemented, a fuse should be placed as close aspossible to the RJ11 as shown in Figure 7. It isimportant for the routing from the RJ11 connectorthrough the ferrite beads FB1 and FB2 to be wellmatched. The routing to C24 and C25 should also bewell matched. The distance from the TIP and RINGconnections on the RJ11 through the EMC capacitorsC24 and C25 to chassis ground should be kept as shortas possible. If possible, the routing through the ringer

network to the line-side device pin 5 and pin 6 shouldalso be well matched as shown in Figure 8.

Figure 7. RJ11

Figure 8. Ringer Network

Routing all the connections from RJ11 to FB1, FB2,RV1, C24, C25, C31, C32, and F1 using a 20 mil tracewill improve the EMC performance of the solution.

Good general design practices should be followed toimprove the EMC performance of the solution. Thisincludes laying out the digital ground plane as small aspossible and rounding off the corners. Placing seriesresistors on the clock signals near their source andensuring that the traces from oscillators or crystals aremade as short as possible will contribute to the overallemissions performance of the solution.

When using the Skyworks Solutions DAAs in unearthedsystems, the designer should consider making somemodifications to prevent common mode 50/60 Hzsignals from entering the signal path. In an unearthedsystem, a large 50/60 Hz signal can be present

AN19


between IGND (line-side pin 3) and DGND (digital-sidepin 12). This signal is often as large as 50 VRMS.

The primary consideration is to use well-matchedcapacitors which bridge the telephone network voltage(TNV) to the safety extra-low voltage (SELV). C1 shouldmatch C4, and C24 should match C25. Matching shouldbe within 10%. To the extent that C1 and C24 does notequal C4 and C25, there will be a common mode todifferential conversion of the 50/60 Hz signal. Typicalcommon mode rejection of the 50/60 Hz signal is betterthan 95 dB.

A secondary consideration is capacitive coupling fromDGND (SELV) to nodes on the line-side (TNV) circuitry.The most prevalent system design where capacitivecoupling occurs is in mini PCI and MDC designs.However, this coupling always exists and can have anoticeable effect on analog performance when SELV isphysically close to TNV.

For safety considerations, Skyworks Solutionsrecommends 3 mm spacing between TNV and SELV(international minimum is 2.5 mm). However, there arethree nodes on the line side which require specialconsideration to insure robust analog performance inunearthed systems:

RX pin on Si3012/14/15

FILT pin on Si3014/15

FILT2 pin on Si3014/15

For these pins and the traces that connect to these pins,the following guidelines should be followed:

Whenever possible, keep at least a 5 mm distance between these nodes and SELV.

An IGND guard ring can be used on the board level. This IGND guard ring should be inserted between SELV and the nodes listed above. For FR4 board material, the IGND guard can be placed on any layer. Optimal placement would be for the IGND guard ring to be on the same layer as the nodes listed above. This guard ring allows SELV to couple into IGND rather than the nodes listed above.

For designs (e.g., MDC, mini PCI designs) which have TNV circuitry in close proximity (< 5 mm) to a SELV plane, a Faraday shield can be used to protect against coupling. This coupling occurs through air between the SELV plane and the TNV nodes described above. A small IGND shield can be placed between the TNV nodes and the SELV plane. This plane allows the SELV to couple into IGND rather than the TNV nodes.

5. SafetyThe layout of the modem circuitry, in particular the areaof the circuit that is exposed to telephone networkvoltages (TNV), is subject to many safety complianceissues. Skyworks Solutions recommends that allcustomers consult with their safety expert or consultanton the various regulations that could impact theirdesigns. Application note “AN17: Designing forInternational Safety Compliance” discusses the detailsof safety. Contact your Skyworks Solutionsrepresentative to obtain a copy of this document. Itcontains helpful information regarding multiple safetyissues. One of the most critical layout issues that relatesto safety is to ensure that a minimum 2.5 mm (3 mmpreferable) or 100 mil space is provided between safetyextra low voltage (SELV) and TNV circuitry. Designsrequiring 5 kV isolation between TNV and SELV shoulduse 5 mm minimum spacing.

When L1 and L2 are included in the DAA, the spacingrequirements between the TNV circuit and SELV needsto be increased from 2.5 mm to 3.5 mm. This increasedspacing requirement compensates for the secondarypeaking effects during longitudinal surges resulting fromthe addition of L1 and L2. Refer to Figure 1.

In addition to the increased spacing requirementbetween TNV and SELV, there is a second spacingrequirement within the TNV circuit. During surge events,the voltage across the L1 and L2 inductors can besufficient to create arcing to nearby TNV nodes. Toprevent arcing, it is recommended the opposingterminals of the L1 and L2 inductors be isolated fromeach other by 2.0 mm. Thus, the nodes correspondingto RV1, FB1, FB2, RJ11, and one terminal of L1/L2,should be isolated by 2.0 mm from nodes that connectto the other terminal of L1/L2. Refer to Figure 1.

6. AssemblyThere are several steps that can be taken in layout toensure that the assembly process goes smoothly. Forexample, an assembly-related error is to install thepolarized capacitors with the polarity backwards. Thiscan be prevented by stenciling the board with a plussign on the correct side of C12, C14, and C5 to indicatethe proper orientation for the polarized capacitors. Also,indicating pin 1 on the board with a stencil markingimproves the chances that the integrated circuits will beinstalled correctly. Thought should also be given tousing several footprints for a given component to allowfor multiple vendor choices. Popular components usingmultiple footprints are C1, C2, C4, C12, C24, C25, C31,C32, F1, and Z1. Taking these basic steps will assist inthe assembly process and ease future troubleshooting.

AN19


7. Thermal ConsiderationsWhen using the Si3034/44 or Si3038/48 chipset incommon applications, there are several thermalconsiderations that should be taken into account. Thesethermal considerations will ensure that the device is notoperating outside of the recommended operatingconditions, thus protecting the device from possibledegradation.

On small form factor printed circuit board (PCB)designs, the ability of the PCB to dissipate heatbecomes a very important design consideration. Thesesmall designs will require additional mechanisms toremove the heat from the Si3014/15. For applications

with a PCB area of less than approximately 3000 mm2,thermal design rules should be applied. These designrules can be found in Skyworks Solutions’ applicationnote entitled “Thermal Considerations for Applicationsusing the Si3034, Si3038, and Si3044” (AN21).

8. Check List

Tables 1 and 2 one pages 6 and 9 are check lists thatthe designer can use during layout. The items markedas required should be taken into consideration first.

Table 1. Si3034/35/44 Check List

# Layout Items Required

Operational Items

1 Small loop from C3 (and R3) to U1 pin 13 and pin 12 Yes

2 Small loop from C10 to U1 pin 4 and pin 12 Yes





22 Copper pad heat sink is at least 0.08 sq. in. for Q4. Yes

Analog Performance

7 Small loop from R11 to U2 pin 11 and pin 3 Yes

8 Separate trace from Q4 pin 3 to U2 pin 1 than the trace from C12 and C13 to U2 pin 1 Yes

9 Minimum of 15 mil traces in DAA section

10 Minimum of 20 mil trace for IGND

11 No ground plane in DAA section Yes

n/a > 5 mm spacing between SELV and TNV nodes (RX, FILT, FILT2) Yes

n/a IGND guard ring to protect TNV nodes (RX, FILT, FILT2) Yes

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n/a IGND Farady shield to protect TNV nodes (RX, FILT, FILT2) Yes

EMC Items

12 Small loop formed between U1, U2, C1, C2, and C4. Yes

13 Minimum of 20 mil trace from U1 to C1, C2, and C4 and from U2 to C1 and C2

14 FB1, FB2, and RV1 placed as close as possible to the RJ11 Yes

n/a Routing from TIP and RING of the RJ11 through F1 to the ferrite beads is well matched Yes

16 Distance from TIP and RING through EMC capacitors C24 and C25 to Chassis Ground is short

Yes

17 C9 is located near C4

n/a C4 is located with C2 between U1 and U2

18 Minimum of 20 mil trace from RJ11 to FB1, FB2, RV1, C24, C25, C31, C32, and F1

19 Routing of TIP and RING signals from the RJ11 through the ringer networks to U2 pin 5 and pin 6 is well matched

20 Trace from D1 & D2 to IGND and to C4–C9 node is well matched and forms a small loop.

21 DGND return paths for C10 and C3 should be on component side.

n/a Digital Ground plane is made as small as possible

n/a Ground plane has rounded corners

n/a Series resistors on clock signals are placed near source

Safety Items

23 Additional 2 mm spacing for inductors (if necessary)

24 Minimum 2.5 mm (100 mils) between SELV and TNV (3.0 mm or higher recommended, see "Safety" section)

Yes

n/a Space for fire enclosure

Assembly Items

26 Polarity for C5 is negative side connects with U2 pin 14

27 Polarity for C12 is negative side connects with U2 pin 15

n/a Polarity for C14 is negative side connects with U2 pin 3 (IGND)

n/a Pin 1 marking for U1 and U2

Table 1. Si3034/35/44 Check List (Continued)

# Layout Items Required

AN19


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Table 2. Si3036/38/48 Check List

# Layout Items RequiredOperational Items

1 Small loop from C3 to U1 pin 13 and pin 12 Yes2 Small loop from C10 to U1 pin 4 and pin 12 Yes3 Small loop from C6 to U2 pin 9 and pin 3 Yes4 Small loop from C16 to U2 pin 10 and pin 3 Yes5 Small loop from C12 to U2 pin 15 and pin 1 Yes6 Small loop from C13 to U2 pin 16 and pin 1 Yes22 Copper pad heat sink is at least 0.08 sq. in. for Q4. Yes

Analog Performance7 Small loop from R11 to U2 pin 11 and pin 3 Yes8 Separate trace from Q4 pin 3 to U2 pin 1 than the trace from C12 and C13 to U2 pin 1 Yes9 Minimum of 15 mil traces in DAA section10 Minimum of 20 mil trace for IGND11 No ground plane in DAA section Yesn/a > 5 mm spacing between SELV and TNV nodes (RX, FILT, FILT2) Yesn/a IGND guard ring to protect TNV nodes (RX, FILT, FILT2) Yesn/a IGND Farady shield to protect TNV nodes (RX, FILT, FILT2) Yes

EMC Items12 Small loop formed between U1, U2, C1, C2, and C4. Yes13 Minimum of 20 mil trace from U1 to C1, C2, and C4 and from U2 to C1 and C214 FB1, FB2, and RV1 placed as close as possible to the RJ11 Yesn/a Routing from TIP and RING of the RJ11 trough F1 to the ferrite beads is well matched Yes

16Distance from TIP and RING through EMC capacitors C24 and C25 to Chassis Ground is short Yes

17 C9 is located near C4n/a C4 is located with C2 between U1 and U218 Minimum of 20 mil trace from RJ11 to FB1, FB2, RV1, C24, C25, C31, C32, and F1

19Routing of TIP and RING signals from the RJ11 through the ringer networks to U2 pin 5 and pin 6 is well matched

20 Trace from D1 & D2 to IGND and to C4–C9 node is well matched and forms a small loop.21 DGND return paths for C10 and C3 should be on component side.28 Traces from oscillators or crystals are made as short and direct as possiblen/a Digital Ground plane is made as small as possiblen/a Ground plane has rounded cornersn/a Series resistors on clock signals are placed near source

Safety Items23 Additional 2 mm spacing for inductors (if necessary)

24Minimum 2.5 mm (100 mils) between SELV and TNV (3.0 mm or higher recommended, see "Safety" section) Yes

n/a Space for fire enclosureAssembly Items

26 Polarity for C5 is negative side connects with U2 pin 1427 Polarity for C12 is negative side connects with U2 pin 15n/a Polarity for C14 is negative side connects with U2 pin 3 (IGND)n/a Pin 1 marking for U1 and U2

AN19


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AN19


NOTES:

Copyright © 2021 Skyworks Solutions, Inc. All Rights Reserved.Information in this document is provided in connection with Skyworks Solutions, Inc. (“Skyworks”) products or services. These materials, including the information contained herein, are provided by Skyworks as a service to its customers and may be used for informational purposes only by the customer. Skyworks assumes no responsibility for errors or omissions in these materials or the information contained herein. Skyworks may change its documentation, products, services, specifications or product descriptions at any time, without notice. Skyworks makes no commitment to update the materials or information and shall have no responsibility whatsoever for conflicts, incompatibilities, or other difficulties arising from any future changes.

No license, whether express, implied, by estoppel or otherwise, is granted to any intellectual property rights by this document. Skyworks assumes no liability for any materials, products or information provided hereunder, including the sale, distribution, reproduction or use of Skyworks products, information or materials, except as may be provided in Skyworks’ Terms and Conditions of Sale.

THE MATERIALS, PRODUCTS AND INFORMATION ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, INCLUDING FITNESS FOR A PARTICULAR PURPOSE OR USE, MERCHANTABILITY, PERFORMANCE, QUALITY OR NON-INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHT; ALL SUCH WARRANTIES ARE HEREBY EXPRESSLY DISCLAIMED. SKYWORKS DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. SKYWORKS SHALL NOT BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO ANY SPECIAL, INDIRECT, INCIDENTAL, STATUTORY, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS THAT MAY RESULT FROM THE USE OF THE MATERIALS OR INFORMATION, WHETHER OR NOT THE RECIPIENT OF MATERIALS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Skyworks, the Skyworks symbol, Sky5®, SkyOne®, SkyBlue™, Skyworks Green™, Clockbuilder®, DSPLL®, ISOmodem®, ProSLIC®, and SiPHY® are trademarks or registered trademarks of Skyworks Solutions, Inc. or its subsidiaries in the United States and other countries. Third-party brands and names are for identification purposes only and are the property of their respective owners. Additional information, including relevant terms and conditions, posted at www.skyworksinc.com, are incorporated by reference.

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AN19 - Silicon Labs

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Transcript of AN19 - Silicon Labs