Improved Batch Pan Monitoring and Control – a soft sensor approach
An Improved “Soft” eFPGA Design and Implementation Strategy
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Transcript of An Improved “Soft” eFPGA Design and Implementation Strategy
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An Improved “Soft” eFPGA Design and Implementation Strategy
Victor Aken’Ova, Guy Lemieux, Resve Saleh
SoC Research Lab, University of British Columbia
Vancouver, BC Canada
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Overview• Introduction and Motivation
– Embedded FPGA (eFPGA)• Soft Embedded FPGAs
– Configurable Architecture• Improving Soft eFPGAs
– Tactical Standard Cells– Structured eFPGA layout
• Results• Summary and Conclusions
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Introduction
• SoC designs are getting more complex and costly
• Programmability can be built into SoCs to
amortize costs by reducing chip re-spins
No Flexibility
Software Flexibility
Hardware FlexibilityeFPGAs
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Applications for eFPGA Fabrics
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eFPGA for product differentiation
An eFPGA for CPU acceleration
An eFPGA for revisions
CPU
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Motivation
• shortcomings of existing eFPGA design approaches– Hard eFPGA
• Highly efficient full-custom layouts but inflexible
– Soft eFPGA • Very flexible but inefficient standard cell layouts
• alternative approach: flexible + efficient
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“Hard” eFPGA Approach with a library of 3 Cores
??
Restrictive! overcapacity increases area and delay overheads
1
3
2
RTL
user circuit
?
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The “Soft” eFPGA Approach
eFPGA RTL Generator
ASIC flow autogenerated eFPGA
Generic Standard Cells7x area and 2x delay versus full-custom
much less logic and routing overcapacity
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Some Solutions to Problems of Existing Approaches
• retain eFPGA generator idea for flexibility
• use tactical cells to reduce area + delay
• use structured approach for efficiency
But…
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Our Improved Design Approach“Soft++”
StructuredASIC FLOW
autogenerated eFPGA
Tactical +Generic Cellscombine best of soft and hard approaches
GOALGOAL
eFPGA RTL Generator
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Island-style eFPGA Architecture
• used island-style architecture because
– Mainstream: existing FPGA CAD tools can
can be leveraged
– can exploit its regular structure to improve
design efficiency
• Created parameterized eFPGA in VHDL
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Island-style eFPGA Architecture
(a) Island-style eFPGA (b) eFPGA Tile Layout
L
L: Left Edge TILE
B
B: Bottom Edge TILE
C
C: Corner TILE
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Unstructured vs. Structured eFPGA Design Approach
Soft eFPGASoft eFPGA
Fixed Fixed LogicLogic
Fixed Fixed LogicLogic
(a) unstructured eFPGA layout (b) structured eFPGA layout
tile1tile2
tile3 tile4
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Measured Impact of Structure on eFPGA Quality
• Significant improvements in logic capacity
– result of a more efficient CAD methodology
• wire-only critical path delay less by 21%
• Cut CAD design time by as much as 6X
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Architecture-specific Tactical Cells – The Concept
• improve quality by creating few tactical
standard cells to replace generic cells
• detailed analysis of design profile should
reveal areas that yield significant gains
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Standard cell Area Breakdown for Island-Style Architecture
flip-flops and multiplexers dominate eFPGA area
LUT mux 39%
input mux 13%
LUT30%
switch 16%
other12%
flip-flops 46%
muxes 42%
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Architecture-specific Tactical Cells – Flip-Flop vs. SRAM
An SRAM circuit has fewer transistorsfewer transistors = less area
(b) typical SRAM cell(a) typical D flip-flop
~2:1 area ratio!VDD
write readbit bitb
GND
D
clock clock
Q
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Custom Layout of Standard Cell – Flip-Flop vs. SRAM
Standard Cell Flip-flop Tactical SRAM Cell
2.5Xvdd
gnd
1X vdd
gnd
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Architecture-specific Tactical Cells – CMOS vs. Pass Gate
pass tree logic uses fewer transistorsfewer transistors and is fasteris faster
D
OS0
S0
C
B
A
S0
S1
S1S0
~4:1 area ratio!
after extra output inverterdecompose into NAND, INV
O
S0
D
C
B
A
VDDS1 S1S0
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Layout Technique for Pass-Tree Multiplexers
n-well cut-outs allow denser pass transistor tree layouts
n-well cutout
n-well n-well
gnd gnd
vdd vdd
underutilized region extra NMOS(denser cell)
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Architecture-specific Tactical Cells – Cell Area
EquivalentStandard cell Area (um2)
CustomTactical cell Area (um2)
improvement Factor
Cell
1-SRAM
16:1 MUX
32:1 MUX
4-LUT
5-LUT
61 24 2.5899 146 6.1
2228 293 7.6
1875 530 3.53.910614180
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Area Impact of Tactical Standard Cells – eFPGA Area
eFPGA
(c) full-custom(b) soft ++(a) soft
eFPGA
-58%
eFPGA
-85%
soft ++ ~2.4X smaller than soft = 58% area savings
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Graphs of Area and Delay SavingsA
rea
Del
ay
Benchmarks
Benchmarks
2.4X Better1.6 – 2.8X full-custom area
1.4X Better
1.1X of full-custom delay
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Fabricated Chip Designs with eFPGAs (180nm process)
(a) gradual architecture (b) island-style architecture
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Summary
• eFPGA area improved 58% (on average)
– 2 to 2.8X larger than full-custom equivalent (worst case)
• eFPGA delay improved 40% (average)
– within 10% of delay of full-custom versions
• exploited the regularity of island-style architecture to increase logic capacity
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End of Talk
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Question and Answer Slide
Logic Capacity
Are
aSoft
Soft++
soft++ fills some of performance gap left by hard
hard
custom