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Web FindBestStuff

AN FPGA-BASED DIGITAL LOGIC CORE FOR ATE

SUPPORT AND EMBEDDED TEST APPLICATIONS

A Doctoral Dissertation

Presented to

The Academic Faculty

By

Justin S. Davis

In Partial Fulfillment

of the Requirements for the Degree

Doctor of Philosophy in Electrical Engineering

Georgia Institute of Technology

July 2003

Copyright Justin S. Davis 2003

iii

To my parents,

Stanford and Laurie Davis,

for their endless love, encouragement, and support.

iv

ACKNOWLEDGEMENTS

Throughout my time in graduate school, Dr. David Keezer has contributed a

significant amount of time and effort to the development of my career. I would like

to express my deepest gratitude for his guidance, patience and encouragement. He

has been an outstanding mentor and advisor. I owe a great deal to him for imparting

his knowledge and wisdom, without which this thesis would not be possible.

I would like to express my gratitude to Dr. Chuanyi Ji for serving as the

chairman of my proposal committee and as a committee member for my Ph.D.

dissertation. I would also like to thank Dr. Abhijit Chatterjee and Dr. D. Scott Wills

for serving on the reading committee of my Ph.D. dissertation and on the proposal

committee, and for their constructive comments and suggestions. I also appreciate

Dr. C.P. Wong for serving on my defense committee.

A special thanks goes to Bruce Poole, Chi Bair and Chris Korte for shaping

my career while I was interning at Agilent Technologies. I would like to thank

Keren Bergman and Odile Liboiron-Ladouceur at Columbia University for providing

their technical expertise. I appreciate all of my fellow graduate research assistants

over the years for sharing their knowledge, experience and time with me. Finally I

would like to thank my friends and family for providing support and encouragement

throughout all my time at Georgia Tech.

v

TABLE OF CONTENTS Acknowledgements ................................................................................................ iv List of Figures ........................................................................................................ ix List of Tables ........................................................................................................ xiii List of Abbreviation .............................................................................................. xiv Summary ............................................................................................................... xvii

CHAPTER 1: Introduction ....................................................................................1

CHAPTER 2: Background ....................................................................................7

2.1 Automated Test Equipment ..............................................................7

2.1.1 ATE History .........................................................................7

2.1.2 Modern ATE Architecture ....................................................11 2.1.3 ATE Costs..............................................................................13

2.2 DFT and BIST Technology ...............................................................16

2.2.1 BIST architectures ................................................................19

2.2.2 DFT and BIST costs . 21

2.3 Programmable Logic Technology .22 CHAPTER 3: Using FPGAs in Testing ................................................................27

3.1 Massively-parallel interconnect test method .....................................27

3.1.1 MCM interconnect test concept ............................................28

3.1.2 Generation of test patterns ...................................................31

3.1.3 Partial fault detection ............................................................32

vi

3.1.4 Test implementation ..............................................................34

3.2 Test Support Processor .....................................................................40

3.2.1 TSP concept .........................................................................41

3.2.2 TSP prototype implementing FPGAs ....................................43

3.2.3 Pattern generation and analysis in FPGA TSPs ....................44

3.2.4 TSP implementation...............................................................47

CHAPTER 4: Digital Logic Core ..........................................................................50

4.1 DLC Concept .....................................................................................51

4.1.1 Pin Electronics .....................................................................51

4.1.2 Communications (USB) .......................................................53

4.1.3 Memory devices ...................................................................56

4.2 DLC Implementation .........................................................................57

4.2.1 Hardware ..............................................................................57

4.2.2 Printed circuit board layout considerations ..........................62

4.2.3 Software ...............................................................................65

4.2.4 Firmware ..............................................................................69

4.3 Techniques for increasing data rate ..................................................71

4.3.1 Increasing output data rate capability ...................................72

4.3.2 Increasing input data rate capability .....................................74

4.4 DLC Comparisons .............................................................................78

4.5 DLC Example Application Continuity Checker .............................81

vii

CHAPTER 5: DLC Application: Standalone Test Bed........................................87

5.1 Opto-electronic test bed concept........................................................88

5.2 Emitter-coupled logic ........................................................................94

5.3 Opto-electronic test bed implementation ...........................................96

5.3.1 Hardware ...............................................................................97

5.3.2 Delay calibration ................................................................101

5.3.3 Power supply noise ............................................................103

5.3.4 Software .............................................................................104

5.3.5 Firmware .............................................................................107

5.4 Opto-electronic test bed results.......................................................109

5.4.1 Timing offset measurements ..............................................110

5.4.2 Jitter measurements ............................................................113

5.4.3 Optical connections ............................................................117

5.5 Future Versions ..............................................................................119

CHAPTER 6: DLC Application: System-level Embedded Test.......................125

6.1 Nano-scale wafer-level prober concept .........................................127

6.2 Nano-scale wafer-level prober implementation .............................134

6.2.1 Hardware ............................................................................134

6.2.2 Start-up considerations .......................................................139

6.3 Nano-scale wafer-level prober results ...........................................140

6.4 Future Versions ..............................................................................142

CHAPTER 7: Conclusions and Future Work....................................................145

viii

7.1 Conclusions ....................................................................................145 7.2 Future Work ....................................................................................148

Appendix A: Cypress Microcontroller Code......................................................150 Appendix B: Visual Basic Code ...........................................................................172

B.1 Manual entry program ....................................................................173 B.2 Opto-electronic bit-parallel interface program ...............................183

Appendix C: Firmware Schematics ....................................................................220 REFERENCES .....................................................................................................238 VITA.......................................................................................................................245

ix

LIST OF FIGURES Figure 2.1: Shared-Resource and Tester-per-pin Architectures ...............................9

Figure 2.2: General ATE Architecture......................................................................12

Figure 2.3: Semiconductor Test cost vs. Manufacturing cost...................................14

Figure 2.4: Yield Losses Due to Lack of Accuracy Achievement ...........................15

Figure 2.5: Serial-Scan DFT Chip Architecture .......................................................18

Figure 2.6: Generic BIST Architectures ...................................................................20

Figure 2.7: FPGA Chip Architecture ........................................................................23

Figure 3.1: Cross-section of a Multi-chip Module....................................................29

Figure 3.2: Interconnect fault examples: Open and Short-to-Ground ......................31

Figure 3.3: Improved sensitivity model for partial faults .........................................33

Figure 3.4: Time-based plot of theoretical response.................................................34

Figure 3.5: Prototype Board for Interconnect Test using FPGAs.............................35

Figure 3.6: Control Module Diagram for Interconnect Test Board ..........................37

Figure 3.7: Tester Module Block Diagram for Interconnect Test Board..................38

Figure 3.8: Bi-directional signaling delay conflict ...................................................41

Figure 3.9: Test Support Processor concept minimal configuration......................42

Figure 3.10: Test Support Processor Block Diagram ...............................................44

Figure 3.11: Linear feedback shift register ...............................................................45

Figure 3.12: Test Support Processor Printed Circuit Board .....................................48

Figure 4.1: USB communication path ......................................................................55

x

Figure 4.2: Digital Logic Core design ......................................................................57

Figure 4.3: Digital Logic Core evaluation board ......................................................61

Figure 4.4: Microstrip equations to determine characteristic impedance .................64

Figure 4.5: Client software to FPGA interface .........................................................68

Figure 4.6: Visual Basic interface for the DLC evaluation board ............................69

Figure 4.7: Three-stage DDR output at 622Mbps ....................................................73

Figure 4.8: Combining three low-speed channels into one high-speed channel.......74

Figure 4.9: Multipass technique for capturing multiple bits.....................................75

Figure 4.10: High-speed data 1:2 demultiplexer examples ......................................77

Figure 4.11: Flip-chip printed circuit board cross-section........................................82

Figure 4.12: Digital Logic Core flip-chip continuity checker ...............................84

Figure 4.13: Flip-chip continuity checker printed circuit board ...............................85

Figure 5.1: Application to opto-electronic gigabit-per-second Tx/Rx......................89

Figure 5.2: Waveforms and timing examples of transmitter signals ........................91

Figure 5.3: Opto-electronic test bed block diagram..................................................93

Figure 5.4: Emitter-couple logic circuit diagram......................................................95

Figure 5.5: Opto-electronic transmitter schematic....................................................97

Figure 5.6: Opto-electronic receiver schematic ........................................................98

Figure 5.7: Opto-electronic transceiver printed circuit board................................101

Figure 5.8: Delay calibration error.........................................................................103

Figure 5.9: Delay setup in the software interface ..................................................105

Figure 5.10: Test pattern selection in the software interface .................................106

xi

Figure 5.11: Test pattern entry in the software interface .......................................106

Figure 5.12: Data capture in the software interface...............................................107

Figure 5.13: Two 4-bit wide data words................................................................109

Figure 5.14: Example timing adjustments (1ns increments) .................................110

Figure 5.15: Edge placement resolution 20ps steps............................................111

Figure 5.16: Edge placement resolution 10ps steps............................................112

Figure 5.17: Minimum pulse width (

xii

Figure 6.9: Half-speed Signal Output (2.2Gbps) ...................................................141

Figure 6.10: Demonstration of 4.4Gbps output (A)...............................................142

Figure B.1: Evaluation Startup Window Form......................................................175

Figure B.2: High Speed Interface Form.................................................................178

Figure B.3: High Speed Formatter Form ...............................................................182

Figure B.4: Opto-electronic Startup Window Form ..............................................185

Figure B.5: Opto-electronic Interface Form ..........................................................214

Figure B.6: Opto-electronic Calibration Form.......................................................219

Figure C.1: USB Interface Schematic....................................................................221

Figure C.2: Flip-chip state machine illustrations...................................................223

Figure C.3: Flip-chip primary schematic ...............................................................224

Figure C.4: Flip-chip secondary schematic ...........................................................225

Figure C.5: Opto-electronic USB interface schematic ..........................................227

Figure C.6: Opto-electronic state machine schematic ...........................................228

Figure C.7: Opto-electronic test functions schematic............................................229

Figure C.8: Delay programming schematic ...........................................................231

Figure C.9: Delay reporting schematic ..................................................................232

Figure C.10: Test routine schematic ......................................................................234

Figure C.11: Test reporting schematic...................................................................235

Figure C.12: Wafer-level prober output schematic................................................237

xiii

LIST OF TABLES

Table 2.1: FPGA to ATE comparison......................................................................26

Table 3.1: Digital test patterns for 8 substrate networks .........................................32

Table 4.1: USB read/write data structure.................................................................66

Table 4.2: ATE/DLC comparison............................................................................79

Table 5.1: PECL devices used in the opto-electronic test bed..............................100

Table 6.1: PECL devices used in the wafer-level prober......................................137

Table C.1: Flip-chip state machine definitions ......................................................223

xiv

LIST OF ABBREVIATIONS

Symbols Meanings

ASIC.......................................................Application-Specific Integrated Circuit

ATE ........................................................................... Automatic Test Equipment

BGA............................................................................................. Ball Grid Array

BIST ..........................................................................................Built-In Self Test

CLB .............................................................................Configurable Logic Block

CMOS........................................... Complementary Metal-Oxide Semiconductor

CUT ........................................................................................ Circuit Under Test

DFT .............................................................................................Design For Test

DDR..........................................................................................Double Data Rate

DLC ........................................................................................ Digital Logic Core

DLL ...................................................................................... Delay-Locked Loop

DMA................................................................................ Direct Memory Access

DNRZ ............................................................................... Do Not Return to Zero

DUT........................................................................................ Device Under Test

ECL .................................................................................. Emitter-coupled Logic

EPROM ................................Electronically-Programmable Read-Only Memory

FBA ......................................................................................Failure Bit Analyzer

FPGA.................................................................Field Programmable Gate Array

FPSLIC .........................Field Programmable System Level Integration Circuits

GaAs.........................................................................................Gallium Arsenide

xv

GTL .......................................................................... Gunning Transceiver Logic

HDL.................................................................. Hardware Description Language

HSTL ................................................................... High-Speed Transceiver Logic

IC .......................................................................................... Integrated Circuit

I/O ............................................................................................ Input and Output

IOB ........................................................................................ Input/Output Block

IRL ....................................................................... Internet Reconfigurable Logic

ISA ..................................................................... Industry Standard Archetecture

JTAG .............................................................................Joint Test Action Group

LFSR ...................................................................Linear Feedback Shift Register

LUT .............................................................................................Look-Up Table

LVCMOS ..............Low-Voltage Complementary Metal-Oxide Semiconductor

LVDS ......................................................... Low-Voltage Differential Signalling

LVTTL .............................................. Low-Voltage Transistor-Transistor Logic

MBE ........................................................................................ Multiple Bit Error

MCM ......................................................................................Multi-chip Module

ORA..........................................................................Output Response Analyzers

OTA............................................................................. Overall Timing Accuracy

PC ........................................................................................Personal Computer

PCB .................................................................................... Printed Circuit Board

PCI ............................................................. Peripheral Component Interconnect

PEC ..................................................................................... Pin Electronics Card

PECL .................................................................. Positive Emitter-coupled Logic

xvi

PMU .................................................................... Parametric Measurement Unit

PRNG .........................................................Pseudo-Random Number Generator

PROM ..........................................................Programmable Read Only Memory

PSU ........................................................................................Power Supply Unit

QDR ....................................................................................Quadruple Data Rate

RAM ............................................................................Random-Access Memory

RDA ..............................................................................Response Data Analyzer

RF ........................................................................................... Radio Frequency

RMS ....................................................................................Root Means Squared

RZ ...............................................................................................Return to Zero

SIE ..................................................................................Serial Interface Engine

SOC ....................................................................................... System On A Chip

SRAM ............................................................... Static Random-Access Memory

SSTL ................................................................... Stub Series Termination Logic

TCK ......................................................................................... JTAG Test Clock

TDI ........................................................................................ JTAG Test Data In

TDNA ...............................................................Time-domain Network Analysis

TDO .................................................................................... JTAG Test Data Out

TDR ........................................................................Time-domain Reflectometry

TMS ...............................................................................JTAG Test Mode Select

TPG ................................................................................Test Pattern Generators

TTL .......................................................................... Transistor-Transistor Logic

USB .................................................................................... Universal Serial Bus

xvii

SUMMARY

The Digital Logic Core is proposed in this thesis to address the technological

and economical challenges facing the IC test industry today. The DLC is a

customized circuit that is incorporated into the test environment to enhance the

testability of the DUT by supplementing automatic test equipment (ATE)

capabilities, providing a standalone test bed, or embedding test functionality into

larger systems.

The enabling technology of the DLC is programmable logic, such as field-

programmable gate arrays (FPGAs), which off-loads the ATE test logic and

functions. Previous work used FPGAs for applications which required low speed,

but high test channel count. With the rapid advancement of FPGA technology, the

DLC can now perform most test functions of ATE while maintaining and exceeding

their performance. This level of complexity can be attained while drastically

reducing the cost of current test systems. Furthermore, the rapid development of

FPGA technology exceeds the rate of ATE improvement making this test strategy

more useful into the future.

To demonstrate the feasibility of this concept, several applications are

developed and analyzed including an opto-electronic test bed for standalone

operation and a nano-scale wafer-level prober for embedded system operation.

These systems have been proven to operate at multi-gigahertz speeds which match

and exceed modern ATE specifications. More applications are planned for the near

future which far exceed these rates.

CHAPTER 1

INTRODUCTION

The objective of this research is to provide an economical solution to the

multi-gigahertz digital test problem of digital devices, circuits, and multichip

modules (MCMs) operating at clock frequencies upwards of 10GHz. Testing of

such circuits at full-rated speed is essential to assure the devices meet design

specifications throughout the entire range of intended operation. An additional

goal is to minimize both the cost and physical size of the test device to be of

practical use embedded into a system. Embedding a test device into a system

increases the range of testing options available over standalone devices. This

research presents a cost-effective and verifiable solution to the multi-gigahertz

digital test problem through the use of programmable logic devices.

Testing of circuits, multi-chip modules, and digital systems is crucial to

assure the devices meet the design specifications. Since the invention of

integrated circuits (ICs) in the 1960s [1], the complexity of the technology has

grown along with the cost and sophistication of testing. Today, design and test

are no longer separate issues. Test circuitry built into chips, along with expensive

external test equipment, is used to ensure the quality of shipped products.

2

Testing of integrated circuits is categorized into functional tests

(input/output timing and behavior), environmental tests (power and temperature),

and reliability tests (quality, failure rate, and life expectancy). The most common

tests used in production include acceptance test, sample test, go/no-go test, burn-

in test, diagnostic test, and on-line test. The characterization test is used for both

production and development and is used to verify the design is correct and meets

all of the specifications [2].

Although design-for-test (DFT), either in the form of serial scan methods

or built-in self-test (BIST), can be used to internally verify the structural

characteristics, the need for external test remains to verify full functionality. Most

DFT and BIST methods are focused on verification of logical connectivity and

physical structure but may not fully test the functional characteristics of the circuit

or module. Therefore, a need for testing functional and parametric characteristics

still exists. Many of the structural tests, such as the widely used boundary-scan

method, do not even operate at full clock rate of the device. For applications

where high frequency performance is expected, a need remains for functional

testing at the intended frequency of operation

Modern automatic test equipment (ATE) can perform most of these tests,

but at a high cost. However, ATE is slow to maintain pace with modern advances

in speed, complexity, and physical nature of circuits and modules. The majority

of digital integrated circuit ATE in use today operate at clock and data rates below

1.0 GHz, with cost increasing as frequency increases. The challenge is to provide

a substantial increase in frequency and pin-count while decreasing the overall cost

3

of testing. The challenge must be met to provide for economical testing of

advanced devices, as will be seen in the following discussion.

Part of the problem with current test systems is the historical trend to

always add features to new test systems. ATE manufacturers continue to expand

capability while either maintaining or increasing the test system price instead of

applying technological advancements to try to reduce the price. The next

generation of test systems rarely reduces the number of functions available. The

trend toward increased complexity and variety in semiconductor technologies has

led to equally complex and expensive ATE.

With semiconductor technology continuing into sub-micron dimensions,

speed, density and complexity of the devices is increasing swiftly. Even though

tester electronics are testing higher speeds and more complex devices, the

innovations in the devices being tested are increasing even more rapidly. The

costs of testing per device are also rising due to this gap in performance. New

methods of testing must be found to keep pace with the emerging technologies.

The cost-efficient approach set forth in this work provides simpler high-

performance configurations utilizing programmable devices which assist ATE and

BIST testing and also allows standalone and embedded testing. This approach is

geared not only for specifically high-frequency test generation, but also for

massively-parallel test requirements, nano-scale wafer-level probing, and optical

interfacing. Available chip designs are used to achieve an economic advantage by

eliminating costs associated with custom IC design.

4

This work introduces the concept of a Digital Logic Core (DLC) which

is a re-usable, reconfigurable circuit that can be incorporated into various testing

scenarios either to enhance existing test capabilities or to implement new test

functions. As illustrated in Chapter 4, the test core includes a field-programmable

gate array (FPGA) chip that is used for generating test stimuli and capturing

output responses. The DLC must also be easily interfaced to a controlling

computer and must support a large number of programmable input/outputs (I/Os)

with provisions for large test pattern memory. Furthermore, some applications

(such has gigahertz testing) will require additional logic to achieve advanced test

functions. Therefore the test core must be easily interfaced to other logic circuits.

Several scenarios are imagined where the digital test core can be applied.

It can serve as a support circuit to enhance the test capabilities of traditional ATE.

In some cases the test core may actually take the place of the ATE, requiring only

a low-cost external computer for control. In this case, the test core could even be

replicated to permit parallel testing, such as during wafer probe or burn-in. The

test core could also be embedded within the design of future ATE providing a

reconfigurable solution that achieves advanced test functions and higher

performance at lower cost. The test core may be embedded within a larger

(system-level) circuit for self-test features. In this scenario, the programmable

logic could also be used to perform normal circuit functions when not in the test

mode.

FPGAs are ideally suited for testing because pin density is easily scalable

with a low cost per pin. Even though output data rates are typically limited to

5

about 840Mbits/sec, this is comparable to that of modern ATE. Gigahertz-range

speeds can still be attained by using multiplexing techniques with positive

emitter-couple logic (PECL) circuits as shown in Chapter 4. Using thousand-I/O

FPGAs, hundreds of multiplexed, multi-gigahertz test signals can be produced to

produce terabit-per-second aggregate test data rates

A computer is still needed for the user interface, but it does not need to be

a high-performance workstation because the critical testing logic is contained

within the FPGA. However, sometimes massive amounts of data must be

transferred to the pin electronics, so a relatively high-speed interface is still

needed between the user interface and pin electronics. A common interface in

modern computers is the Universal Serial Bus (USB) standard, operating at a rate

of 480Mbps.

The main components needed for the test core include: (1) an FPGA to

provide the flexible logic, (2) a chip to support computer interfacing, and (3) fast

memory chip(s) for pattern storage. The combination of these components is a

multi-purpose Digital Logic Core (DLC) which is essentially a miniature ATE.

A brief review of the origins and history of digital ATE, the development

of the design-for-testability concept, built-in self-test designs, and enabling

technologies such as FPGAs is given in Chapter 2. This leads into Chapter 3,

which explores the use of FPGAs in different configurations to perform testing.

The first configuration uses multiple FPGAs to provide a massively-parallel

interconnect test method. The second configuration uses an FPGA to minimize

the timing problems associated with bi-directional data buses. Chapter 4

6

introduces the concept of the Digital Logic Core which utilizes an FPGA to

perform many functions of ATE. The details of realistically implementing the

DLC are discussed, and an example application is described. Chapter 5 describes

another application of the DLC in an optoelectronic test pattern generator and

receiver which can also be used as a high-speed electronic tester. The latest

application is described in Chapter 6 as a nano-scale wafer-level prober for pre-

packaging testing of silicon devices. The appendices included are the

microcontroller source code and Visual Basic source code for interfacing the

DLC, and detailed schematics of the FPGA firmware.

CHAPTER 2

BACKGROUND 2.1 Automated Test Equipment

Most modern testing is performed using generalized test machines which

can probe many channels at once. These machines can perform many different

types of tests and come in a variety of configurations. Some ATE can test optical,

mixed-signal, and radio frequency (RF) devices, but in this thesis, the specific

ATE referred to are the dedicated digital testers. These testers perform

characteristic testing on digital-only devices through specialized pin electronics.

Without digital ATE, testing can be cumbersome and costly by performing each

test with a different test machine or by hand as was originally done.

2.1.1 ATE History

In the late 1980s and early 1990s, high speed digital testing entered into

the gigahertz range. At this speed, digital ATE methods and architecture were

unable to maintain pace with the rapid semiconductor evolution. In order to meet

new requirements, several ATE producers and company-internal research groups

began to develop testers with enhanced accuracy and frequency capability [3-7].

8

An example of state-of-the-art digital ATE in 1984 was the Cybernetics

Viking 200 capable of 100 MHz, costing $0.9-1.9M for a 256-pin system [8].

The Megatest Mega One and the Tektronix S-3295 used concepts such as

frequency-doubling by multiplexing adjacent pins and the tester-per-pin

architecture [8]. The cost of the digital ATE started approaching $1M to $3M for

a 256-pin system. These systems had edge placement timing accuracy of about

0.5ns to 1ns, and edge placement resolutions of around 100ps.

Up to this point, a shared-resource architecture was used in digital ATE

systems. Using switching or multiplexing techniques, a single timing generator

and voltage-level generator circuits are shared among several test system

channels. A small amount of dedicated per-pin electronics, such as formatters or

comparators, can serve as the interface to the device under test (DUT). This

allows for a cost advantage at lower pin counts. As pin counts increase, other

factors such as tester calibration and programming become very tedious because

of signal routing. As speed increased, the multiplexing section (usually magnetic-

reed relays) presented bandwidth limitations and additional calibration

uncertainty.

One of the main transitions was from this shared-resource architecture

to a per-pin architecture [8]. In this method, all pin electronics and pattern

generation are included in each pin of the test system. The multiplexing network

and complex switch algorithms are eliminated. The architecture is more

simplistic and easier to use since each channel is independent and may be

addressed independently. The cost of the system is reduced because of simplified

9

programming and is scalable with number of pins. Each pin can also be

independently calibrated which increases accuracy. The simplified structure is

shown in Figure 2.1.

Shared Resource Pin Electronics

Multiplexing Network

Dedicated Pin Electronics

Shared-Resource digital test architecture

Per-Pin digital test architecture

Test Head A

Test Head B

Fully Dedicated Per-Pin Electronics

Pin1Pin2

Pin3Pin4

Figure 2.1: Shared-Resource and Tester-per-pin Architectures

By 1990, the Hewlett-Packard 200/400 MHz HP82000 tester became

available and illustrated this new architecture. Up to this point, the MECL 10K

series [9, 10], released in 1971, was the leading logic technology with operating

frequency up to about 200MHz. But about the time the HP system became

available, Motorola [11] and Sony [12] released a new series of emitter-coupled

logic (ECL) device families operating at peak frequencies above 3GHz. GigaBit

10

Logic released a gallium-arsenide (GaAs) standard family with edge rates below

100ps [13].

The need to test at gigahertz rates led to the development of company-

internal systems due to lack of commercially available ATE systems operating at

this speed [3]. Custom application-specific integrated circuits (ASICs) or gate

array designs integrated the functionality of pin driver buffers, low voltage

overdrives, and high-sensitivity comparator designs [3-7]. Using custom chips,

performance was pushed to the 500MHz range [3] and new architectures were

introduced such as the sequencer-per-pin architecture [4] and algorithmic

pattern generation [5]. But some of the complex architectures become unusable at

gigahertz frequencies due to delays in feedback paths, bandwidth limitations of

specific parts, and timing errors.

Random noise (like jitter) and systematic errors are the two basic

categories of timing errors. Jitter is defined as short-term non-cumulative

variations of the significant instants of a digital signal from their ideal positions in

time [14]. Systematic errors are more significant than random errors and are

divided into four main categories: crosstalk, thermal effects, impedance

mismatches, and bandwidth limitations [15]. Good system design can minimize

these effects along with highly accurate test system calibration and performance

characterization. Calibration techniques often send a signal through a specialized

probe or multiplexed channels which routes back into the test system. The timing

information is used for delay measurements [16] or time-domain reflectometry

(TDR) to automatically calibrate each channel [17].

11

By the mid-1990s, Hewlett-Packard introduced the HP 83000-F660 tester

[9, 10] capable of 666Mbps. The timing accuracy for this system is +/-50ps with

10ps programmable edge placement. System cost still remains in the $1M-$3M

range scalable for number of channels. Since then, Hewlett-Packards test

division has become Agilent, but the 83000-F660 is still a top-of-the-line ATE.

2.1.2 Modern ATE Architecture

With the high costs of ATE, the test system must perform a wide range of

diagnosis and analysis to make them practical. The primary objective is to ensure

the DUT operates within its specifications. If the DUT fails to meet its

requirements, then the ATE can be used to isolate defects for process

augmentation or failure analysis support. The ATE must also be able to

determine the performance limits and device operating margins such as setup and

hold time, propagation delay, and threshold levels. As the needs of new

technology increases, so does the complexity of the ATE, yet the basic structure

remains constant.

An ATE must have these main capabilities: a power supply unit, cooling

unit, development workstation, and tester mainframe as shown in Figure 2.2. The

power supply unit (PSU) must be able to provide a high current while maintaining

a precise voltage with minimal background noise. Usually more than one voltage

level is required for modern devices, so most PSUs can provide at least four

differential voltages. With the high amount of power dissipation, normal air

cooling becomes insufficient to regulate the temperature of the devices. Liquid

12

cooling systems control temperature more reliably and also reduce the air

conditioning requirements of the work area. The development workstation

provides the test conditions, displays the results, and further diagnoses faults [18].

This host computer is used by the test engineer to set up all tests and test flows for

characterizing, debugging, and verifying the DUT.

Cooling Unit

Power Supply Unit

Control DeviceTo Development Workstation

Tester Mainframe

Memory Pin Electronics To Device Under Test

Master Clock

Calibration

Communication

Compression

Sequencer

Error Map

Storage

Formatters

Comparators

PMU

Figure 2.2: General ATE Architecture

The tester mainframe houses the major electronic circuitry which consists

of the control device and input/output devices. The control device contains the

calibration circuits, the communication interface to the workstation, the data

compression/decompression logic, and the master clock which controls the timing

generator. The input/output devices provide the test stimuli, capture the DUT

13

output responses, and contain the parametric measurement unit (PMU) [18]. Each

I/O device contains memory modules and pin electronics cards (PECs). Since

modern ATE has per-pin architecture, each pin has a unique formatter,

sequencer, and timing generator [4]. During a test, the stimulus test vectors are

output from the memory and formatted by the pin electronics to the correct shape

and timing. The responses from the DUT are then captured by the pin electronics,

compared with expected data values, and then stored into the memory module

[18].

The entire architecture of ATE can be scaled to the needs of each

individual, but the basic structure remains the same. Device scaling tends towards

lower voltage, better timing accuracy, higher clock rate, higher pin count, and

extended test patterns. As technology continues to increase demands on ATE,

manufacturers continue to add new features and upgrade systems. Since older test

functions are maintained in systems, cost continually increases as well.

2.1.3 ATE costs

The cost of electrical testing is a major factor in developing and

manufacturing of semiconductor devices. While the fabrication cost per function

has decreased 25-30% annually, test cost per function has decreased only 5-10%

annually [19]. The test cost per function is projected to remain about the same in

the near future. Since testing represents

14

1960 1970 1980 1990 2000 2010 2020 2030 2040

Cos

t Per

Fun

ctio

nTest CostManufacturing Cost

Figure 2.3: Semiconductor Test cost vs. Manufacturing cost [20]

33% to 50% of the IC production cost now, in the future it may cost more to test

semiconductor devices than to manufacture them [20] as predicted in Figure 2.3.

Digital ATE manufacturers offer a wide assortment of test systems with

different sequencing and throughput capabilities, as well as different accuracies

and pattern depths. The cost per channel of a typical test system varies from

about $3,000 per channel to $10,000 per channel. Therefore, a 256-channel ATE

system can range from $0.8M, to almost $3M. If the tester is to be used for

production, then per-part cost varies as a function of the number of devices tested.

For example, if a $3M digital ATE is purchased to test one million chips, then the

testing cost of each chip is $3. Modern devices are now exceeding 1,000 pins per

part and speeds into the gigahertz range. This can drive test system costs into the

$10M to $30M range, so the number of chips tested must be very high to justify

the capital expenditure. If the systems are testing modules instead of individual

15

chips, then the volume will probably be much lower which increases the per

module cost.

Until now, the DUT time period has decreased at almost the same rate as

the overall timing accuracy (OTA) of the ATE at the rate of 12% per year [21]. In

the future, the DUT time period will continue to decrease, but the OTA is

projected to remain constant at about 100ps. Since the ATE must control timing

of individual events to within 1% of the device clock interval and the OTA must

remain with 5%, yield losses have continued to increase [22] which leads to

increased cost per chip as shown in Figure 2.4.

10

100

1000

10000

1985 1988 1991 1994 1997 2000 2003 2006 2009Year

Tim

ing

Acc

urac

y (p

s)

0

25

50

75

100

Perc

ent Y

ield

Overall ATE AccuracyATE Accuracy NeededEstimated Yield

Figure 2.4: Yield Losses Due to Lack of Accuracy Achievement [22]

By the year 2014, the price of ATE is projected to surpass $20M unless

major changes are made in the architecture [23]. The cost continues to rise

because the basic capabilities of the ATE must keep up with increasing demands

such as higher operating frequency, higher pin count, better timing accuracy,

increased volume of test patterns, and lower voltage. As features are added to

current test systems, manufacturers make test equipment more complex and more

16

expensive to maintain and may not even be compatible with the current

architecture.

2.2 DFT and BIST technology

One method of reducing costs and enhancing testability of components is

to consider testing methods up front during system development [24]. When

devices are designed for testability (DFT) early in development, either in the form

of serial scan methods or built-in self-test (BIST), design engineers work with the

test engineers early in development to select the best design strategy for testing

purposes. Selected test methods should meet both cost and performance goals.

This technique has been widely used in IC design and testing. [25-28].

Most modern IC designs implement DFT techniques and diagnostic

functions which usually result in less test development time, smaller test

generation cost, and higher fault coverage. DFT techniques can affect ATE needs

as well by reducing tester memory requirements and shortening test application

time [29]. Other uses have evolved out of this kind of designing such as

enhancing debug capability, supporting process characterization, lowering burn-in

cost, and automating test generation and test process. However, even though

some costs are being reduced, other costs increase such as number of I/O pins,

silicon area and test time [30].

With DFT techniques, testing does not only need to be limited to

production. Even though a device may work at production time, it may fail

shortly after leaving the manufacturing facility. A system in field operation can

17

carry out a self-test and diagnose a fault to a particular part. The faulty part can

be replaced without having to swap the entire system. This concept is called two-

level maintenance which extends the life-cycle costs. [30].

Design for testability techniques usually refers to serial scan tests and

built-in self-test. Scan-based designs are the most popular external testing

methods that observe and control the device pins with scan chains, but other

methods are used such as full serial scan, partial serial scan, non-serial scan, and

system level scan [30]. Typical examples of scan-based designs are the Joint Test

Action Group (JTAG) Boundary Scan Standard [31] and the IEEE 1149.1

Testability Bus Standard [32]. The standards address the use of a test bus and the

protocol associated with it, the bus master, the I/O ports which connect the chip to

the bus, and the control circuitry to interface the BIST application portion of the

chip [30]. Serial-scan DFT is often used to assist the BIST. An example of

serial-scan and BIST architecture is shown in Figure 2.5.

18

Data In

Data Out

Control Signal

Control Clock

Miscellaneous Registers

MU

X

CUTC

ontro

ller

Bypass Register

Instruction Register

Figure 2.5: Serial-Scan DFT Chip Architecture

The IEEE 1149.1 standard defines a test bus and interface for boundary

scan architecture, which is widely adopted by the IC industry. This boundary

scan test architecture consists of four signals: the test clock (TCK), the test mode

select (TMS), the test data in (TDI), and the test data out (TDO). Test instructions

and test data are sent through the TDI input to the scan register in each chip in the

system. Test results and status information are sent back from the chip on the

TDO line. Each device has certain functions implemented as defined by the

standard such as loading and unloading of the boundary-scan registers.

Additional functions can be included specific to the device for other internal

testing. The sequence of operations is controlled by the bus mode select which

19

can be controlled either by an ATE or other test equipment for this specific

purpose [56-59].

The standard also allows for multiple circuits to be serially chained

together so only one test port is needed. Each device has its own identifying

address which is included with every operation request. If the request does not

include the devices address, the request is passed on to the next device in the

chain. If all devices in a system use this standard, then only four test channels are

needed to verify all of the connectivity of the system.

2.2.1 BIST architectures

While scan-based designs test external elements of the device, BIST

checks internal logic structures. BIST techniques are especially important for

embedded devices where it is difficult to access the device I/O pins. BIST can be

defined on the chip, board, MCM, or system level and falls into two categories:

online and offline. Two types of online BIST are concurrent, which operates at

the same time as normal functioning, and non-concurrent, which tests when the

system is in an idle state. Offline BIST deals with testing the device while not in

normal operation and cannot detect errors in real time. Two generic types of

offline BIST are functional and structural [30].

Offline BIST circuitry is classified as either centralized or distributed.

Similarly the BIST elements are classified as either embedded or separate. The

elements vary between designs, but most use standard components such as test-

pattern generators (TPGs), output-response analyzers (ORAs), the circuit under

20

test (CUT), a distribution system (DIST) to manage data between the previous

three elements, and a controller to manage the BIST circuitry and the CUT.

In centralized BIST architecture, shown in Figure 2.6, several CUTs share

TPG and ORA technology. Less circuitry is used, but at the expense of increased

test time. Conversely, a distributed BIST architecture often uses functional

elements with the CUT. The result leads to a more complex design to control but

with less separate circuitry and decreased testing time. The choice of which

architecture used is governed by many factors, such as level of packaging, fault

coverage, degree of test parallelism, performance degradation, and test time [30].

Figure 2.6: Generic BIST Architectures

The self-test requires some parts of the circuit to be operational. This is

generally referred to as the hardcore of the system. Usually the hardcore contains

power, ground, clock distribution circuitry, and other managing circuitry such as

the BIST controller. If any of the hardcore circuitry is faulty, then the self-test

might indicate a failure in the CUT. The hardcore is usually difficult to test

21

clearly, so ATE is often used to test the hardcore, or redundancy is implemented

to make the hardcore self-testing.

The employment of DFT is also limited by physical restrictions such as

chip size, weight, power, and cooling cost. Adding testing hardware inside a chip

increases the silicon area, which increases all of the physical problems. If

hardware is added along critical timing paths, it may restrict the speed and

degrade the testing performance. Also the DFT cannot test the performance of

external driving transistors, debug device and process defects, sufficiently address

testing needs associated to field failures, nor test all circuit fabric types.

2.2.2 DFT and BIST costs

While online testing can be very helpful in observing and diagnosing

errors, the complexity of the circuitry usually makes the device not cost effective.

Only in applications where the cost is justified, such as the medical field or

satellite technology, can it be implemented effectively. Offline mode testing is

usually more practical and therefore more widely used [30].

While DFT can do a wide variety of testing, it cannot replace all testing

with conventional ATE. Since DFT often requires large silicon overhead on each

IC, it is usually not a cost effective solution for complex devices. Even with

extensive use of DFT, it is usually not designed to exercise at-speed functional

tests or characterization tests [33]. DFT is often designed to compliment ATE

systems, so even though an IC may have over a thousand pins, only a few are

needed to connect to the ATE. Since the main cost of modern ATE is in the

22

number of pins, the ATE expense can be reduced by a factor of ten or more [23].

Some system manufacturers implement DFT effectively enough to lower the ATE

cost to only $200/pin [21]. By utilizing boundary scan methods with parametric

tests, the number of ATE full-function pins can be reduced to less than sixty for

the highest pin-count devices, allowing the other pins to be used for parametric

testing.

2.3 Programmable Logic Technology

By 1985 the first field programmable gate arrays were introduced. Xilinx

developed a family of standard user-configurable products utilizing industry

standard SRAM technology. Design engineers who had access to a desktop

computer could use FPGAs along with a relatively low-cost design tool which

made gate array technology easy to implement [34].

Even though many families of FPGAs vary in their specific functionality,

the basic layout is the same. Small units of configurable logic blocks (CLBs)

provide the majority of the logic in the chip. They consist of look-up tables

(LUTs), which provide the combinatorial logic, and latches or flip-flops, which

provide the sequential logic. The CLBs are interconnected through a routing

network of short (direct CLB to CLB) and long (clock distribution) interconnects.

The network is also connected to input/output blocks (IOBs) for data transmission

on to and off of the FPGA. Other functionality can be employed depending on

23

the needs of the designer, such as memory elements or delay-lock loops (DLLs)

for clocking [35]. All these elements are shown in Figure 2.7.

CLB

IOB Switching Network

IOB

IOB IOB

Switching Network

Switching Network

Switching Network

CLB

Figure 2.7: FPGA Chip Architecture

Originally, the chip industry was utilizing thousands of gates of logic into a

single FPGA. Today, manufacturers can put an entire system on a chip (SOC)

which not only integrates the programmable and ASIC logic onto a single chip,

but also adds processor, memory, and analog functions. New families of products

being released which address programmable SOC are the Atmel FPSLIC (Field

Programmable System Level Integration Circuits), which includes the Atmel

AVR RISC processor, and the Xilinx Virtex-II Pro, which includes the IBM

PowerPC processor [34].

FPGAs are known for providing designers with several benefits in system

design. One of the most important is shortening time-to-market. The quicker a

24

company gets its products to market, the higher percentage market share it can

capture from competitors. Research institutes can prototype designs without

needing to create multiple ASICs. The flexibility provided by FPGAs can allow

designers to modify their firmware up to the day the product is released to

customers. With the concept of Internet Reconfigurable Logic (IRL), designers

can modify their designs after the products have been shipped to customers [36].

One of the advantages inherent in FPGAs is the fault-tolerant behavior.

Using special DFT techniques, part of an FPGA can fail, and still maintain full

functionality. If the FPGA is configured with a BIST program, the faults can be

analyzed and reported to the designer. The designer then reconfigures the device

to route around the faulty areas of the FPGA [37]. A more complex program can

be used to automate this procedure. This is based on an on-line self-test and

repair approach which involves both network configuration and logic

reconfiguration. The former applies whenever a fault affects the routing of

signals, and the latter applies to a CLB failure. If a fault is detected by the self-

test, the part can reconfigure itself and route around the faulty parts. While not all

faults can be corrected (such as IOB failures) the lifetime of the FPGA can be

extended. If the FPGA is embedded into larger system, this can also extend the

lifetime of that application. Some applications where repair or replacement is not

cost effective like space or arctic environments, online self-test and repair is

critical to maintain operation [38]. Fault tolerance is also necessary in test

applications. The first step in making an accurate test analysis is to ensure the

functionality of the test equipment [21].

25

Until recently, the cost per programmable gate was very high which

created a price penalty for utilizing the benefits of FPGAs. The cost of creating a

prototype ASIC was lower than the cost of using programmable gates. The gate

density on FPGAs has increased steadily with little change in the price range,

which has decreased the price per gate. FPGAs have surpassed the multi-million

gate per device level, and that number will continue to increase. This trend allows

for larger designs and the ability to absorb the functionality of other on-board

chips. Fewer chips mean lower cost and more efficient circuit board layout. Now

that FPGAs are more attractive in high volume applications, the price has reduced

to the point where they compete more evenly with ASICs [39].

The performance of FPGAs has always lagged that of ASICs. ASICs are

built with cutting edge technology and optimized for each design. Even though

ASICs will always be faster, FPGAs are not far behind. On-chip and I/O

performance has increased steadily since the introduction of FPGAs [40]. With

internal clock speeds approaching 420MHz, high speed applications can be

implemented [41]. With software optimization, internal delays can be minimized

[37].

Since FPGAs are used in a wide range of applications, a wide range of

interface options is necessary. Currently available FPGAs have I/O technology

capable of speeds upwards of 840Mbps which can interface other high speed

circuits. FPGAs are also capable of using different voltage levels to conform to

the standards used by other on-board chips. As newer standards evolve, the

FPGAs can be easily modified either on or off chip to interface with them. Along

26

with performance, the number of general purpose I/Os has risen into the

thousands. This enables the FPGAs to interface with many different chips at once

or chips with very high pin counts [41].

The more advanced FPGAs become, the more similarities they have to ATE

systems. FPGAs and ATE both have a high signaling rate, high channel count,

and a wide range of configurable interface options. High-end ATE systems

operate at about 1.6Gbps per channel, while FPGAs operate at about 840Gbps per

channel. Pin counts for high-end FPGAs surpasses many ATE systems, but at a

much lower cost. This comparison is shown in Table 2.1.

Table 2.1: FPGA to ATE comparison

FPGAs ATE

Throughput per channel 840Mbps 1.6Gbps

Maximum channel count ~2,000 ~500

Cost per channel $1-$2 $10,000-$100,000

CHAPTER 3

USING FPGAS IN TESTING

By using FPGA technology, tester electronics can keep pace with increasingly

advanced devices. Modern FPGAs approach input/output speeds of high-end ATE

and have the flexibility to perform the same tests. By complimenting the FPGA with

high-performance circuitry, speeds can exceed current ATE and provide support for

current and future devices. Adding support circuitry internal and external to the

FPGA removes the reliance on ATE to provide a standalone tester and even enable

the test circuitry to be embedded into systems. This chapter explores previous work

completed using FPGAs for testing. This provided the framework for creating

standalone/embedded test systems utilizing FPGAs.

3.1 Massively-parallel interconnect test method

In an initial research project using FPGAs, a low-cost massively-parallel

interconnect test method for multi-chip module substrates was designed and built.

Due to the large number of general purpose I/Os, FPGAs provided an excellent

solution for testing a large amount of substrate interconnects. Previously, wafer

28

probing was accomplished by using a flying prober where only very few

interconnects are verified per cycle. The prober would physically move across the

wafer and individually contact two points on an interconnect. After checking for

faults on the line, the prober would then move to the next interconnect and continue

the process until all possibly faults were accounted for. But by using multiple

FPGAs, all of the interconnects can be tested at once [42].

3.1.1 MCM interconnect test concept

A multi-chip module consists of silicon chips fabricated separately and then

packaged into one device. The individual chips are mounted onto a routing layer

which connects them internally and externally. These signals can be routed to other

chips inside of the module or can be routed to the base substrate which houses the

power and ground planes. The signals can also pass through the base substrate to the

I/O pins on the package to interface externally. A cross-sectional diagram of an

MCM is shown in Figure 3.1.

29

Known Good Die

Signal Layers

Base Substrate

Power/Ground Planes

I/O Pins

Figure 3.1: Cross-section of a Multi-chip Module

A wide variety of substrate test methods are currently in use which include

capacitance [43, 44], resistance[44, 45], electron beam[46, 47, 48, 49, 50], latent open

testing [51], time domain network analysis (TDNA) [52], and tuned load probing

[53,54]. Other test methods using digital test patterns provide a potential solution for

testing of high density substrate interconnections [55, 56, 57, 58]. These methods are

currently applied after die attachment to verify the integrity of the bonds to the

substrate. Defect detection is limited by the boundary scan implementation of the test

patterns.

The individual faults that can occur on the signal interconnect layer are opens

and short circuits. An open is a complete break in a network that results in very high

30

(>10M) series resistance. A short is a low-resistance (

31

Driver Enabled

Driver

Receiver

011010101

011010101 Receiver

Driver

Driver Disabled

000000000

Open

Driver Enabled

Driver

Receiver

011010101

000000000 Receiver

Driver

Driver Disabled

000000000

Short-to-Ground

Figure 3.2: Interconnect fault examples: Open and Short-to-Ground

3.1.2 Generation of test patterns

The tester has access to each node on the substrate network which allows one

technique to diagnose all shorts and opens. For a set of n isolated nets, a signature

of length N where

N = [log2(n)+2] (3.1)

will detect all shorts and opens. For example, in the case of eight nets, a signature of

length five is required to perform the test. The signatures are assigned as shown in

Table 3.1.

32

Table 3.1: Digital test patterns for 8 substrate networks

Net 1 01000 Net 2 01001 Net 3 01010 Net 4 01011 Net 5 01100 Net 6 01101 Net 7 01110 Net 8 01111

The first two bits are set to 01 on all channels to distinguish shorted nets

from shorts-to-ground or shorts-to-power depending on whether ones or zeros

dominate on a channel under contention. For example, if net A was give code 01011

and net B was given code 10100 and the networks were shorted, then the all zeros or

all ones pattern would be received. However, if a transition occurs on all signal lines,

then the codes will not resemble the short-to-ground or short-to-power pattern. Since

each channel has a unique code associated with it, analyzing the return data can

determine which nets are faulty. Any nets with the same code received are shorted

together.

3.1.3 Partial fault detection

While this method is effective as detecting and diagnosing catastrophic faults,

it has a limited sensitivity to partial failures. These faults are often called near faults

because they dont always lead to immediate failure of the system. Instead, they

cause degradation in signals and may lead to shortened lifetime of the system.

33

A fault can be modeled as a resistor between nets, power, or ground. A no-

fault condition would be an infinite resistance, whereas a catastrophic fault is a

resistance very near zero. If the resistances is somewhere inbetween (in the range of

~100), then the FPGA alone cannot reliably detect the fault. To improve sensitivity

to these partial faults, a capacitor of known value can be added to the driver side of

the probe as shown in Figure 3.3.

RS

Ro

Substrate

VBRIN

RG

VA

Vin RG

Test Channel A Test Channel B

Active Driver Receiver(Driver Disabled)

CG CG

Figure 3.3: Improved sensitivity model for partial faults

When a transition occurs on a driver, the capacitor will limit the rise and falls

times. These rise and falls times are dictated by the RC time constant (). When the

voltage reaches a certain level, the receiver signals a transition. By adjusting the

strobe timing through a linear search method, the time between driving a logic level

change and receiver the change can be measured. This time is directly related to the

34

RC time constant. Once the rise or fall time has been measured, a simple calculation

will result in the resistance measurement.

ROCG (3.2)

RO / CG (3.3)

The fault resistance can then be computed and as a result, the accuracy of

detecting partial faults is improved by an order of magnitude [59-61]. This timing is

shown in Figure 3.4.

Driver ADriver A

Receive BReceive B

Receive AReceive A

Time

VVAA

VVBB

RROOCCGG

Logic OneThreshold

Logic OneThreshold

0

1

0

1

0

1

0

1

0

1

t1 t2

Figure 3.4: Time-based plot of theoretical response

3.1.4 Test implementation

The required components for the test system are electronic instrumentation

with sufficient channels to test the substrate, a method to contact to the substrate, and

35

a computer to control the test and process the results. A low-cost prototype test

system was constructed using an ISA interface and multiple FPGAs to provide 128

channels as shown in Figure 3.5. Each FPGA includes the logic required for 16

driver/receiver pairs. This card is inserted directly into a personal computer ISA bus

so a larger test system can easily be assembled using several identical cards. A

computer program handles the configuration of the test channels to drive and receive

the signatures and process the results. In addition to improving throughput and

recurring test cost, this approach requires minimal capital investment [59-61].

I/O Pins for Tester ChannelsControl Chip

8 Tester ChipsPC ISA Interface

FPGA Configuration

Figure 3.5: Prototype Board for Interconnect Test using FPGAs

36

Once the prototype board is developed, it must be programmed since the

FPGAs are only empty arrays of logic before configuration. The firmware is

designed using a CAD program on the computer which is easily modified and

downloadable. The controller FPGA is designed to interface to the PC through the

ISA bus, process all incoming and outgoing data, control the test process, and issue

instructions to the eight tester FPGAs. Each of the eight tester FPGAs contain the pin

electronics and uses the same code to perform each test. The results of those tests are

returned to the controller FPGA. Using FPGAs enables the test engineer to make

quick changes to the firmware which accelerates the test development time.

The control module is designed to select one of sixteen tester modules and

pass information to and from the controller computer. Only eight tester modules are

implemented on the prototype board, but a double-sided printed circuit board could

be created to use all sixteen modules. The main purpose for this module is to

minimize the number of ISA address busses used since there are a finite number of

available addresses. The specific address used on each board can be programmed

with either the DIP switches or hardcoded into the control module. The basic layout

of the firmware is shown in Figure 3.6.

37

Interface to PC ISA

RegisterFile

Dat

a B

us [7

:0]

4x16Decoder

Interface to Pin Electronics FPGA

s

ErrorRegisters

Enab

les [

1:0]

Read/Write Control [2:0]

Chip Select [15:0]

Return Data [7:0]

Writ

e En

able

Rea

d En

able

Figure 3.6: Control Module Diagram for Interconnect Test Board

Each test card can be configured to operate on a different bus address so many

different cards can be used at once. With this prototype, the number of test cards

usable at once is limited by the size of the ISA bus. The physical size of the board

also limits the number of test channels. However, with further development both of

these limitations are easily overcome so a test system can be developed to meet the

needs of any MCM.

The test vectors are transmitted through the control module to the tester

module where the data is processed and transmitted to the substrate under test. The

tester module also receives the results from the substrate and processes the data

before returning it to the control module. The block diagram is shown in Figure 3.7.

38

State Machine

DriverRAM

Enab

lePC

Interface

DriverEnable

ReceiverRAM

ErrorRAMXOR

Writ

e En

able

Substrate Under Test

OutputSelect

I/O D

ata

Bus

[7:0

]

Writ

e En

able

Control

IRQ

Writ

e En

able

Out

put S

elec

t

Figure 3.7: Tester Module Block Diagram for Interconnect Test Board

The data sent from the computer is formatted in two blocks: driver setup and

test vectors. The driver setup data is latched, and the test vectors are stored in an on-

chip RAM. Once the computer signals the test to begin, the data is sent sequentially

to the output pins. In the next cycle, the returning data is captured in another RAM.

At the same time, it is compared with the sent data to detect any errors, which are also

stored in a RAM. Once the test is completed, the computer can perform one read to

see if any errors occurred during the testing. If so, the specific errors can be

transmitted back to the computer along with the raw capture data to perform fault

diagnosis.

The software to perform the diagnosis of the faults is written in the C

programming language. This program provides test vectors to transmit and diagnoses

39

errors reported. However, the channels need to be configured manually. A more

complex program could be designed to interface with the substrate layout software to

automatic generate the interconnect netlist. The software could then automatically set

up the test vectors for each substrate. The only remaining step would be to configure

the bed-of-nails physical interface to the substrate.

Even though this design fulfills all the requirements of a standalone tester, the

technology used would limit its functionality. This prototype was constructed in

1998 using top-of-the-line FPGAs. Even though the technology was cutting edge, it

was not fast enough to compete with high-end test equipment. However, this specific

application did not need high-speed I/Os. However, faster FPGAs could reduce

testing times and enhance resolution of the resistance measurements.

Since previous testing methods tested one interconnect at a time, this

technique increases test time by testing many interconnects at once. With the

evolving FPGA technology, the usefulness of this style of testing has greatly

increased. Even though each FPGA was limited to 16 test channels per device,

modern FPGAs have hundreds of test channels per device in packages one-quarter of

the size.

This device laid the foundation for a standalone tester using FPGAs. Even

though this device was designed using a top-down approach for testing MCM

interconnects, the method of using FPGAs in testing has since become the focus of

interest. This test system could easily be replaced by a modern version using almost

one tenth of the area and far more test channels. The rate of development of FPGA

technology shows this form of testing to become even more practical in the future.

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3.2 Test Support Processor

In testing fast-switching I/O pins, one challenge is to minimize the

interconnect lengths while providing a controlled-impedance well-shielded

transmission path. Even using the best available packaging technology, the pin

electronics in ATE are physically distributed throughout the test head which has a

typical volume of to 1 cubic meter [62]. The distance between the DUT pin and

the ATE pin electronics is at best 10 cm, and may be as much as 80 cm. The round

trip delay for this distance is about 1ns and can be as much as 8ns.

When a test channel is operating in a bi-directional configuration, a conflict

can occur when switching between input and output modes as shown in the Figure

3.8. A restriction is necessary on the allowed sampling time for the receiver to ensure

that the DUT outputs are not enabled while the driver is active. To test gigahertz bi-

directional signals, this distance must be reduced to 1cm or less because the switching

frequency is limited by this round trip delay (Tpd) [63]. If the round trip delay is 2Tpd,

then the allowed DUT I/O pin switching frequency has to be less than 1/(2Tpd) to

avoid corrupting the driving signals.

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DUT Input Signal DUT Output Signal

Driver Output

TPD TPD

Signal

at DUT

Signal

at ATE

ATE Input

Driver Conflict

Figure 3.8: Bi-directional signaling delay conflict

3.2.1 TSP concept

One method to reduce this limitation of testing bi-directional pins is to reduce

the length of the bi-directional signal trace. If the ATE tri-state drivers and high

input-impedance comparators are very close to the DUT pin (

42

TSP decodes these signals into separate driver and receiver channels which it

transmits directly back to the ATE. These separate channels can be calibrated so the

length between the TSP and ATE will not limit the test frequency.

ATE

PCB

Test Socket

DUT

TSP

~1 inch

Figure 3.9: Test Support Processor concept minimal configuration

In this example, the distance between the TSP and the DUT is about one inch

which translates to about 150ps round-trip delay [65, 66]. By removing the socket

and optimizing the fixture, the round-trip delay could be as little as 30ps (0.2 inches).

At that length, transmission line effects are minimal, and matching resistors could be

eliminated. Furthermore, because the unidirectional channels to the ATE can be

operated at fixed logic levels dictated by the TSP, the pin electronics can be replaced

by simpler line drivers and receivers which will work at fixed voltage levels. This

method will maintain signal quality while permitting fast I/O switching.

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3.2.2 TSP prototype implementing FPGAs

Using an FPGA as the TSP is the easiest way to demonstrate this concept.

The FPGA is fully programmable to perform the signal processing. It has many

general-purpose I/Os to connect both to the DUT and the ATE which can operate at a

variety of signal levels. The FPGA can also synchronize asynchronous signals,

perform signal processing, or generate real-time algorithmic patterns.

The structure in the FPGA can be as simple as a tri-state driver and receiver.

Precisely timed data signals are transmitted from the ATE to the FPGA, which are

then encoded onto the bi-directional channel to the DUT. Along with the data,

precisely timed enable signals must also be sent to activate the tri-state drivers. At all

times, the receiver is transmitting data back to the ATE for analysis. Sometimes the

returning data is being sent from the ATE and sometimes from the DUT.

Even though the basic function of the TSP is to decode bi-directional signals,

with the incorporation of FPGAs, further functionality can be explored. In certain

applications, the data transmitted to the DUT can be predefined in the FGPA. In this

situation, the ATE will still transmit precisely timed signals for the tri-state drivers,

but the data will be generated internal to the FPGA. This reduces the number of test

channels needed from the ATE. The block diagram for this configuration is shown in

Figure 3.10.

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ATE DUT

HP83000-F660

FPGA

Xilinx XC4008E MCM69P819 SRAM

PC

FPGA Configuration [7:0]

60

TPD 100ps

Control Bus

Tri-state Drivers

Output Data

Input Data

Figure 3.10: Test Support Processor Block Diagram

3.2.3 Pattern generation and analysis in FPGA TSPs

Since FPGAs contain more than I/O decoders, other functions could also be

included. Modern ATE has difficulty in testing asynchronous signals. With an

intermediate TSP, those signals can be synchronized for processing by the ATE. The

data sent to the circuit can be generated internal to the FPGA or preprogrammed on

configuration. The FPGA can also do processing on the output from the DUT. If the

ATE is only testing the error rate of the data, the FPGA can be programmed to expect

a certain pattern from the DUT and report the deviance from that pattern. The FPGA

then takes on the role of an output response analyzer.

The test pattern generation circuitry is critical in testing devices. It assists in

determi