An Extraction Method of the Energy Distribution of Interface Traps by an Optically Assisted Charge...

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 11, NOVEMBER 2011 3667

An Extraction Method of the Energy Distributionof Interface Traps by an Optically Assisted

Charge Pumping TechniqueSungho Kim, Sung-Jin Choi, Dong-Il Moon, and Yang-Kyu Choi

Abstract—The energy distribution of interface traps is extractedusing an optically assisted charge pumping (optical CP) technique.Optically generated majority carriers through light illuminationenable the CP process even in a floating-body (FB) device withoutan extra body contact. With the use of square pulses at differentrising and falling times and the proposed analytical model, theenergy distribution of the interface traps is investigated via anoptical CP technique. The optical CP technique is useful to extractthe energy distribution of interface traps, as well as the interface-trap density in nanoscale FB devices. The data extracted by theoptical CP is verified in a comparison with the data extracted bysubthreshold-slope techniques.

Index Terms—Charge pumping (CP), floating-body (FB), inter-face trap, silicon-on-insulator metal–oxide–semiconductor field-effect transistor (SOI MOSFET), trap energy level.

I. INTRODUCTION

ACCOMPANYING the aggressive scaling down of field-effect transistors (FETs) into the nanoscale range, the

potential use of floating-body (FB) devices such as nanowireFETs, thin-film transistors, vertical-channel FETs, andMOSFETs built on a silicon-on-insulator (SOI) substrate hasattracted a considerable amount of attention owing to the highperformance and the structural benefits of these devices forhigh-density integration. The performance and the reliabilityof these nanoscale FB devices are considerably influenced bytheir interface states due to the increased surface-to-volumeratio by device scale-down advances. Therefore, quantitativeanalyses of the interface states of these devices such as themagnitude of trap density and the energy distribution of trapsare becoming more important. However, the commonly used

Manuscript received February 22, 2011; revised July 11, 2011; acceptedJuly 19, 2011. Date of publication August 30, 2011; date of current versionOctober 21, 2011. This paper was supported in part by the Center for NanoscaleMechatronics and Manufacturing under Grant 08K1401-00210, which is oneof the 21st Century Frontier Research Programs supported by the KoreanMinistry of Education, Science, and Technology (MEST); by the Nano R&Dprogram through the National Research Foundation of Korea funded by theMEST under Grant 2010-0018931; by the Information Technology R&Dprogram of Ministry of Knowledge Economy/Korea Evaluation Institute ofIndustrial Technology under the Terabit Nonvolatile Memory DevelopmentGrant 10029953; and by Samsung Electronics Company, Ltd. The review ofthis paper was arranged by Editor R. Huang.

The authors are with the Department of Electrical Engineering, KoreaAdvanced Institute of Science and Technology, Daejeon 305-701, Korea(e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2011.2163146

technique for the analysis of interface states, i.e., chargepumping (CP), is not directly applicable to FB devices becausea supply of majority carriers to the FB is indispensible for theCP process. Thus far, specially designed device structures thatinclude an extra body contact [1] or gated-diode-like devices[2] have been instead used for CP measurements in FB devices.In addition, the measured CP current ICP is proportional tothe channel area, which is typically too small to measure innanoscale devices. Thus, a multifin structure has been requiredto enlarge the channel area in the case of FinFETs [3].

To overcome the limitations associated with the conventionalCP, it was demonstrated that a novel optically assisted CP(optical CP) technique could quantify the interface-trap densityDit directly in FB devices [4]. In optical CP measurements, ma-jority carriers were generated by light illumination and removedvia recombination through the CP process. The consequentchange in the drain current was used to extract the interface-trapdensity with the aid of a developed analytical model. However,previous works only demonstrated the extraction procedure forthe interface-trap density without the energy distribution oftraps, and the extracted data were not verified in comparisonwith the data extracted by other trap characterization tech-niques. Thus, the confirmation of the validity of the extractionprocedure and the analytical model for the proposed optical CPprocess remains incomplete.

In this paper, in Section II, the basic principles of the opticalCP are discussed with more detailed measurement procedurescompared with those in previous research [4]. In addition, thisoptical CP technique is applied to an independent-gate FinFET(IG-FinFET) structure that has a submicrometer-dimension FBinstead of the micrometer-sized planar SOI MOSFETs. Next, inSection III, through an analysis of the measured drain current,which is a function of the rising and falling times of thepulse, the application of the optical CP is extended to extractthe energy distribution of interface traps [Dit(E)] for p- andn-channel devices. Finally, in Section IV, the data extracted viathe optical CP are verified in comparison with the data extractedby well-known subthreshold-slope techniques reported by othergroups.

II. BASIC PRINCIPLE OF THE OPTICAL CP

A. Basic Principles

An examination of the proposed optical CP technique wascarried out on a nominal FB FET composed of four terminals,

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3668 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 11, NOVEMBER 2011

Fig. 1. Cross-sectional view of the device for an explanation of the measurement setup. Three different factors (Glight, Ghole, and RCP) determine themodulation of the hole density (ΔNhole) at the front interface.

i.e., front gate G1, back gate G2, source S, and drain D, asshown in Fig. 1. During optical CP measurements in the caseof an n-channel FET, the back gate VG2 is sustained with apositive voltage so as to induce a strong inversion layer at theback interface. A small drain bias VDS monitors the resultingdrain current ID. Additionally, the front gate VG1 is biasedwith the sum of the negative dc voltage and a pulse waveformdesigned for the CP process. Under these bias conditions, Dit

at the front interface is selectively detected. In the case of ap-channel FET, the polarities of VG1 and VG2 are reversed, ascompared with that of the n-channel FET. Given that the rolesof the two gates are interchangeable, it is unambiguous that Dit

at the back interface is also measurable. Hence, it is additionallyadvantageous to analyze the Si/buried-oxide (BOX) interface ofthe SOI substrate.

Contrary to the conventional CP technique, holes are sup-plied through light illumination and then accumulate near thefront interface in the optical CP measurements. For the sakeof convenience, the following explanations are provided for then-channel FET only. Those holes contribute to enabling the CPprocess without an extra body contact. The hole density Nhole istherefore modulated by the CP process, which is monitored viatransient ID characteristics. In detail, when the light is turnedon, holes are generated at a constant rate of Glight. These op-tically generated holes accumulate at the front interface due tothe negative front-gate bias VG1 = VL. Consequently, Nhole atthe front interface is increased. However, it cannot be infinitelyincreased, i.e., its upper level is under compliance according tothe following diffusion-out process of the holes. When the num-ber of holes grows too large (= when Nhole exceeds a criticallevel), the front interface is forwardly biased with respect to then+ source/drain region. Therefore, accumulated holes diffuseto the n+ source/drain region according to the lower potentialbarriers, which determines the maximum hole capacity. As aconsequence of the capacitive coupling between the front andback interfaces in the FB, ID is increased according to the hole

Fig. 2. (a) Biasing level and timing of the applied pulse waveform (VG1), and(b) the expected ID characteristics according to the applied value of VG1.

accumulation at the front interface. This phenomenon has beenequivalently observed in a lateral bipolar photodetector on aSOI [5]. Under this situation, the pulse stream is applied to thefront gate under light illumination. If the VH (VL) value of thepulse is higher (lower) than the threshold voltage (the flat-bandvoltage), holes then recombine with trapped electrons in theinterface traps (this is known as the traditional CP process [6],[7]). Therefore, Nhole decreases due to the CP process, whichis monitored by the decrement of ID. The recombination rateby the CP process (RCP) is given as RCP = f · Dit, where fis the applied pulse frequency.

Fig. 2(a) shows the schematics of the bias condition for VG1,and Fig. 2(b) shows the expected ID characteristics accordingto the applied VG1. When light is illuminated with a negativedc bias (VG1 = VL), ID is increased from ID,dark to ID2 dueto the holes that accumulate at the front interface. Becausethe maximum hole capacity is limited by the aforementionedhole diffusion-out effect, the increment of the drain current issaturated at ID2. Subsequently, a pulse stream is applied for theCP process under continuous light illumination. When a pulse

KIM et al.: EXTRACTION METHOD OF ENERGY DISTRIBUTION OF INTERFACE TRAPS 3669

of f = f1 < fcrit is applied (fcrit is the critical frequency), ID2

does not change because the hole generation rate caused bylight illumination is still higher than the recombination rate bythe CP process (Glight > RCP). Next, when f reaches fcrit,Glight is equal to RCP (= fcrit · Dit), and the system continuesand remains in a steady state. After f exceeds fcrit (f =f3 > fcrit), R′

CP (= f3 · Dit) exceeds Glight. Consequently,the accumulated holes are recombined by the CP process,causing ID2 to decrease. However, the decrement of ID2 doesnot continuously occur and becomes saturated at ID1 becausea certain amount of hole generation Ghole occurs accordingto the sudden hole recombination caused by the CP process(ΔNhole). When a pulse of f = f3 is applied to the front gate,due to the sudden hole reduction by the CP process, more holesshould be supplied to maintain the charge balance. However, asholes cannot be promptly supplied due to the absence of a bodycontact, the system enters into a nonsteady state. Due to the sud-den hole reduction at the front interface, a shift in the electro-static potential occurs inside FB, which results in the bulk holegeneration Ghole governed by the Shockley–Read–Hall theory[8]. This nonsteady state leads to a condition in which holes aregenerated in the bulk region of the body as the system attemptsto restore the steady state. Consequently, holes generated fromthe bulk region try to make a balance with the recombinationcaused by the CP effect. The detail quantitative analysis is understudy. Accordingly, Ghole offsets the hole reduction causedby the CP process, thus allowing the decrement of ID to beobserved only within a specific time tCP. Here, tCP denotesthe time to stabilize the drain current from ID2 to ID1. Finally,after the lapse of tCP, Glight + Ghole and R′

CP enter into a newsteady state, which keeps the drain current to be constant again.Therefore, Dit can be attained by [4]

(fcrit − f3) · Dit × tCP = ΔNhole = ΔNhole2 − ΔNhole1.(1)

To calculate Dit from (1), the correlation between the decre-ment of the drain current (ΔID) according to the hole densitymodulation ΔNhole at the front interface should be analyticallymodeled. This is given as [4]

ΔNhole = ΔNhole2 − ΔNhole1

= (1 + Cox1/CSi)(Cox2/q)× (VG2 − Vth)(ΔID/ID,dark − 1) (2)

where ID,dark is the measured value of ID under a darkcondition and Vth is the threshold voltage of the back interfacein thermal equilibrium at VG1 = VL. Consequently, using (1)with the measured values of ID,dark, ΔID, and fcrit, Dit iscalculated from (2).

Here, it should be noted that the explained operation princi-ples and the derived models are developed under the assump-tion; the hole density modulation ΔNhole at the front interfacetotally resulted from the interface traps. However, when VG1 =VH , holes are expelled from the front interface. They canrecombine with the electrons in the bulk region of the body,resulting in additional ΔNhole and consequent ΔID. Therefore,

Fig. 3. Relevant information of an IG-FinFET: (a) Listed device dimensionsand process flow. (b) Schematic of the IG-FinFET and (c) cross-sectional TEMimage.

tH should be minimized to reduce this unwanted ΔNhole,which can improve the accuracy of the extracted Dit value.

B. Interface-Trap Density Extraction by the Optical CP

An IG-FinFET was used to demonstrate the optical CP asan analysis tool for the extraction of Dit. A summary of theprocess of the IG-FinFET flow and its corresponding schematicare shown in Fig. 3(a) and (b), respectively. The process flowis similar to that of the previous IG-FinFET process [9]. Asa starting material, a SOI wafer whose doping was adjustedby boron at a concentration of 1018 cm−3 was used. The finheight Hfin was fixed by the initial silicon thickness, whichwas 100 nm in the SOI used here. The BOX had a thicknessof 140 nm. As a first step, nitride with a thickness of 50 nmwas deposited onto the Si as an etch stopper [hard mask (HM)]during the subsequent chemical-mechanical polishing (CMP)process to separate the gate. The fin width Wfin ranged from 30to 150 nm. Patterning here was done using conventional opticallithography and dry etching. Afterward, tetraethyl orthosili-cate (TEOS) oxide with a thickness of 20 nm (tox) and n+

in situ doped polycrystalline silicon (poly-Si) with a thicknessof 110 nm were sequentially deposited as a gate dielectric anda gate electrode, respectively. By utilizing the CMP process,the protruding poly-Si gate was polished until its topology wasflat. Hence, the connected single gate was separated into gates1 (G1) and 2 (G2). After patterning the gate electrode, thesource and drain electrodes were formed through the use ofarsenic implantation at 30 keV of energy and a dose of 5 ×1015 cm−2. Fig. 3(c) shows a transmission electron microscope(TEM) image of the fabricated IG-FinFET. Henceforth, theG1-SiO2/Si and G2-SiO2/Si interfaces are assigned as thefront interface and back interfaces, respectively. Here, it shouldbe noted that this IG-FinFET is not a special device structure.Although the optical CP was demonstrated to analyze 20 nm ofTEOS gate dielectric in this case, the application of the opticalCP is not constrained by the thickness, the material of the gatedielectric (e.g., high-k), or the device structure. As a proof, itwas previously confirmed that the thermal oxide at 5 nm wasanalyzed using a conventional planar SOI MOSFET structureby the optical CP [4].

Fig. 4(b) shows the measured ID transient characteristicswith the aid of a semiconductor parameter analyzer (HP4155B).White light from a halogen lamp (Cascade Microtech, VMS-70Z, Fiber Optic Illuminator) was used as an illuminationsource; it was assumed that the wavelength of the light is not


Fig. 4. (a) Typical ID–VG2 characteristics with/without illumination and(b) the optical CP measurement result. (Inset) ΔID − f3 characteristic todetermine fcrit; fcrit is defined as the specific f3 value when ΔID is zero.

critical in the optical CP measurements. When light is illumi-nated with a dc bias of VG1 = −2 V, a certain amount of ID isincreased due to the holes that accumulate at the front interface.Subsequently, a pulse stream is applied for the CP processunder continuous light illumination. Until f < fcrit = 160 Hz,the hole generation rate by light (Glight) remains higher thanRCP (= fcrit · Dit); this causes ID to remain in a steady state.After f is changed from fcrit to f3 abruptly, R′

CP (= f3 · Dit)overcomes Glight. Consequently, the accumulated holes aresuddenly reduced via recombination through the CP process,causing ID to decrease as a result. Finally, Glight + Ghole

and R′CP settle into a new steady state, which makes ID

constant. fcrit is not easily determined accurately throughmeasurements. Therefore, fcrit is extracted by extrapolating theΔID − f characteristics, as shown in the inset of Fig. 4(b).Consequently, from the measured values of ΔID, fcrit, and theaforementioned developed model, the extracted value of Dit is1.02 × 1011 cm−2, which is in good agreement with the valueobtained in the Si/SiO2 (TEOS) interface reported in anotherstudy [10].

III. ENERGY DISTRIBUTION OF INTERFACE TRAPS

From the derived model for the extraction of the interface-trap density Dit in optical CP measurements, (1) can be ex-panded in the same manner derived in an earlier study [7], i.e.,

ΔNhole/ [(f3 − fcrit) · tCP] =

E2∫

E1

DitdE. (3)

Here, E2 and E1 are the nonsteady state emission levels ofthe electron and the holes, respectively. E2 and E1 are given asfollows:

E2 = Ei − kT · ln (vth · σn · ni · tf · |VFB − Vth|/|ΔVG|)E1 = Ei + kT · ln (vth · σp · ni · tr · |VFB − Vth|/|ΔVG|) .

(4)

Under the assumption that tCP and fcrit are independent ofthe rising and falling times of the pulse (tr and tf , respectively),

Fig. 5. (a) Measured ΔID values at different tr/tf values of the squarepulse. (b) Energy distribution of interface traps analyzed by the optical CPin both n- and p-channel IG-FinFETs. It is assumed here that σn = σh =1 × 10−16 cm2 [12] and vth = 1.5 × 107 cm/s [7]. (Dashed horizontal line)Dit as extracted by the optical CP method.

the differentiation of (3) with respect to tr and tf leads to

(1 + Cox1/CSi)(Cox2/q)(VG2 − Vth)(f3 − fcrit) · tCP · ID,dark

· d

dti(ΔID)

= Dit(E2)dE2

dti− Dit(E1)

dE1

dti, ti = tr or tf . (5)

The aforementioned assumption about tCP and fcrit as afunction of tr and tf were originated from the measured data;tCP and fcrit values are independent tr and tf (data are notshown). Under the condition that the falling time of the squarepulses is changed and the rising time of these values is fixed,it is necessary to scan the energy range in the upper half ofthe band gap between the conduction band and the midgap[7]. Thus, for example, when the rising time is sustained as aconstant under the condition that the falling time is changing,the result is


· d

dtf(ΔID)

= Dit(E2)dE2

dti

where E1 is independent of the falling time. According to (4),dE2/dtf = −kT/tf . Therefore, Dit(E2) can be obtained as

Dit(E2) = − tfkT


· d

dtf(ΔID). (6)

In a similar manner, Dit(E1) was determined according to

Dit(E1) = − trkT


· d

dtr(ΔID) (7)

while scanning the energy range in the lower half of the bandgap between the midgap and the valence band.

Fig. 5(a) shows the ΔID values characterized by changingtr (or tf ) of the square pulse. Using the derived equations


of (6) and (7), the energy distribution of the interface traps[Dit(E)] is extracted from ΔID, which is dependent on therising/falling time, as shown in Fig. 5(b). Fig. 5(b) shows the ex-tracted Dit(E) values from the n- and p-channel IG-FinFETs,respectively. It should be noted that the scanned energy levelrange can be enlarged by using increased values of tr, tf , andtH . Most of the traps are distributed near the conduction- andvalence-band edges in the Si/SiO2 interface [7], [11]; hence-forth, the scanned ranges focus on the near-band-edge regionsin these measurements. These extracted Dit(E) values by theoptical CP show good consistency with those obtained by thecapacitance–voltage (C–V ) technique in the Si/SiO2 (TEOS)interface [10]. Therefore, it can be concluded that the proposedoptical CP technique is valid for extracting Dit(E) values.

IV. VERIFICATION OF THE OPTICAL CP TECHNIQUE

To verify the validity of the extracted data by the opticalCP in Sections II and III, these values should be comparedwith the data extracted in a different manner by other trapcharacterization techniques. The best means of carrying outthis verification is to compare extracted data (Dit and Dit(E))directly according to both the optical and conventional CPmethods. However, an extra body contact device or a gated-diode structure is necessary to characterize an interface trapfor the conventional CP technique, which requires a specialtest structure and additional fabrication steps. In addition, oneshould pay careful attention to the geometric current componentof FB devices to avoid measurement errors in conventional CPmeasurements [13], [14]. Alternatively, trap characterizationthrough subthreshold-slope techniques [15], [16] can properlyconfirm the validity of the optical CP method because the mea-surement procedures used with these methods are simpler thanother techniques and are applicable to various types of devicesregardless of the device structure. However, it is noteworthy thatsubthreshold-slope techniques have relatively low sensitivityand are not applicable to short-channel devices showing a highlevel of parasitic leakage [17]. Neither can those techniques beaccurate in the presence of lateral trap nonuniformity [18]. Inaddition, the techniques can be affected by surface potentialfluctuations, which result in inaccurate values of the interface-trap density [19].

Nevertheless, the subthreshold-slope technique reported ina recent study [15] was adopted to verify the data of Dit inSection II for a simple comparison. This technique involvessweeping both the front- (VG1) and back-gate (VG2) voltagessimultaneously while maintaining a constant gate bias ratiok (= VG2/VG1). The subthreshold slope reached 60 mV/decat k = k0, and Dit could be calculated by referencing themeasured value of k0. This technique is available for a fullydepleted SOI MOSFET and a double-gate FET structure (thedetailed principles of the technique were described in theliterature [15]). Fig. 6(a) shows the front-channel subthresholdswing S1 as a function of k. The corresponding ID versus VG1

curves are shown in the inset. As k increases, S1 decreases toless than 60 mV/dec. This arises from the much earlier turnon of the back channel by the quicker back-gate voltage sweep.For this device, k0 = 4.3, which yields Dit of 3.6 × 1011 cm−2.

Fig. 6. (a) Front-channel subthreshold swing S1 versus the gate bias ratio kunder independent-gate operation. (Inset) Corresponding ID–VG1 characteris-tics for selected k values. (b) The extracted Dit values by both the optical CPand subthreshold-slope techniques. The data set was extracted from 20 differentdevices with the same device dimensions.

Fig. 6(b) shows the data extracted from 20 different devicesusing both the optical CP and subthreshold-slope techniques,respectively. These values show a reasonable agreement in bothtechniques; therefore, it can be concluded that the value of Dit

extracted through the optical CP is reliable and that its validityis verified.

Next, to verify the data of Dit(E) in Section III, anothersubthreshold-slope technique, as reported in [16], was adopted.This technique involves ID–VG characteristics in the sub-threshold region of operation that can be expressed as ID =ID,max(1 − exp(−qmVDS/nkT )), in which n = 1 + (Cit +Csi)/Cox and m = 1 + Csi/Cox. In addition, ID,max is themaximum drain current for the applied gate voltage. Parametern can be obtained from the transfer characteristics of logID versus VG. At a given gate bias VG, ratio m/n can beobtained from the slope of − log(1 − ID/ID,max) versus theVDS plot (the detailed principles of the technique are describedin the literature [16]). Fig. 7 shows the comparative data ofDit(E) extracted by both the optical CP and subthreshold-slopetechniques in [16]. These values are in good agreement in bothtechniques; thus, it can be concluded that the value of Dit(E)extracted by the optical CP method is also validated. Althoughthe scanned energy range of the subthreshold-slope techniqueis wider than that of the optical CP technique, traps in theupper level of the band gap are only analyzed in the case ofthe subthreshold-slope technique. On the other hand, both theupper and lower levels of the band gap are characterized by theoptical CP technique, which is a benefit in a full analysis.

V. CONCLUSION

In summary, an optical CP technique has been demonstratedto quantify the energy distribution of the interface-trap densityin nanoscale FB devices. The optical CP technique overcomesthe limitations of the conventional CP; energy distributions, as


Fig. 7. Energy distributions of the interface traps extracted by both the opticalCP and subthreshold-slope techniques. (Inset) Variation of the drain currentaccording to the drain voltage for different values of the gate voltage. Thesewere used to extract the energy distribution.

well as the density of the interface trap, have been directlyextracted without specially designed structures. An analyticalmodel has been also developed for the extractions. The dataextracted by the optical CP was verified in comparisons with thedata extracted by several subthreshold-slope techniques. Theproposed optical CP technique provides information pertain-ing to the interface states regardless of the device structure,materials, or dimensions. This would be a great benefit wheninvestigating nanoscale FB devices, which have attracted aconsiderable amount of attention related to futuristic devicetechnology.

However, it should be noted that the derived model for theoptical CP in this time has not considered short-channel effectsor any parasitic effects. This simple model may include someerrors, particularly in sub-100-nm devices. This needs furtherconsideration, including the corrected device model with com-prehensive physical analyses, which will be discussed in a laterstudy.

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Sungho Kim received the B.S. and M.S. degree fromKorea Advanced Institute of Science and Technol-ogy, Daejeon, Korea, in 2006 and 2008, respectively,where he is currently working toward the Ph.D.degree in electrical engineering in School of Elec-trical Engineering and Computer Science, Divisionof Electrical Engineering.

His research interests are in trap characterizationusing charge pumping technique.

Sung-Jin Choi received the B.S. degree in elec-tronics and electrical engineering from Chung-AngUniversity, Seoul, Korea, in 2007 and the M.S. de-gree from Korea Advanced Institute of Science andTechnology, Daejeon, Korea, in 2008, where he iscurrently working toward the Ph.D. degree in electri-cal engineering.

His research interests include Schottky-barrierdevices, capacitorless dynamic random-access mem-ory, biosensors, and nanowire electronics.


Dong-Il Moon received the B.S. degree fromKyungbook National University, Daegu, Korea, in2008. He is currently working toward the M.S.degree in the Division of Electrical Engineering,Korea Advanced Institute of Science and Technol-ogy, Daejeon, Korea.

His research interests include silicon photonicdevice and capacitor-less 1 transistor dynamicrandom-access memory ranging from devicedesign to process development, simulation, andcharacterization.

Yang-Kyu Choi received the B.S. and M.S. degreesfrom Seoul National University, Seoul, Korea, in1989 and 1991, respectively, and the Ph.D. degreefrom the University of California, Berkeley, in 2001.

From January 1991 to July 1997, he was a ProcessIntegration Engineer with Hynix Semiconductor,Inc., Kyungki, Korea, where he developed 4-, 16-,64-, and 256-M dynamic random-access memorydevices. He is currently an Associate Professorwith the Division of Electrical Engineering, Schoolof Electrical Engineering and Computer Science,

Korea Advanced Institute of Science and Technology, Daejeon, Korea. Hehas authored or coauthored over 130 papers and is the holder of sevenU.S. patents and 100 Korean patents. His research interests are multiple-gate metal–oxide–semiconductor (MOS) field-effect transistors, exploratorydevices, novel and unified memory devices, nanofabrication technologies forbioelectronics, and nanobiosensors. He has also worked on reliability physicsand quantum phenomena for nanoscale complementary MOS.

Dr. Choi was the recipient of the Sakrison Award for the Best Dissertationfrom the Department of Electrical Engineering and Computer Sciences, Uni-versity of California, in 2002. He was also the recipient of “The Scientist ofthe Month for July 2006” from the Ministry of Science and Technology inKorea. His biographic profile was published in the 57th Marquis Who’s Whoin America.

An Extraction Method of the Energy Distribution of Interface Traps by an Optically Assisted Charge...

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