An Energy-Efficient ECG Processor in 45-nm CMOS Using Statistical Error Compensation

2882 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 11, NOVEMBER 2013

An Energy-Efficient ECG Processor in 45-nm CMOSUsing Statistical Error CompensationRami A. Abdallah, Member, IEEE, and Naresh R. Shanbhag, Fellow, IEEE

Abstract—A subthreshold ECG processor in 45-nm IBM SOICMOS is designed to operate at the minimum energy operatingpoint (MEOP). Statistical error compensation (SEC) is em-ployed to further reduce energy at the MEOP. SEC isshown to reduce by 28% compared with the conventional(error-free) case while maintaining acceptable beat-detectionperformance. SEC enables the supply voltage to be scaled to15% below its critical value at MEOP, while compensating fora 58% precorrection error rate . These results represent animprovement of 19× in beat-detection performance and 600×in over conventional (error-free) systems. The prototype ICconsumes 14.5 fJ/cycle/1k-gate and exhibits 4.7× better energyefficiency than the state of the art while tolerating 16× morevoltage variations.

Index Terms—Error resiliency, robust design, statistical com-puting, subthreshold, ultralow power, voltage overscaling.

I. INTRODUCTION

S PIRALLING healthcare costs and a rapidly aging pop-ulation has led to a growing interest in personal and

preventive healthcare systems and telemedicine [1]. Cardio-vascular diseases (CVD), such as coronary heart disease,atrial fibrillation, and ventricular arrhythmia, constitute signif-icant health burdens as it accounts for 30% of all deaths [2],[3]. Real-time monitoring and analysis of electrocardiogram(ECG) is expected have a significant impact on personal andpreventive healthcare by enabling expert intervention in theearly stages of CVD [1], [4], [5]. ECG consists of periodicQRS-complexes [see Fig. 1(a) which reflect the electricalactivity in the heart during ventricular contraction. Accuratereal-time QRS detection and beat-to-beat (RR) interval [seeFig. 1(a)] extraction are the basis for heart monitoring devicesand CVD classification algorithms and are widely consideredto provide a simple noninvasive and quantitative assessment ofcardiac health and serves as an indicator for the onset of CVDs.For example, the RR-intervals across three consecutive cycleswere shown to be a simple and accurate detector for arrhythmia

Manuscript received January 24, 2013; revised July 06, 2013; acceptedAugust 01, 2013. Date of publication September 16, 2013; date of currentversion October 19, 2013. This paper was approved by Associate EditorDejan Markovic. This work was supported by the Gigascale Systems Re-search Center, one of six research centers funded under the Focus CenterResearch Program (FCRP), a Semiconductor Research Corporation entity.R. A. Abdallah is with the Visual and Parallel Computing Group, Intel Cor-

poration, Hillsboro, OR 97124 USA (e-mail: [email protected]).N. R. Shanbhag is with the Coordinated Science Laboratory and the

Electrical and Computer Engineering Department, University of Illinois atUrbana-Champaign, Urbana, IL 61801 USA (e-mail: [email protected]).Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/JSSC.2013.2280055

[5]. Several techniques have been proposed for RR-intervalextraction such as derivative-based algorithms, filter banks,wavelet transforms, neural networks, and genetic algorithms,and others (see [6] and [7] for a comprehensive coverage of thedifferent algorithms). This paper implements the Pan–Tomp-kins algorithm (PTA) [8], which is a derivative-based algorithmwidely used in ECG processing systems as it does not requireextensive computation, manual segmentation of data, trainingphase, or patient-specific modifications and provides gooddetection accuracy compared with other algorithms [4], [9].Recently, several wearable/implantable devices and SoCs

[10]–[20] have been reported, which monitor and process vitalphysiological signals such as ECG, electroencephalography(EEG), electromyography (EMG), and electrooculography(EOG). An important requirement for wearable and im-plantable biomedical devices is ultralow-energy operation.Lowered energy consumption results in extended battery life-time and a smaller form factor for wearability.Since vital biomedical signal bandwidths are less than

1 MHz, energy-efficient health-monitoring systems operateat or near the minimum achievable energy operating point(MEOP), which is a well-studied topic [21]–[24]. MEOP typi-cally occurs in the subthreshold regime and, hence, is subject toincreased variability (e.g., process, voltage, and temperature).However, MEOP operation has so far been studied withoutexploiting the energy efficiency and robustness benefits oferror resiliency. The use of error resiliency allows digitalcircuits to be operated in voltage and frequency regimes wheretiming errors are allowed to occur and then compensated forwith sufficiently low overhead, thereby achieving both en-hanced robustness and energy savings over error-free operatingconditions. Error resiliency can be introduced either throughstatistical error compensation (SEC) techniques [25], [26],where errors are compensated for by exploiting the knowledgeof error statistics, or through microarchitectural techniques[27]–[29] that employ deterministic local error-detection andglobal error-correction via architectural replay. Deterministicmicroarchitectural error correction [27]–[29] achieves energyefficiencies of up to 15% beyond the point-of-first-failure(PoFF) in superthreshold regime, while correcting for an errorrate of less than 0.1%, where is defined as the percentageof clock cycles in which the output is in error. For example,RAZOR [27] (RAZOR II [28]) operates at an error rate of

while achieving an energy savings of15% (5%). Error detection sequential (EDS) [29] and tunablereplica circuit (TRC) achieve 7% energy reduction over PoFFoperation. In contrast, SEC is able to compensate for error ratesof up to 86% and demonstrated 3.3 to 5.8 reduction in

0018-9200 © 2013 IEEE

ABDALLAH AND SHANBHAG: ENERGY-EFFICIENT ECG PROCESSOR IN 45-nm CMOS USING STATISTICAL ERROR COMPENSATION 2883

Fig. 1. ECG processing: (a) input (noisy) ECG [36], (b) filtered ECG, (c) ECG at derivative output, and (d) ECG at moving average output.

energy for high-speed FIR filters [25] and PN-code acquisitionfilters [26]. One drawback of SEC techniques is that theseare application-specific and rely on application-level aware-ness, e.g., the knowledge of application-level metrics such assignal-to-noise ratio (SNR) or probability of detection .Past work in the use of error compensation [25]–[29] has

been done in the superthreshold regime only. Subthresholdregime is characterized by a higher sensitivity to process,voltage, and temperature variations than the superthresholdregime. In addition, leakage energy becomes comparable todynamic energy. Thus, error-resilient designs in subthresholdneed to explore the entire -plane in order to identifythose coordinates at which the error rate is within the upperbound imposed by the error compensation technique and thenchoose the one where energy is minimized. This is unlike thesuperthreshold regime, where the supply voltage is reducedmonotonically until the error rate hits the aforementionedupper bound. This paper demonstrates that , i.e., energyconsumption at the MEOP in subthreshold, can be reducedand robustness enhanced via the use of SEC. These resultsare demonstrated by the application of SEC to design an en-ergy-efficient ECG processing core for RR-interval extractionin a 45-nm CMOS process. In [30], we presented theoreticalanalysis and simulation results of a MAC unit in 130 nm thatillustrates the benefits of SEC in reducing . In [31], wepresented preliminary measurement results from the ECG

processor IC designed in a 45-nm process node. This paperexpands upon [31] by providing the theoretical background,architectural details, and additional measurement results.This paper is organized as follows. Section II presents a brief

background on PTA for ECG processing and SEC. Section IIIdescribes the architecture and implementation details of theECG processor. Section IV presents measurement results illus-trating the benefit of SEC in terms of robustness and energyefficiency in subthreshold, and Section V concludes.

II. BACKGROUND

Here, we present background on PTA and SEC for robust andenergy-efficient system design.

A. Pan–Tompkins Algorithm

The PTA is the most widely used algorithm for QRS de-tection. It consists of noise-removal filters, a derivative andsquaring stage, a moving average, and a peak detector (seeFig. 2). The raw ECG signal [see Fig. 1(a)] is corrupted byvarious noise artifacts such as 60-Hz noise, muscle noise, mo-tion artifact, and skin interface [32]. PTA employs a bandpassfilter as a first step to maximize the QRS SNR in the QRSfrequency band of interest which is 5 to 15 Hz. The bandpassfilter is implemented using a cascade of a low-pass filter (LPF)with a cutoff frequency of 15 Hz and a high-pass filter (HPF)with a cutoff frequency of 5 Hz. The filtered ECG signal is


Fig. 2. Block diagram of PTA for ECG processing.

Fig. 3. ANT. (a) Framework. (b) Error distributions.

then differentiated in order to amplify the higher frequenciesof ECG wave (QRS-complex) while attenuating the lowerfrequencies [P- and T-waves in Fig. 1(b)]. Squaring is thenapplied to intensify the higher frequencies. The squared signal

is then passed through a moving window integrator toprovide information about the QRS-complex width. The finalstage in PTA is an adaptive detector which exploits informationabout the QRS amplitude, slope, and width, as well as physio-logical properties of ECG in order to determine the locationsof the R-waves. Thus, the final output is a pulse trainwhere each pulse indicates a location of an R-wave. IrregularRR-intervals can then signal the onset of a CVD [4], [5].

B. Statistical Error Compensation: AlgorithmicNoise-Tolerance (ANT)

Statistical error compensation in the form of ANT [33] inFig. 3(a) incorporates a main block and an estimator. The mainblock is permitted to make errors, but not the estimator. Theestimator is a low-complexity block (typically 5%–20% of themain block complexity) generating a statistical estimate of thecorrect main block output, i.e.,

(1)

(2)

where is the actual main block output, is the error-freemain block output, is the hardware error, is the estimatoroutput, and is the estimation error. Note that the estimator hasestimation error because it is simpler than the main block.ANT exploits the difference in the statistics of and [seeFig. 3(b)]. To enhance robustness, it is necessary, when ,that be large compared with . In addition, the probability ofthe event must be small. The final/corrected output of anANT system is obtained via the following decision rule:

ifotherwise

(3)

where is an application-dependent parameter chosen to max-imize the performance of ANT. Under the conditions outlinedabove, it is possible to show that

(4)

where , and are the SNRs ofthe uncorrected main block ( dominates), the estimator (dominates), the ANT system, and the error-free main block(ideal), respectively. Thus, ANT detects and corrects errorsapproximately, but does so in a manner that satisfies an applica-tion-level performance specification (SNR). The ANT decisionblock is designed to be timing error-free at all process cornersand reduced voltages as it is a critical block that directly impactsperformance and typically constitutes less than 5% ofthe main block complexity. Several low-overhead estimationtechniques have been proposed by exploiting data correlation,system architecture, and statistical signal processing techniques[34].

C. Subthreshold Energy Reduction via ANT

Ultralow-power applications with low-throughput re-quirements typically operate in the subthreshold regime at theirMEOP, which is characterized by the tuplewhere and are the critical supply voltage and fre-quency of operation resulting in the minimum system energy

. The energy consumption in both subthreshold and su-perthreshold is described by

(5)

where is the dynamic energy, is the leakage energy,is the switching activity factor, is the average load capac-

itance, is the operating frequency, is the supply voltage,


Fig. 4. Architecture of ANT-based ECG processor.

and is the OFF-state average leakage current. For ANTto provide energy efficiency, it is necessary that the errors inthe main block ( : a function of voltage and frequency)arise primarily from efforts to improve energy efficiency. Givena maximum error rate which the system can tolerate,error resilient designs need to find first the set of pairs:

, i.e., iso- contours,and then determine the operating pointwhere the total energy is minimized. In subthreshold designs,dynamic and leakage components of energy are comparableespecially at the MEOP. Thus, energy is minimized in sub-threshold error resilient designs by simultaneously employingvoltage overscaling (VOS) and frequency overscaling (FOS).In VOS, the supply voltage is reduced below the critical voltage

needed for error-free operation while keeping the oper-ating frequency fixed at . In FOS, is kept fixedwhile is increased beyond . In contrast, our past workin superthreshold designs [34] assumed a specified throughput(fixed ). This constraint, combined with the fact that dynamicenergy dominates in superthreshold, implies that energy in su-perthreshold is minimized at the lowest voltage at which theerror rate constraint is met. Thus, unlike subthreshold regime,the supply voltage and hence VOS is the only effective designvariable in fixed-throughput error-resilient superthreshold de-signs. Note that, as most arithmetic computations are least-sig-nificant-bit (LSB) first, timing violations due to VOS or FOSare generally large magnitude most-significant-bit (MSB) er-rors. Thus, timing violations due to VOS or FOS satisfy theerror distribution shown in Fig. 3(b). Next, we describe the de-sign and implementation of the subthreshold ANT-based ECGprocessing chip employing PTA.

III. ECG PROCESSOR ARCHITECTURE AND IMPLEMENTATION

ANT is employed to provide robustness and reduce energyof the designed ECG processor. Here, we describe the design ofthe prototype IC architecture and the choice of precisions.

A. ECG Processor IC Architecture

The chip architecture is shown in Fig. 4. The main processor(M) consists of low-pass (LPF) and high-pass (HPF) filters,a derivative and squaring blocks (DS), and a moving averageblock (MA). The main block operates on 11-b input ECG signal.A reduced precision redundancy is employed as estimator. Thereduced precision estimator (RPE) has the same architectureand operates at the same supply voltage as the main block, butoperates on the 4-b MSB of the input instead of 11 b, i.e., theRPE block is identical to the M block except for its precision.Thus, the RPE has more timing slack than the M block. Thisenables the RPE block to operate error-free even when the Mblock is in error. Input precision selection for the M and RPEblocks will be further discussed in Section III-B. The ANT-de-cision block in Fig. 4 employs the principle of statistical detec-tion explained in Section II-B in order to compute the correctedoutput. The PTA peak detector, similar to ANT-decision block,presents a challenge for statistical error compensation since itis nonlinear with one-bit output, which makes it difficult to de-sign a low-complexity estimator. Thus, the PTA peak detectoris designed to operate error-free with sufficient timing slack tohandle VOS or FOS. The estimator and the ANT-decision blockgate complexity constitutes 32% of the main ECG processorcomplexity.The M and RPE blocks employ a reconfigurable data-path

where pipelining latches (D) can be introduced at the output of


Fig. 5. Architecture of building blocks in PTA: (a) LPF, (b) HPF, (c) derivative-square (DS) block, and (d) moving average (MA) block. The precision shown isfor the M-block and the notation represents integer-bit and fractional-bit.

TABLE ITRANSFER FUNCTION OF BUILDING BLOCKS IN PTA

different blocks. Doing so enable one to control the locationswhere VOS or FOS errors appear. The filter coefficients are de-signed to be power of 2 to reduce complexity [8]. The transferfunctions of basic blocks and the corresponding architecturesare shown in Table I and Fig. 5, respectively. The LPF and HPFare designed using pole-zero cancellation on the unit circle inorder to have integer coefficients. The derivative is a five-pointderivative which approximates an ideal derivative up to 30 Hz.The moving average window size is 32 samples to accommo-date the largest QRS-complex width (160 ms) at a sample rateof 200 samples/s. The moving average block [see Fig. 5(c)] isdesigned using Wallace-tree carry-save adders. For the rest ofthe blocks in the ECG processor, the basic computation struc-ture employs ripple carry adders and array multipliers.

B. Detection Accuracy and Precision

The metrics commonly employed for evaluating QRS de-tection performance are: 1) the sensitivity (probability ofdetecting a true QRS-complex given that it exists) and 2) thepositive predictivity (fraction of detected QRS-complexeswhich are true) [35], defined as follows:

where , and are the number of true-positive,false-negative, and false-positive events, respectively. Prob-ability values greater than or equal to 0.95 for andare desirable [35]. Using fixed-point C simulations, Fig. 6(a)shows that an 11-b input to the main M is required to achievea detection accuracy greater than 0.95 for and . Thisrelatively high precision is necessary due to the low-complexityprocessing done by PTA and agrees with other implementa-tions reported in literature [11], [10]. The input precision tothe RPE is selected such that the system can tolerate at leasta 50% pre-correction error rate while having andgreater than or equal the desirable threshold of 0.95. Em-ploying back-annotated gate-level simulations, FOS is used tointroduce an error-rate of 50% at the output of the M-blockwhile varying the RPE input precision and measuring thedetection accuracy at the output of the overall ANT system.The results are illustrated in Fig. 6(b) where it is shown thatat least a 4-b RPE input precision is required to achieve thedesired 0.95 accuracy detection threshold while tolerating a50% pre-correction error rate. The estimator design plays animportant role in determining the energy efficiency of ANT.The estimator should simultaneously have low complexity andprovide a reasonably good estimate of the correct output. Thereare a number of approaches to design such an estimator [34],including the use of a reduced precision estimator, as donein this work. The existence of such an estimator requires theapplication to exhibit the following properties: 1) the systemperformance metric is statistical in nature and 2) the input SNRis sufficiently low to mask the increase in the quantization noisedue to precision reduction, thereby providing more room forexploring reduced precision estimators. Fig. 6(a) shows thatthe ECG application satisfies this requirement as: 1) it employsdetection probability as a metric of performance and 2) a 4-bRPE achieves around 80% detection accuracy while 11-b isneeded to obtain greater than 95% accuracy. Other estimationtechniques [34] could have been explored had this not been thecase.


Fig. 6. Architectural precision selection. (a) Detection performance versus main-block input precision via fixed-point C simulations under error-free conditions.(b) Detection performance at 50% pre-correction error rate versus RPE input precision via back-annotated gate-level simulations (M-block input precision isfixed at 11 b).

Fig. 7. ECG processor prototype IC in 45-nm IBM SOI CMOS. (a) Die photograph. (b) Layout.

C. Circuit Implementation

The chip is implemented in a regular , 1-V 45-nm IBMSOI CMOS process employing an ARM standard-cell library.The usage of library cells is restricted to minimum strength cellsto reduce energy and introduce timing slack between MSB andLSB parts and thus enable a graceful increase in error rate atthe output ofM in the presence of VOS and FOS. A total of 12power domains were implemented in order to enable fine-graincontrol of error locations if needed and an accurate power mea-surement. The power domains are spread across each of the fol-lowing six modules: 1) M-block filters and DS; 2) RPE-blockfilters and DS; 3)M-block DS; 4) RPE-blockMA; 5) ANT-de-cision block; and 6) PTA peak detector. Furthermore, separatepower domains are provided for the combinational and sequen-

tial logic within each of the six modules in order to prevent thefailure of sequential logic at very low voltages. In this paper,all of the different power domains, including those of the RPE,were operated at the same supply voltage. The extra flexibilityfor controlling the error locations was not needed.The final design has a total of 36 K NAND2 equiva-

lent gates and a total chip area including the pad frameof 1.25 mm 1.3 mm. The core area is approximately0.7 mm 0.7 mm. The chip layout and microphotograph isshown in Fig. 7.

IV. IC MEASUREMENT RESULTS

The chip testing was done using two different workloads tostudy the impact of switching activity factor: 1) ECG dataset


Fig. 8. Measured energy and frequency of the conventional (error-free) ECGprocessor under different workloads.

(average switching activity ) consisting of 30-minECG recording of ten patients from the MIT-BIH arrhythmiadatabase [36] and 2) a synthetic dataset (average switching

). The MIT-BIH database provides 11-bquantized ECG waveform samples at a sampling frequencyof 200 Hz. These samples were employed as inputs to theECG processor chip. However, given a critical supply voltage

, the chip is operated at the corresponding criticalfrequency which, in our case, is greater than 65 kHz andthe samples are fed depending on . In order to match theECG sampling frequency to the IC operating frequency inreal-time ECG monitoring, the IC would have to be designedusing higher threshold devices and/or multiple ECG signalscan be processed simultaneously. For example, modern ECGmonitoring systems use 12- and 16-lead ECG sensors insteadof three leads [1].Fig. 8 shows the measured energy for the conventional

(error-free without error compensation) system and the cor-responding as a function of supply voltage. Measuredresults indicate that the error-free MEOPis (0.4 V, 600 kHz, 0.72 pJ) and (0.3 V, 65 kHz, 4.1 pJ)for the ECG and synthetic datasets, respectively. The lower

for the synthetic dataset is expected since a higherswitching-activity factor causes dynamic energy to be moredominant than leakage energy, and, thus, equilibrium is reachedat a lower supply voltage. In addition, the higher switchingactivity excites more processing nodes on critical timing paths.This results in a slightly lower frequency of operation forthe synthetic workload compared with the ECG workload, asshown in Fig. 8. Next, we study the timing-error behavior atMEOP and illustrate the robustness benefits and energy savingsachieved by the ANT-based ECG processor.

A. Timing Errors and Statistics at MEOP

Hardware/timing errors can be introduced by either VOS( , where is the VOS factor),

Fig. 9. Measured pre-correction error rate of ECG processor under voltageoverscaling and frequency overscaling.

FOS ( , where is the FOS factor),or a combination of both to reduce energy. These two designknobs (voltage and frequency) affect the appearance of timingerrors differently. Under FOS, the critical paths are not allowedenough time to complete. However, the timing of processingnodes on the critical paths does not change. Thus, the number offailing path depends on the processor architecture parametersand is independent of the voltage operating region. Under VOS,the timing of processing nodes increase, and this increase sig-nificantly depends on the voltage operating point. To illustratethe difference between FOS and VOS at MEOP, the pre-cor-rection error rate which is the probability that the main ECGprocessor output (without error compensation) is in error, dueto VOS or FOS at the output ofM-block is shown in Fig. 9 forthe ECG and synthetic datasets. The pre-correction error rateincreases rapidly for VOS as compared to FOS. This is due

to the exponential dependence of delay on in subthresholdregime, and its linear dependence on . Note that the syntheticdataset has higher than the ECG dataset since more criticalpaths are being excited with higher switching activity.An important factor to consider in SEC techniques is error

statistics (the probability distribution of the output timing error).Advanced SEC [34] techniques explicitly exploit error statisticsto improve system robustness by using probabilistic-based deci-sion rules. These advanced SEC techniques have been verifiedusing back-annotated gate-level simulations. Although in cur-rent design the error statistics are not explicitly used, we showthe correlation between error statistics obtained via the back-an-notated gate-level simulations and the actual error statistics col-lected from the prototype IC. This verifies the applicability ofprobabilistic SEC techniques and depicts more confidence intheir achieved robustness and energy benefits. To achieve this,we collected error statistics from the prototype IC at the outputof the M-block MA and compared with those obtained fromback-annotated gate-level simulations. Error statistics were ob-tained for bothVOS and FOS scenarios. As shown in Fig. 10, thestatistics obtained via measurements correlates well with thosevia simulations.


Fig. 10. ECG processor error statistics at the output of the M-block MA: (a) measured under VOS at MEOP with , (b) back-annotated gate-levelsimulation at , (c) measured under FOS at MEOP with , and (d) back-annotated gate-level simulation at .

B. ECG Detection Accuracy and Robustness

While the distinction between VOS and FOS is important todetermine the energy consumption at a given error rate, simula-tions show that the system performance metric depends on theerror rate rather than the source of error (VOS, FOS, or a combi-nation of both). That is why in Fig. 11, we show the system-levelimpact of timing errors on the QRS detection metrics and

as a function of error rate irrespective of the source of error.Probability values greater than or equal to 0.95 are desirablefor and [35]. Here, the pre-correction error rates inFig. 11 are induced by applying VOS and FOS to the ECG pro-cessor starting from its MEOP of (0.4 V, 600 kHz, 0.72 pJ)when processing the ECG dataset. The MA block is kept errorfree as it acts as a low-pass filter averaging out large-magnitudeerrors. Error-free operation in the MA block is ensured by in-troducing pipelining latches at the outputs of the DS and MAblocks, and not voltage overscaling the MA block. Error com-pensation, however, is done at the output of theMA block. Theconventional design detection performance drops significantlystarting at a very small . This can be attributed mainly to therecursive nature of the filter and peak detector blocks in PTA. Ifan error is uncorrected, it is registered in the system and requiresa couple of cycles to minimize its effect. The ANT-based ECGprocessor achieves the desired level of detection accuracy (

Fig. 11. Measured QRS detection performance at different error rates in con-ventional and the ANT-based ECG processor.

and ) in the presence of a large pre-correction errorrate . This corresponds to a greater -handlingcapability, and a improvement in and comparedwith conventional error-free designs in Fig. 11.The functional resiliency to timing errors can also be demon-

strated through the reported RR-intervals (the measured heart


Fig. 12. Distribution of instantaneous RR-interval measurement at MEOP.(a) Conventional ECG processor. (b) ANT-based ECG processor.

rate) from the conventional and the ANT-based processorsunder timing errors. The RR-interval distribution when pro-cessing the ECG dataset is shown in Fig. 12 under differentat MEOP with an error-free MA (similar measurement settingsto Fig. 11). Conventional processor maintains a reasonableRR-interval (1.2 s) for only very low after whicha large spread is observed in the RR-interval distribution. Onthe other hand, the ANT processor maintains a reasonableRR-interval up to . All of this clearly illustrates theerror resiliency of SEC which allows the system to maintainacceptable beat detection performance in presence of up to58% pre-correction error rate.The increased resiliency to timing errors also demonstrate

the robustness of the ECG processor to voltage variations.Fig. 13 shows the sensitivity ofand to voltage variations underthe ECG dataset. The sensitivity was characterized at theconventional MEOP supply voltage ( V) and

Fig. 13. Measured sensitivity and robustness of conventional and the ANT-based ECG processors to voltage variations at the conventional MEOP (0.4 V,600 kHz) for the ECG dataset.

voltage variations were induced by VOS the ECG processor. The ANT-based processor

tolerates up to higher voltage variations, and shows upto lower metric sensitivity ( and ) compared tothe conventional processor at the MEOP.

C. Voltage–Frequency Versus Error-Rate Characterizationand Energy Savings

Applying both VOS and FOS, the IC was characterized interms of its pre-correction error rate and energy consump-tion as a function of the supply voltage and frequency forthe ECG and the synthetic datasets. Fig. 14 shows the measurediso- contours in the plane. We refer to the ANT-basedECG processor operating on the contour in Fig. 14without error-compensation overhead as the conventional pro-cessor. Vertical translation (fixed ) in the plane fromthe contour corresponds to an application of FOS only.Similarly, a horizontal translation (fixed ) in the planefrom the contour corresponds to an application of VOSonly. Arbitrary translations correspond to a joint application ofVOS and FOS. The total energy consumption per iso- con-tour (including the energy overhead of error compensation for

) is shown in Fig. 15. The new MEOP of the ANT-basedprocessor at is (0.34 V, 630 kHz, 0.52 pJ) for theECG dataset and (0.26 V, 80 kHz, 3 pJ) for the synthetic dataset.Compared to the conventionalMEOP of the ECG dataset (0.4 V,600 kHz, 0.72 pJ), the new MEOP corresponds to a simulta-neous 15% reduction in , 5% increase in

, and a 28% reduction in . For the con-ventional MEOP of the synthetic dataset (0.3 V, 65 kHz, 4.1 pJ),the new MEOP corresponds to a simultaneous 13% reductionin , a 23% increase in

, and a 27% reduction in . Note that FOS plays a moreimportant role in reducing energy at the MEOP of the syntheticdataset as compared with the ECG dataset since the error-free

of the synthetic dataset is lower than that of the ECGdataset, i.e., leakage energy is more dominant at the synthetic


Fig. 14. Iso- contours operating points for (a) the ECG dataset and(b) the synthetic dataset.

dataset MEOP. At the new MEOPs, the RPE block energy con-stitutes 18% and 21% of the total ANT-based processor energyfor the ECG dataset and the synthetic dataset, respectively.Alternative to comparing MEOPs, Fig. 8 shows that the

conventional processor under the ECG (synthetic) datasetat 0.34 V (0.26 V) operates at 250 kHz(0.35 kHz) and consumes 0.9 pJ (4.8 pJ), respectively. Thuscomparing at the same , the ANT-based processor at itsnew 0.58 MEOP for the ECG (synthetic) dataset inFig. 15 can be viewed as being frequency overscaled with afactor of , i.e.,there is increase in throughput, along with 42%(38%) energy savings. Note that, as reduces in Fig. 15,the energy savings due to FOS (comparing conventional andANT-based design at the same ) increase since leakagestarts to increase.

Fig. 15. Measured energy of conventional ECG processor and ANT-based ( and including error-compensation overhead) ECG processor fordifferent workloads.

D. Comparison With the State of the Art

Reported implementations of PTA in literature [10], [11] havebeen carried out in the superthreshold regime, which makes itdifficult to compare with our design. Table II compares our de-sign to other subthreshold biomedical processors bynormalizing the energy to gates. We note here that thesebiomedical processors are based on general-purpose processorsand thus provide additional functionality when compared withour work, which is optimized for QRS extraction. The ANT-based ECG processor consumes 14.5 fJ/cycle/1k-gate which isat least more energy-efficient than the state of the art. Twomain factors contribute to this energy enhancement.1) Technology scaling from 90 to 45 nm provides an improve-ment factor of in [37]. In minimum energy de-signs, the improvement in due to technology scalingis proportional to , where is the load capacitanceand is the subthreshold swing, and the energy improve-ment is independent of the supply voltage [37].

2) The use of SOI versus bulk CMOS in 45 nm provides anadditional improvement in due to the reductionin capacitance and leakage [38].

Comparing with other error-resilient designs in su-perthreshold, the ANT-based ECG processor tolerates anerror rate of up to 58%, which is at least greater thanexisting techniques in Table II. Therefore, we see that SECprovides tremendous increase in robustness while meeting thethreshold of acceptable detection performance.

V. CONCLUSION

We have presented a statistical error-compensation-basedECG processor in 45-nm CMOS. The prototype IC illustratesthe robustness and energy benefits of statistical error compen-sation in the subthreshold region, where robustness is more ofa concern due to increased sensitivity to voltage, process, andtemperature variation. SEC in subthreshold shows robust


TABLE IICOMPARISON WITH STATE-OF-THE-ART SYSTEMS

operation up to 58% error rate along with a 28% energy re-duction beyond the absolute minimum energy. Compared withconventional systems, this represents a improvementin handling capability. In addition, SEC can tolerate upto higher voltage variations and shows up to lowermetric sensitivity in minimum energy designs. Therefore,SEC achieves both enhanced robustness and energy savingsin minimum energy designs by allowing operation in over-scaled voltage and frequency regimes despite the increasedsubthreshold sensitivity to variations.Future work can be directed towards studying the robustness

of ANT and other SEC techniques in the subthreshold regimefor various emerging applications and in both CMOS and be-yond CMOS technologies.

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Rami A. Abdallah (M’06) received the B.Eng. de-gree (with the highest distinction) from the Amer-ican University of Beirut, Beirut, Lebanon, in 2006,and the M.S. and Ph.D. degrees from the Universityof Illinois at Urbana-Champaign, Urbana, IL, USA,in 2008 and 2012, respectively, all in electrical andcomputer engineering.Since June 2012, he has been with the Visual and

Parallel Computing Group, Intel Corporation, Hills-boro, OR, USA, as a Silicon Architecture Engineerworking on the design of many-integrated core chips.

From 2006 to 2012, he was a Research Assistant with the Coordinated ScienceLaboratory. During the summers of 2007, 2008, and 2009, he was with TexasInstruments, Inc., Dallas, with the Applications and Systems R&D Labs, wherehe was involved with the design of communication receivers for 4G systems andon-chip dc–dc conversion for ultralow-power medical platforms. His researchinterests are in the design of integrated circuits and systems for communica-tions, digital signal processing, and general-purpose computing.Dr. Abdallah was the recipient of the 2012 Low Power Design Contest Award

at the International Symposium for Low Power Electronics and Design and the2011 Best-in-Session Award at the Semiconductor Research Corporation (SRC)TECHCON conference. At the University of Illinois, he was the recipient ofthe Mac Van Valkenburg Outstanding Researcher Award, the Yi-Min Wang andPi-Yu Chung Research Award in 2012, and the HKN Honor Society Scholar-ship in 2009. At the American University of Beirut, he was the recipient of theCharli S. Korban Outstanding Undergraduate Award in 2006 and was on theDean’s honor list from 2002 to 2006. In 2001, he was selected among World’stop students to participate in the Research Science Institute at the MassachusettsInstitute of Technology.

Naresh R. Shanbhag (F’06) received the B.Tech.degree from the Indian Institute of Technology,New Delhi, India, in 1988, the M.S. degree fromthe Wright State University, Dayton, OH, USA, in1990, and the Ph.D. degree from the University ofMinnesota, Minneapolis, MN, USA, in 1993, all inelectrical engineering.From 1993 to 1995, he was with AT&T Bell

Laboratories, Murray Hill, NJ, USA, where hewas the Lead Chip Architect for AT&T’s 51.84Mb/s transceiver chips over twisted-pair wiring

for asynchronous transfer mode (ATM)-LAN and very high-speed digitalsubscriber line (VDSL) chip-sets. Since August 1995, he has been with theDepartment of Electrical and Computer Engineering and the CoordinatedScience Laboratory, University of Illinois at Urbana-Champaign, Urbana,IL, USA, where he is presently a Jack Kilby Professor of Electrical andComputer Engineering. He was on a sabbatical leave of absence at the NationalTaiwan University in the fall of 2007. He has authored or coauthored morethan 200 publications and holds 12 U.S. patents. He is also a coauthor of theresearch monograph Pipelined Adaptive Digital Filters (Kluwer Academic,1994). In 2000, he cofounded and served as the Chief Technology Officer ofIntersymbol Communications Inc., a venture-funded fabless semiconductorstart-up that provides DSP-enhanced mixed-signal ICs for electronic dispersioncompensation of OC-192 optical links. In 2007, Intersymbol CommunicationsInc., was acquired by Finisar Corporation Inc. His research interests are inthe design of robust and energy-efficient integrated circuits and systems forcommunications including VLSI architectures for error-control coding, andequalization, noise-tolerant integrated circuit design, error-resilient architec-tures and systems, and system-assisted mixed-signal design.Dr. Shanbhag was the recipient of the 2010 Richard Newton GSRC Industrial

Impact Award, the 2006 IEEE JOURNAL OF SOLID-STATE CIRCUITS Best PaperAward, the 2001 IEEE TRANSACTIONS ON VERY LARGE-SCALE INTEGRATION(VLSI) SYSTEMS Best Paper Award, the 1999 IEEE Leon K. Kirchmayer BestPaper Award, the 1999 Xerox Faculty Award, the Distinguished Lectureshipfrom the IEEE Circuits and Systems Society (CASS) in 1997, the NationalScience Foundation CAREER Award in 1996, and the 1994 Darlington BestPaper Award from the IEEE CASS. He served as an associate editor forthe IEEE TRANSACTION ON CIRCUITS AND SYSTEMS—PART II: EXPRESSBRIEFS (1997–1999) and the IEEE TRANSACTIONS ON VERY LARGE-SCALEINTEGRATION (VLSI) SYSTEMS (1999–2002 and 2009–2011), respectively.He is the General Cochair of the 2012 IEEE International Symposium onLow-Power Design (ISLPED), was the Technical Program Cochair of the2010 ISLPED, and served on the technical program (wireline subcommittee)committee of the International Solid-State Circuits Conference (ISSCC) from2007 to 2011. He lead the Alternative Computational Models in the Post-SiEra research theme, in the DOD and Semiconductor Research Corporation(SRC) sponsored Microelectronics Advanced Research Corporation (MARCO)center under their Focus Center Research Program (FCRP) from 2006–12.Since January 2013, he has been the founding Director of the Systems OnNanoscale Information fabriCs (SONIC) Center, a five-year multi-universitycenter funded by DARPA and SRC under the STARnet phase of FCRP.

An Energy-Efficient ECG Processor in 45-nm CMOS Using Statistical Error Compensation

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