An Automatic AMBA Wrapper Generation Tool for Embedded Cores Laboratory for Reliable Computing...
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Transcript of An Automatic AMBA Wrapper Generation Tool for Embedded Cores Laboratory for Reliable Computing...
An Automatic AMBA Wrapper An Automatic AMBA Wrapper Generation Tool for Generation Tool for
Embedded CoresEmbedded Cores
Laboratory for Reliable Computing (LaRC)
Electrical Engineering Department
National Tsing Hua University
Laboratory for Reliable Computing (LaRC)May-2004
Ming-Shen Liu & Cheng-Wen Wu 2
OutlineOutlineOutlineOutline
Introduction
Template and Configuration
Verification and Simulation Result
Conclusion
Laboratory for Reliable Computing (LaRC)May-2004
Ming-Shen Liu & Cheng-Wen Wu 3
OutlineOutlineOutlineOutline
Introduction AMBA System AMBA Wrapper Generation Tool
Template and Configuration
Verification and Simulation Result
Conclusion
Laboratory for Reliable Computing (LaRC)May-2004
Ming-Shen Liu & Cheng-Wen Wu 4
AMBA SystemAMBA SystemAMBA SystemAMBA System Advanced Microcontroller Bus Architecture
Distinct Buses Defined within AMBA Advanced High-performance Bus (AHB) Advanced System Bus (ASB) Advanced Peripheral Bus (APB)
Laboratory for Reliable Computing (LaRC)May-2004
Ming-Shen Liu & Cheng-Wen Wu 5
AMBA SystemAMBA SystemAMBA SystemAMBA System
AR MProcessor
O n-C hipR AM
ExternalM em ory Interface
D M ABus M aster Bridge
U AR T PIO Keypad T im er
AH B or ASB Bus
APB Bus
APB Bridge
Laboratory for Reliable Computing (LaRC)May-2004
Ming-Shen Liu & Cheng-Wen Wu 6
AHB Model DiagramAHB Model DiagramAHB Model DiagramAHB Model Diagram
Master 1 Master 2
Slave A Slave B
AHB
Arbiter
DecoderDSELA DSELB
AGNT1
AREQ2AREQ1
AGNT2
Laboratory for Reliable Computing (LaRC)May-2004
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AHB Multiplexer SchemeAHB Multiplexer SchemeAHB Multiplexer SchemeAHB Multiplexer Scheme
Arbiter
Master #1
Master #2
Slave #1
Slave #2
Slave #3
ADDR
ADDR
ADDR
ADDR
ADDRW DATA
W DATA
W DATA
W DATA
W DATA
RDATA
RDATA
RDATA
RDATA
RDATA
Decoder
Address andC ontro l M ux
W rite D ata M ux
R ead D ata M ux
Address Bus In terconnection
D ata Bus In terconnection
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AHB Basic Transfer CyclesAHB Basic Transfer CyclesAHB Basic Transfer CyclesAHB Basic Transfer Cycles
Simple Transfer Transfer With Wait SatesHCLK
Address Phase Data Phase Address Phase Data Phase
HADDR[31:0] A A
Control Control Control
HWDATA[31:0] Data A Data A
HREADY
HRDATA[31:0]Data A Data A
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Overview of AHB Wrapper Generation ToolOverview of AHB Wrapper Generation Tool Overview of AHB Wrapper Generation ToolOverview of AHB Wrapper Generation Tool
Wrapper GeneratorAHB Wrapper
AHB
AHBMaster
InterfaceIP
Core
Configuration
Template
AHBSlave
Interface
IPCore
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The Flow to Use ToolThe Flow to Use ToolThe Flow to Use ToolThe Flow to Use Tool
Start
Valid ?
Configuration
System.cfgMaster.cfgSlave.cfg
No
WrapperGenerator
Yes
VerilogRTL
Code
Laboratory for Reliable Computing (LaRC)May-2004
Ming-Shen Liu & Cheng-Wen Wu 11
Software SystemSoftware SystemSoftware SystemSoftware System
Configuration Files
Parser
Evaluator
RTL Generator
Template
Verilog RTL Code
AMBA Wrapper Generator
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OutlineOutlineOutlineOutline
Introduction
Template and Configuration AHB Slave AHB Master
Verification and Simulation Result
Conclusion
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Ming-Shen Liu & Cheng-Wen Wu 13
AHB Slave Template InterfaceAHB Slave Template InterfaceAHB Slave Template InterfaceAHB Slave Template Interface Define some established signals for user to choose.
AHBSlave
Interface
HSELx
HWRITE
HSIZE[2:0]
HRESETn
HCLK
HADDR[31:0]
HREADYHRESP[1:0]
HRDATA[31:0]
HWDATA[31:0]
HTRANS[1:0]
HBURST[2:0]
WR_validRD_valid
Chip_select
WR_ready
RD_ready
Range
Start_WR
End_WR
.....
.....
ClkReset
IPCore
WR_data1
WR_data2
WR_dataN
RD_data1
RD_data2
RD_dataN
WR_addr
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AHB Slave TemplateAHB Slave TemplateAHB Slave TemplateAHB Slave Template WR_valid: this is a signal from Wrapper to slave IP core. Its
function is to indicate that write data is valid or not.
WR_valid: connected_port_name, <high|low>, time_offset WR_valid: wr_valid, high, 1
T0 T1 T2HCLK
HSEL
HWRITE
HTRANS 0 2
HADDR A
HREADY
HWDATA data
WR_valid
WR_data data
T0 T1 T2 T3 T4HCLK
HSEL
HWRITE
HTRANS 0 2
HADDR A
HREADY
HWDATA data
WR_valid
WR_data data
WR_ready
Without WR_ready Without WR_ready With WR_ready With WR_ready
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AHB Slave TemplateAHB Slave TemplateAHB Slave TemplateAHB Slave Template RD_valid: this is a signal from Wrapper to slave IP core. Its
function is to indicate that Wrapper will read data from slave, that is, Wrapper is ready to be transferred data from slave.
RD_valid: connected_port_name, <high|low>, time_offset RD_valid: rd_valid, high, 1
T0 T1 T2HCLK
HSEL
HWRITE
HTRANS 0 2
HADDR A
HREADY
RD_data data
RD_valid
HRDATA data
T0 T1 T2 T3 T4HCLK
HSEL
HWRITE
HTRANS 0 2
HADDR A
HREADY
RD_data data
RD_valid
HRDATA data
RD_ready
Wrapper Without RD_ready Wrapper Without RD_ready Wrapper With RD_ready Wrapper With RD_ready
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AHB Slave TemplateAHB Slave TemplateAHB Slave TemplateAHB Slave Template Range[N-1:0]: this is a signal from Wrapper to slave IP core. Its
function is to decode address and activate some signal high or low. And ‘N’ is an arbitrarily positive integer.
Range: <Yes|No>[, range_number, {connected_port_name, address_mask_pattern, <high|low>, delay}] Range: Yes, 2, dec_out1, 8000_xxxx, high, 0, dec_out2, 8100_xxxx, low, 1
HCLKHADDR A B
Range[0]Range[0] delay 1Range[0] delay 2Range[1]
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AHB Slave TemplateAHB Slave TemplateAHB Slave TemplateAHB Slave Template Start_WR: Its function is to indicate that an AHB master writes the first
transfer of a burst.
End_WR: Its function is to indicate that an AHB master writes the last transfer of a burst.
Start_WR: <Yes|No>[, connected_port_name, start_address, <high|low>, time_offset] Start_WR: Yes, init, 0, high, 0
End_WR: <Yes|No>[, connected_port_name, start_address, <high|low>, time_offset] End_WR: Yes, last, 0, high, 0
T0 T1 T2 T3 T4 T5 T6 T7HCLK
HWRITE
HTRANS 0 2 3 0
HADDR A A+N A+2N A+3N A+4N B
HREADY
HWDATA D0 D1 D2 D3 D4 D5
WR_valid
WR_data D0 D1 D2 D3 D4 D5
WR_ready
Start_WR
End_WR
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AHB Slave TemplateAHB Slave TemplateAHB Slave TemplateAHB Slave Template Chip_select: this is a signal from Wrapper to slave IP core. Its
function is to enable the slave core. It’s timing can be specified by time offset with respect to the reference cycle.
Chip_select: <Yes|No>[, connected_port_name, <high|low>, time_offset] Chip_select: yes, cen, low, 1
T0 T1 T2 T3HCLK
HSEL
HTRANS 0 2
Chip_select time offset = 0
Chip_select time offset = 1
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AHB Slave TemplateAHB Slave TemplateAHB Slave TemplateAHB Slave Template WR_Addr: this is a signal from Wrapper to slave IP core. Its
function is to translate AHB address to IP core or to translate IP address to AHB. WR_Addr: connected_port_name, bit_width, mask_pattern, time_offset WR_Addr: waddr_porta, 16, 0000_ffff, 1
WR_Data: this is a signal from Wrapper to slave IP core. It carries write data from Wrapper to IP core. It is allowed that there are several write data ports. WR_data: connected_port_name, bit_width, time_offset, address_mask_pattern WR_data: wdata_porta, 32, 1, 6000_xxxx
RD_Data: this is a signal from slave IP core to Wrapper. It carries read data from IP core to Wrapper. It is allowed that there are several read data ports. RD_data: connected_port_name, bit_width, address_mask_pattern RD_data: rdata_porta, 32, 6100_xxxx
Laboratory for Reliable Computing (LaRC)May-2004
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AHB Slave Template ExampleAHB Slave Template ExampleAHB Slave Template ExampleAHB Slave Template Example
AHBSlave
Interface
HSELx
HWRITE
HSIZE[2:0]
HRESETn
HCLK
HADDR[31:0]
HREADY
HRESP[1:0]
HRDATA[31:0]
HWDATA[31:0]
HTRANS[1:0]
HBURST[2:0]
WR_valid wr_valid
Chip_select cen
WR_ready ready
Range[0] dec_out1
IPCore
WR_data data_a
RD_data status
WR_addr address
RD_valid rd_valid
Range[1] dec_out2
WR_data data_b
Range: Yes, 2,
dec_out1, 8000_xxxx, high, 0,
dec_out2, 8100_xxxx, low, 1
WR_valid: wr_valid, high, 1
RD_valid: rd_valid, high, 1
WR_Addr: address, 16, 0000_ffff, 1
WR_data: data_a, 32, 1, 6000_xxx
WR_data: data_b, 16, 1, 6001_xxx
RD_data: status, 32, 6100_xxx
Range: Yes, 2,
dec_out1, 8000_xxxx, high, 0,
dec_out2, 8100_xxxx, low, 1
WR_valid: wr_valid, high, 1
RD_valid: rd_valid, high, 1
WR_Addr: address, 16, 0000_ffff, 1
WR_data: data_a, 32, 1, 6000_xxx
WR_data: data_b, 16, 1, 6001_xxx
RD_data: status, 32, 6100_xxx
Laboratory for Reliable Computing (LaRC)May-2004
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AHB Master TemplateAHB Master TemplateAHB Master TemplateAHB Master Template
AHBMaster
Interface
HSELx
HWRITE
HSIZE[2:0]
HRESETn
HCLK
HADDR[31:0]
HREADY
HRESP[1:0]
HRDATA[31:0]
HWDATA[31:0]
HTRANS[1:0]
HBURST[2:0]
IPCore
HBUSREQ
HLOCK
HGRANT
Cmd_valid
Cmd_latched
WdataWdata_valid
Wdata_latched
Rdata
Rdata_valid
Rdata_latched
Response
Resp_valid
Resp_latched
MerrorMretryMready
rw
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Write Transactions of AHB Master WrapperWrite Transactions of AHB Master WrapperWrite Transactions of AHB Master WrapperWrite Transactions of AHB Master Wrappercmd_validcmd_latchedcommandrwwdata_validwdata_latchedwdata D0
rdata_validrdata_latchedrdataresp_validresp_latchedresponse
HCLKHBUSREQHGRANTHTRANS[1:0] IDLE NONSEQ IDLE
HADDR[31:0]HWRITEHBURST[2:0]HPROT[2:0]HWDATA[31:0] ALL 0'S D0 ALL 0'S
HRDATA[31:0]HREADYHRESP[1:0]
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Read Transactions of AHB Master WrapperRead Transactions of AHB Master WrapperRead Transactions of AHB Master WrapperRead Transactions of AHB Master Wrappercmd_validcmd_latchedcommandrwwdata_validwdata_latchedwdatardata_validrdata_latchedrdata D0
resp_validresp_latchedresponse
HCLKHBUSREQHGRANTHTRANS[1:0] IDLE NONSEQ IDLE
HADDR[31:0]HWRITEHBURST[2:0]HPROT[2:0]HWDATA[31:0] ALL 0'S
HRDATA[31:0] D0
HREADYHRESP[1:0]
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OutlineOutlineOutlineOutline
Introduction
Template and Configuration
Verification and Simulation Result AHB Slave Wrapper
For Template Protocol For AMBA Compliance
AHB Master Wrapper For Template Protocol For AMBA Compliance
Conclusion
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EASY (Example AMBA SYstem)EASY (Example AMBA SYstem)EASY (Example AMBA SYstem)EASY (Example AMBA SYstem)
Ccode
TBEasysource file
rom0.datrom1.datrom2.datrom3.dat
External ROM models
ADS C compiler
ARM coremodel
SMI TIC Decoder
RetrySlave
MuxS2M MuxM2S
IntMem APBif
ArbiterDefaultSlave
AHB
AHB Wrapper
APB
IntCntl
RemPause
MuxP2B
Timers
ExtROM
Tube
Load
SRAM
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Verification of WR_valid, RD_valid, Chip_select, Verification of WR_valid, RD_valid, Chip_select, WR_data, RD_data and WR_addrWR_data, RD_data and WR_addr
Verification of WR_valid, RD_valid, Chip_select, Verification of WR_valid, RD_valid, Chip_select, WR_data, RD_data and WR_addrWR_data, RD_data and WR_addr
32 sequence address (HADDR) 0xE0000200 0xE0000204 0xE0000208
0xE000027C
5 wrapper type 5 types of timing-shift
HCLK
HRESETn
HSELx
HADDR
HWRITE
HTRANS
HSIZE
HWDATA
HRDATA
HREADY
HRESP
WR_valid
AHB
RD_validChip_select
WR_ready
RD_ready
Range
Start_WR
End_WRResponseWR_data1WR_data2
.....
WR_dataNRD_data1RD_data2
.....
RD_dataNWR_addr
ClkReset
SRAMAHBSlave
Wrapper
WEN
CEN
D
Q
A
CLK
……
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Verification of AHB Slave WrapperVerification of AHB Slave WrapperVerification of AHB Slave WrapperVerification of AHB Slave Wrapper Simulation with a counter and a SRAM
WR_valid
Chip_select
WR_ready
WR_data1
RD_data1
WR_addr
Clk
SRAM
WEN
CEN
D
Q
A
CLK
Counter
AHBSlave
Wrapper
HCLK
HRESETn
HSELx
HADDR
HWRITE
HTRANS
HSIZE
HWDATA
HRDATA
HREADY
HRESP
AHB
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Verification of Range SignalVerification of Range SignalVerification of Range SignalVerification of Range Signal
Range 0xE1000000,
0xE1000004, 0xE1000008, 0xE100000C, 0xE1000010
5 wrapper type: total pattern number is 25
HCLK
HRESETn
HSELx
HADDR
HWRITE
HTRANS
HSIZE
HWDATA
HRDATA
HREADY
HRESP
WR_valid
AHB
RD_validChip_select
WR_ready
RD_ready
Range
Start_WR
End_WRResponseWR_data1WR_data2
.....
WR_dataNRD_data1RD_data2
.....
RD_dataNWR_addr
ClkReset
SRAMAHBSlave
Wrapper
WEN
CEN
D
Q
A
CLK
Laboratory for Reliable Computing (LaRC)May-2004
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Verification of Start_WR and End_WR SignalsVerification of Start_WR and End_WR SignalsVerification of Start_WR and End_WR SignalsVerification of Start_WR and End_WR Signals
Start_WR 0xE2000000 HBURST[2:0] = 3’b001 (Incrementing Burst) 5 wrapper type: total pattern number is 5
End_WR 0xE3000000 HBURST[2:0] = 3’b001 (Incrementing Burst) 5 wrapper type: total pattern number is 5
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AMBA-Compliant Verification for AHB Slave AMBA-Compliant Verification for AHB Slave AMBA-Compliant Verification for AHB Slave AMBA-Compliant Verification for AHB Slave
Test Module
HADDR
HWDATA
HRDATA
DecoderAHBSlave-Wrapper
Other-Slave
Default-Slave
HADDR
HWDATA
HRDATA
HSEL
HADDR
HWDATA
HRDATA
HSEL
HADDR
HWDATA
HRDATA
HSELRead Data/Response Mux
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Basic transfers
Transfers to Other Slaves 0, 1 and greater than 1 wait state An ERROR response A RETRY response
Basic Read transfer with Wait States
Read transfers with IDLE cycles
Read transfers with BUSY cycles
Basic Write transfer with Wait States
Write transfers with IDLE cycles
Write transfers with BUSY cycles
Testbench Requirements for a Slave InterfaceTestbench Requirements for a Slave InterfaceTestbench Requirements for a Slave InterfaceTestbench Requirements for a Slave Interface
Laboratory for Reliable Computing (LaRC)May-2004
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Testbench Requirements for a Slave InterfaceTestbench Requirements for a Slave InterfaceTestbench Requirements for a Slave InterfaceTestbench Requirements for a Slave Interface Basic Burst transfers
Error response
Laboratory for Reliable Computing (LaRC)May-2004
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Test_Module(Virtual Master)
AHB MasterWrapper
cmd_valid
cmd_latched
commandwdata_valid
wdata_latched
wdatardata_valid
rdata_latched
rdataresp_valid
resp_latched
responseMERROR
MREADY
MRETRY
MADDR
MTRANSMWRITE
MBUSREQ
MBURST
Arbiter
RetrySlave
OKSlave
Decoder
ErrorSlave
SRAM
HSEL
Verification Architecture of AHB Master WrapperVerification Architecture of AHB Master WrapperVerification Architecture of AHB Master WrapperVerification Architecture of AHB Master Wrapper
Laboratory for Reliable Computing (LaRC)May-2004
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Testbench to Verify AHB Master WrapperTestbench to Verify AHB Master WrapperTestbench to Verify AHB Master WrapperTestbench to Verify AHB Master Wrapper For write/read data
cmd_valid = 1 command: ADDRESS = 0x0~0x1F (cmd_latched) wdata_valid = 1 (wdata_latched) cmd_valid = 1 command: ADDRESS = 0x0~0x1F (cmd_latched) rdata_valid = 1 (rwdata_latched)
Laboratory for Reliable Computing (LaRC)May-2004
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Testbench to Verify AHB Master WrapperTestbench to Verify AHB Master WrapperTestbench to Verify AHB Master WrapperTestbench to Verify AHB Master Wrapper For response
cmd_valid = 1 command: ADDRESS = 0xA0~0xA2 (resp_valid) resp_latched = 1 Check response Also check the operation of MERROR, MREADY and
MRETRY
Drive MADDR, MWRITE, MTRANS, MBUSREQ and MBURST respectively and then check the behavior of AHB
Laboratory for Reliable Computing (LaRC)May-2004
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AMBA-Compliant Verification for AHB MasterAMBA-Compliant Verification for AHB MasterAMBA-Compliant Verification for AHB MasterAMBA-Compliant Verification for AHB Master
Test Module 1with
AHBMaster-WrapperHADDR
HWDATA
HRDATA
DecoderAHBSlave-Wrapper
Other-Slave
Default-Slave
HADDR
HWDATA
HRDATA
HSEL
HADDR
HWDATA
HRDATA
HSEL
HADDR
HWDATA
HRDATA
HSELRead Data/Response Mux
Master 2
HADDR
HWDATA
HRDATA
Arbiter
Write Data/Address Mux
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Testbench Requirements for a Master InterfaceTestbench Requirements for a Master InterfaceTestbench Requirements for a Master InterfaceTestbench Requirements for a Master Interface First Transfer Responses
Ensure that all types of response are seen to the first transfer of burst.
Middle Transfer Responses
Last Transfer Responses
Losing Bus Ownership
Grant Response Combinations
Retry Responses
Multi-cycle Responses ERROR, RETRY and SPLIT with more than two cycles
Busy Transfers Generate a BUSY transfer for all responses to the previous
transfer
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Experiment for IPsExperiment for IPsExperiment for IPsExperiment for IPs Compare the time of the two flow to produce AHB wrapper
Configuration
Verilog RTL Code
Tool
CodingWrapper
Manual
Valid?
Verificationand
Debug
Verilog RTL Code
Simulationwith
ARM-basedSystem
daysminutes
VerificationIP
WrapperGenerator
Laboratory for Reliable Computing (LaRC)May-2004
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Experiment ResultsExperiment ResultsExperiment ResultsExperiment Results
AES RSA1 RSA2 HMAC
Total Time
(Manual)3-day 3~4 days 7-day 7-day
Total Time
(Generator)12 min. 23 min. 9 min. 20 min.
Manual Area
(gates)221 326 273 94
Generator’s Area
(gates)257 419 341 108
Area Overhead 16.29% 28.53% 24.91% 16.40%
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OutlineOutlineOutlineOutline
Introduction
Definition of Template Signals
Definition of Configuration
Simulation and Result
Conclusion
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ConclusionConclusionConclusionConclusion The method provides a simple and direct way that
designers’ IP core can be attached onto the AHB.
Advantage of using Wrapper Generator: Reducing time of producing wrapper:
Producing manually: hours Producing by Generator: minutes
Reducing the opportunity of wrapper’s error:
Disadvantage of using Wrapper Generator: Area overhead Can’t support every design type