An Approach to Single Event Testing of SDRAMs

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 57, NO. 5, OCTOBER 2010 2923

An Approach to Single Event Testing of SDRAMsPhilippe C. Adell, Larry Edmonds, Richard McPeak, Leif Scheick, and Steve S. McClure

Abstract—A unique testing approach based on error-patternidentification with a graphical mapping and color-coding ofthe full SDRAM memory during single-event characterizationis proposed. Results about unique SEFI modes and the role oftemperature are discussed.

Index Terms—Micro-displacement, SDRAMs, single eventeffects, stuck bits.

I. INTRODUCTION

S YNCHRONOUS Dynamic Random Access Memories(SDRAMs) are very sensitive to Single Event Effects

(SEU, MBU, SEFI, SEL and Stuck bits) [1]–[10]. When usedin space they are often protected by error detection or correc-tion (EDAC) circuit scheme for single upsets or architecturalscheme (widely separated bits in the same word) for MBUs.With modern SDRAMs, single event testing can be quite chal-lenging because of all the additional circuitry used to controlthe memory cells within the parts. As a result, it becomes moreand more difficult to address all different error modes with goodstatistics. Because heavy ion testing provides the most reliabledata and that current testing practices are very time consuming,it is critical to develop cost-efficient testing strategies thatprovide useful information to fly parts like these in spacewith low risk. In this work, we present a unique testing andanalysis approach that is based on error-pattern identificationwith a graphical mapping and color-coding of the full SDRAMduring single-event characterization. With this technique, alsoapplicable to other memory types, we were able to understandthe SEE behavior of the EDS5104ABTA-75 ELPIDA 512 MbSDRAM (i.e., 128 M words 4 bits). The work is organizedas follows: 1) we provide details about the testing approachand analysis method; 2) we present experimental results andinterpretation about the different unique SEFI modes and othererror-types (SEUs, MBUs and stuck bits) detected with asso-ciated statistics, and 3) we investigate the role of temperatureon the stuck bits response and test the micro-displacementpostulate provided by [3].

Manuscript received January 21, 2010; revised April 13, 2010; accepted July02, 2010. Date of publication September 16, 2010; date of current version Oc-tober 15, 2010. The research described in this paper was carried out at the JetPropulsion Laboratory, California Institute of Technology, under a contract withthe National Aeronautics and Space Administration.

P. C. Adell, L. Edmonds, L. Scheick, and S. S. McClure are with the JetPropulsion Laboratory, California Institute of Technology, Pasadena, CA91101-8099 USA (e-mail: [email protected])

R. McPeak is a consultant in San Pedro, CA 90731 USA (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TNS.2010.2059711

Fig. 1. Representation of the test system.

II. EXPERIMENTAL AND DATA ANALYSIS APPROACHES

The test system used to evaluate the SEE behavior ofthe EDS5104ABTA-75 ELPIDA SDRAM 512 Mb is shownin Fig. 1. The setup consists of a computer, a test head,power supplies and a device under test (DUT) supply currentrecorder with ms resolution. The computer sends commandsto the test head and provides the interface for the user tocontrol and monitor the test. It also coordinates the transferof data from the test head’s local memory in the computer’smemory, processes the DUT data and graphically displaysthe results. The display shows a variety of color-coded errormaps of the contents of the DUT.

The pattern used during the test is called “offset count”. It isan eight-bit pattern that is used for four-bit parts by generatinghalf of the eight bits for an even address and the other half for thefollowing odd address. In the case of a 512 Mb part, the patterngenerates essentially an equal number of 1 s and 0 s (268.8 M0 s, 268.0 M 1 s) and it generates at least 33 M errors for anyinternal stuck address or bank bit.

The pattern is generated by starting with an increasingeight-bit count from 0 to 255, which is followed by a de-creasing count from 254 back to 0. These 511 numbers arethen repeated over and over to fill a memory on the test boardwith approximately 36 K numbers. The DUT is written in 4K bursts of 32 K vectors. After each 32 K burst, the startingpoint in the sequence of 36 K numbers is incremented by one.Because the starting points of the bursts are different, each32 K burst is different from the others and the pattern neverrepeats for any power-of-two number. That is the reason that itcatches addressing problems. The even distribution of 1 s and 0s makes it effective for catching stuck data bit errors. If the part

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2924 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 57, NO. 5, OCTOBER 2010

Fig. 2. Representation of typical case where a bank SEFI error is represented.A single hit can affect a portion of a bank (100 s of rows with errors). Lightgreen background indicates no errors and dark green represents single errors.

Fig. 3. Representation of a typical case where single, double, triple and quadupsets are detected. Isolated dark green dots are single errors. Clusters consistingof two or more adjacent green dots are shown as red dots and indicate multipleupsets.

Fig. 4. Representation of an extreme case where � �� errors wererecorded after a fluence of �� with Xenon (LET of � �� ).

has problems with writing and reading, just about any patternwill work fine. A data analysis program enables the user tosearch the DUT data for various types of error (SEFI, MBU,SEU, Stuck bits) or patterns (combination of errors). Severalillustrations of the type of error that can occur during a heavy

ion run are shown on Figs. 2–4. For each figure, a display of thefull memory with its four banks is represented. For every bankall rows are represented. Foreground displays are blown-upviews. The clock frequency at which the part was operated is67 MHz.

An error can range from a single upset to a multiple rowerrors. Note that it is possible to get inside a row and lookfor column patterns and look at error type (single, double,triple upsets) in a word. Fig. 2 shows a typical case wherea bank SEFI error is represented. A single hit can affect aportion of a bank (100 s of rows with errors). Figs. 3 and 4show red-dot rows with over 1000 errors after a single hit.For all figures, dark green dots are rows with columns withone error. Red line stripes in Figs. 3 and 4 (several rowswith more than 1000 errors) were induced by a single hitand was only obtained at angle . Every error type ischaracterized with its associated statistics based on criteria setby the user. Note that Fig. 4 shows the results of an extremecase where about 20 million errors were recorded after afluence of with Xenon (LET of ).A noticeable difference in sensitivity between banks (two leftbanks and two right banks) is shown. This is a very importantresult because it could define how science data would bestored during a space mission. For instance, towards the endof a mission, a recommendation would be that critical datashould be stored in less sensitive banks of the memory.

To conclude, this analysis method allows for clear deter-mination and differentiation of SEU, SEFI and MBU thatmight be missed if a reduced amount of the memory istested or the data is inspected as lists of numbers. To ourknowledge this is the first time that this type of approach isreported. Indeed, when a part is inspected as a list of numbers,the idea is to compare the output data stream against theexpected data and count the number of times they disagree.The advantage of this approach is that it is relatively easyto build the test circuit. The biggest disadvantage is that ittells you very little about the nature of the errors. Then,assuming that a portion of the memory is representative ofthe entire device also makes it much easier to build a testerand it drastically reduces the difficulty of analyzing the testdata. The disadvantage is that the entire memory has to betested in order to justify the assumption that the portiontested is actually representative of the entire device. Theother problem is that the assumption is incorrect for manydevices. Finally, these commonly used approaches are notadequate or optimized and make testing of the full memorytesting very time consuming and costly [1]–[10]. The ben-efit of our work is that we show the full content of thememory for each heavy ion run in a cost-efficient way andwe recommend pattern analysis for SEU, MBU and SEFIdetection. A 100% test eliminates all of the guessing anddrawing a visual display of the data makes it much easierto understand the nature of the errors. It should be notedthat the error displays are different for stuck address bitsthan they are for stuck bank bits and can be simulated withthe tool in addition to experimental data. Finally, since the

ADELL et al.: AN APPROACH TO SINGLE EVENT TESTING OF SDRAMS 2925

TABLE IION SPECIES USED DURING THE TEST

analysis tool is reconfigurable, it can be altered to investigateany error pattern.

III. EXPERIMENTAL RESULTS AND INTERPRETATIONS

A. Experimental Details

Experiments were performed at Texas A&M facilities withthe 15 MeV/amu ion cocktail detailed in Table I. Some of thedata points were taken with ions used at angle, particularly forhigh LET values. For most of the data points shown in the dif-ferent figures, three parts have been evaluated. All the resultsgiven below were obtained by reading the memory during eachheavy ion run.

B. Experimental Results

With the pattern identification approach described above,single, double and triple bit upsets were recorded for eachion-type with different LETs. The associated cross sectioncurves are plotted in Fig. 5. The results show that single bitupsets have a higher probability to occur compared to doubleand triple bit upsets. For the three error types the LET thresholdis relatively low and the saturated cross section is high indi-cating that the memory is quite SEUs/MBUs sensitive. Fig. 5shows an interesting result at angle with a significant increaseof triple bit upset over 45 degrees. Irradiation at angle over 45degrees generated several red line stripes containing severaltens of rows with over 1000 errors. These error types werewell distributed within the banks and often occurred at thesame location within the four banks indicating some impact inthe surrounding circuitry operating the memory cells. Hence,these appear to be SEFI-type errors. This SEFI type could notbe recovered by reloading the mode register and generatedadditional triple and quadruple errors.

Another category of SEFI was recorded and occurred witha relatively high probability compared to SEUs. The SEFI wasthe loss of a large portion (hundreds of rows) of a bank after asingle ion hit. It is displayed during the test as a large band errorsimilar to the one shown in the display of Fig. 2 (see band oncomputer screen in Fig. 2, or the red bands in Fig. 6). This typeof error was fixed by reloading the mode register. The associ-ated cross section curve is given in Fig. 6. The LET threshold isabout and the saturated cross section is about

. This SEFI was the most critical becauseif the mode register was not reloaded periodically

Fig. 5. Single, double and triple bit upset cross sections as a function of LET.An effect at angle has been observed and results in a large increase in sensitivityfor triple-bit errors.

Fig. 6. SEFI (Bank multiple rows error) cross section as a function of LET.This SEFI type could be recovered by reloading the mode register.

during the runs, millions of errors would have been generated ata relatively low fluence making the memory useless. This resultsuggests that when used in space, some EDAC software modi-fications would have to be made to mitigate this SEFI.

A third category of SEFI was recorded during the test: thisSEFI type was generating over 1000 errors in a single row afteran ion hit. This SEFI could not be eliminated by reloading themode register. It could only be fixed by rewriting or by poweringON/OFF the memory.

With the analysis program we were able to first isolate thisthird category of SEFI from other errors occurring during therun, verify the error distribution among the four banks and gen-erate the associated statistics for each run. Fig. 7 illustrates howerrors are isolated and distributed within banks after a singlerun, and Fig. 8 provides the resulting statistics.

In this case, the LET threshold is and thesaturated cross section about . In addi-tion to SEUs, MBUs and SEFI modes, no single event induceddevice hang was recorded during the course of this evaluation.This SDRAM was also latchup free.


Fig. 7. Representation of the four banks of the memory tested after a run. OnlySEFI (rows with over 1000 errors) are represented.

Fig. 8. Representation of another SEFI type (row with over 1000 errors) asa function of LET. Cross section values are much lower compared to single,double and triple bit upsets. However this error type cannot be cleared afterreloading mode register. They are very well distributed within the four banks.

The number of stuck bits (the number in which the retentiontime is less than the refresh time, i.e., the leakage is bad enoughthat the bit cannot maintain its state until the next refresh) werealso recorded with this test system for different refresh times. Asshown in Fig. 9, the number of stuck bits has been recorded up toa fluence of with Kryptonfor four different refresh times (64, 128, 256 and 512 ms).

As shown in the figure, the number of stuck bits recorded isvery low and it indicates that the cross section is relatively lowcompared to other error types. It should be noted that all bitscould be recovered by reducing the refresh time at room temper-ature. However, a strong temperature dependence was observedduring the test and additional data were taken to investigate therole of temperature on stuck bits.

IV. IMPACT OF TEMPERATURE ON LEAKY BITS RESPONSE

Recent work [3] postulated that ion induced stuck bits arecaused by micro-displacement damage in the reverse biased de-pletion region of the memory cell. This damage increases theleakage current and, as previously stated, the bit is called “stuck”if the leakage is bad enough that the bit cannot maintain its state

Fig. 9. Number of stuck bits as a function of fluence for different refresh times(64, 128, 256 and 512 ms).

until the next refresh (i.e., if the data retention time is shorterthan the refresh time). A plot of the number of stuck bits versusrefresh time is equivalent to a plot of the number of bits havinga data retention time that is shorter than a given value. A plot ofthe number of stuck bits versus temperature reflects the depen-dence that data retention time has on temperature, which in turnreflects the leakage rate as a function of temperature. This pos-tulate can be used to predict the temperature dependence, andthe postulate will be tested by comparing predictions to data.The number of stuck bits after a fluence of withKrypton at an LET of was recorded foreach of several refresh times (32, 64, 128, 256 and 512 ms). Themeasured results are shown as the solid symbols in Fig. 10 (theopen symbols are discussed later). For each of the two temper-atures considered (room temperature and 70 ), the number ofstuck bits versus refresh time is plotted. The figure shows a verystrong temperature dependence. By taking a closer look at thedata and by making a comparison between the two temperaturesin Fig. 10 we were able to test the credibility of the proposedmechanism.

The displacement damage postulate is seen as defects that actas recombination-generation sites, but the generation dominatesrecombination in a reverse-biased depletion region because thecarrier density is less than the equilibrium density. It can beshown that the current density due to the carrier generation inthe depletion region is given by [8]

(1)

where is the intrinsic carrier density, is the depletion-layerwidth, and is the effective lifetime defined in [8]. If we as-sume that the effective lifetime is a slowly varying function oftemperature, the generation current will then have the same tem-perature dependence as [8]. For a silicon device, increasesrapidly with temperature, doubling every 11 [8].

Therefore, the generation current produced by a given gener-ation site at 70 is expected to be about 16 times the current

ADELL et al.: AN APPROACH TO SINGLE EVENT TESTING OF SDRAMS 2927

Fig. 10. Comparison of the number of stuck bits after a fluence of �� with Krypton at an LET of �� for different refresh times.By increasing the temperature, the number of bits increases. Solid symbols aremeasurements at the refresh times 32, 64, 128, 256, and 512 ms. Open symbolsare predictions for one temperature derived from the displacement damage pos-tulate applied to measurements at the other temperature.

Fig. 11. Comparison of the number of stuck bits after a total dose exposure of50 krad for different refresh times at room temperature and 70 C. Irradiationconditions were 25 rad(Si)/s on five parts from the same lot. Electrical test wasdone within one hour following radiation exposure and units returned to Co-60cell for next irradiation steps within 2 hours. Note that total dose has almost noeffect (unlike the heavy ion results) although temperature does have an effect.The refresh time units are “s” (compared to ms in Fig. 10) to obtain a statisticallysignificant number of stuck bits.

from the same generation site at room temperature. The reten-tion times at the two temperatures are expected to be in the re-ciprocal ratio. This is the prediction from the physical assump-tion stated above. We can determine whether this prediction isconsistent with the data in Fig. 10 from the following consider-ations. Select a room-temperature point in the figure, with thispoint described by a number of stuck bits and a refresh time

. If a measurement is now performed at 70 , we would ex-pect this same number of bits to now fail at a refresh timeof . In other words, data points measured at room temper-ature can be used to predict the expected behavior at the hightemperature by simply dividing the horizontal coordinate by 16.Similarly, data points measured at the high temperature can beused to predict the expected behavior at room temperature bymultiplying the horizontal coordinate by 16. This produces theopen symbols in Fig. 10. The fact that the open symbols (pre-dictions) merge with the solid symbols (measured) implies that

the micro-displacement as a physical mechanism appears to beconsistent with the measured data.

The above consistency does not, by itself, exclude other pos-sibilities. It might be postulated that total ionizing dose (TID)is the mechanism that produces leaky bits. This postulate wastested by irradiating a device with 50 krads from a gamma-raysource, which produced results shown in Fig. 11. This doseslightly exceeds the dose produced by the heavy ions at thelargest fluence plotted in Fig. 9. One observation from Fig. 11 isthat TID has virtually no effect (in contrast, Fig. 9 shows a strongeffect from heavy-ion irradiation). In fact, the time units for thehorizontal axis in Fig. 11 are seconds (instead of ms) to ob-tain a statistically significant number of stuck bits, because thisfigure essentially describes a virgin device. However, Fig. 11does show a temperature dependence. This dependence closelyresembles that seen in Fig. 10. This suggests that the leakagemechanism in a virgin device might be the same as in a devicesubjected to heavy-ion irradiation (currents produced by defectsacting as generation sites), but the defects are milder and lessabundant in the virgin device compared to the irradiated device.

V. CONCLUSION

We evaluated the SEE behavior of the EDS5104ABTA-75ELPIDA SDRAM using a unique testingand analysis approach that is based on error pattern identifi-cation with a graphical mapping and color-coding of the fullmemory during single event testing. This approach helps iden-tify all error types with very good statistics and emphasizes thatSEE testing of memories require pattern analysis. Unlike sev-eral reported works, we justify why the full memory needs to betested.

Several key results were extracted from this testing technique:1) single, double, triple and quad bit upsets were measured withan interesting angular effect; 2) three main categories of uniqueSEFI modes were identified and two of them could be fixed byreloading the mode register; 3) while the memory exhibited arelatively low cross section of stuck bits at room temperature,we show that temperature has a very strong effect on this lattersingle event type. Also, by comparing devices irradiated withheavy ions to devices exposed to the same amount of dose fromgamma rays, results seem to indicate that the creation of stuckbits is not a dose effect for this particular device. However, themicro-displacement postulate recently proposed [3] appears tobe consistent with the temperature dependence seen in the mea-sured data. This consistency does not imply that the postulatemust be correct, but does add some credibility to the postulate.In any case, because of the temperature sensitivity experimen-tally seen for this part, a recommendation is to operate this partat relatively low temperature ( room temperature) when usedin space.

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[3] L. Edmonds et al., “Physical mechanisms of ion-induced stuck bits inthe Hyundai 16M x 4 SDRAM,” IEEE Trans. Nucl. Sci., vol. 55, no. 6,pp. 3265–3271, Dec. 2008.

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An Approach to Single Event Testing of SDRAMs

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