An Algorithm for Optimal Decoupling Capacitor Sizing and Placement for Standard Cell Layouts

04/19/23 ISPD'02, San Diego, CA 1

An Algorithm for Optimal Decoupling Capacitor Sizing and Placement for

Standard Cell Layouts

Haihua Su, Sani R. Nassif

IBM ARL

Sachin S. SapatnekarECE Department

University of Minnesota


Outline

On-chip decap overview Modeling and noise analysis Problem formulation and Adjoint sensitivity analysis Decap sizing and placement scheme Experimental results Conclusion


On-chip Decoupling Capacitors

Non-switching gate capacitance Thin oxide capacitance

hwt

Cox

ox

w: width of decaph: height of decaptox: thickness of thin oxideox: permittivity of SiO2


1st order model

2nd order model (non-idealities)

Decoupling Capacitor Models


Power Network Modeling

Power Grid: resistive mesh Cells: time-varying current sources Decaps: 1st order or 2nd order decap model Package: inductance + ideal constant voltage source

+


Power Grid Noise Analysis

Noise metric: shaded area

Waveform of node j on VDD grid

Vj+

Z = z(j)

z(j)

Reference: A. R. Conn, R. A. Haring and C. Visweswariah, Noise Considerations in Circuit Optimization, ICCAD’98


Formulation - Constrained Nonlinear Programming Problem

Minimize Z(wj), j = 1..Ndecap

Subject to wk (1-ri)Wchip, i = 1..Nrow

And 0 wj wmax , j = 1..Ndecap

– ri is the occupancy ratio of row i

Cell

Decap

wj


Solver – Sequential Quadratic Programming (SQP)

QPSOL - Quasi-Newton method to solve the problem of multidimensional minimization of functions with derivatives

Requirements– evaluation of the objective function and constraint functions– calculation of first-order derivatives


Adjoint Sensitivity Analysis

Original circuit

)()()( tutxCtGx Adjoint circuit

)()(ˆ)(ˆ ixCxG

x(t) and – node voltages, source currents, inductor currentsu(t) – time-dependent sourcesi() – current sources applied to all bad nodes

)(ˆ x ij()

Vj(t)+


T

CC dttvtTC

Z0

)()(

Convolve to get sensitivities

T

RR dttitTR

Z0

)()(

Z is the noise metric for all the grid = z(j)

Adjoint Sensitivity Analysis (cont’d)


Fast convolution for piecewise linear waveforms

]2/)()[(

)]([

)]([)'(

pqkkTgpqb

dttTkgb

dttTkgbta

qp

qp

p q

Adjoint Sensitivity Analysis (cont’d)

~O(N+M)N linear segments

M linear segments


Sensitivity w.r.t. Decaps

Adjoint sensitivity w.r.t. Cnear, R and Cfar

Applying chain rule to find the sensitivity w.r.t. decap width w:

w

C

C

Z

w

R

R

Z

w

C

C

Z

w

Z far

far

near

near


Scheme

Analyze circuit and store waveforms Compute Z Setup current sources for adjoint circuit Analyze adjoint circuit & store waveforms Compute Z/Ci and Z/wi Evaluate constraint function & gradients Feed to QP solver to get the updated wi According to the new wi , replace cells and decaps

one by one


Decap Optimization Process(one row for illustration)

Start from equal distribution of decaps:

Iteration 1:

Iteration 2:


Optimization Results

12.5

15.2

0.9

CPU time

(mins)

132

85

53

Num of

rows

0.649 0.200

0.366 0.063

0.121 0.000

Z(Vns)

0.222 0.201

0.230 0.196

0.193 0.176

Vmax(V)

828

861

974

Num of

nodes

100 70

80 63

105 2

Num bad

nodes

Before After

Before After

Before After

Opt

3

2

1

Chip

Vdd =1.8V, vdrop limit =10%Vdd, ri = 80%

3664

3288

1964

Num of

dcps


VDD and GND Contour (chip2)

Vmax=0.190V Vmax=0.191V Vmax=0.230V Vmax=0.196V

Z=0.366(V•ns) Z=0.063(V•ns)


Optimal Placement (chip2)


Noise Reduction Trend (chip2)


Conclusion

Proposed a scheme of decoupling capacitor sizing and placement for standard-cell layouts

Applied after placement and before signal routing Formulated into nonlinear programming problem Reduced transient noise Presented a fast piece-wise linear waveform

convolution for adjoint sensitivity analysis


Thank you!

An Algorithm for Optimal Decoupling Capacitor Sizing and Placement for Standard Cell Layouts

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