AN 747: Implementing PHYLite in Intel® Arria® 10 Devices ... · • Three instances of the Altera...

AN 747: Implementing PHYLite inIntel® Arria® 10 Devices DesignExamplesAN-7472017.05.08

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Contents

1 AN 747: Altera PHYLite for Parallel Interfaces Loopback Reference DesignsApplication Note ....................................................................................................... 31.1 Simple Input/Output PHYLite Simulation Design Example.............................................3

1.1.1 Simulation Design Example Architecture........................................................ 31.1.2 Simulation Reference Design User Guide........................................................41.1.3 Result....................................................................................................... 7

1.2 Simple Input/Output PHYLite with Dynamic Reconfiguration Hardware ReferenceDesign...............................................................................................................91.2.1 Hardware Reference Design Architecture........................................................91.2.2 Hardware Design Example User Guide......................................................... 101.2.3 Result..................................................................................................... 16

1.3 Functional Description........................................................................................... 181.4 Document Revision History.....................................................................................20

Contents

AN 747: Implementing PHYLite in Intel® Arria® 10 Devices Design Examples2

1 AN 747: Altera PHYLite for Parallel Interfaces LoopbackReference Designs Application Note

This application note showcases loopback reference designs using the Altera PHYLiteIP core.

This document is divided into three main segments:

1. A simple input/output PHYLite simulation reference design.

2. A simple input/output PHYLite with dynamic reconfiguration using Arria 10 deviceshardware reference design.

3. Functional description for the modules and application used in both referencedesigns.

1.1 Simple Input/Output PHYLite Simulation Design Example

This section provides architecture description and user guide for the simulationreference design.

1.1.1 Simulation Design Example Architecture

The simulation reference design is a simple design that simulates the behavior of theAltera PHYLite IP core. This design consists of 2 main components:

• A device Under Test (DUT) module that includes two Altera PHYLite IP instances.

• A traffic generator module

1 AN 747: Altera PHYLite for Parallel Interfaces Loopback Reference Designs Application Note

Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartusand Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or othercountries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.

ISO9001:2008Registered

http://www.altera.com/support/devices/reliability/certifications/rel-certifications.html



Figure 1. Simulation Reference Design Block Diagram

Traffic Generator (tg.sv)DUT

dut_INPUT

dut_OUTPUT

group_0_data_to_core[31:0]group_0_rdata_valid[3:0]

core_clk_out [1]

interface_locked[1]

core_clk_out[0]

interface_locked[0]group_0_data_out[3:0]

group_0_strobe_out group_0_data_from_core[31:0]group_0_oe_from_core[15:0]group_0_strobe_out_in[7:0]

group_0_strobe_out_en[3:0]

group_0_rdata_en[3:0]group_0_data_in[3:0]

group_0_strobe_in

reset_n

ref_clk

ref_clk

reset_n

locked

correct_data_counter[15:0]

phylite_top

done

pass

reset_n

Altera PHYLIte IP core

User logic

tb.v

1.1.2 Simulation Reference Design User Guide

Follow these steps to setup and run the simulation reference design.

1.1.2.1 Requirements

The following are the requirements to run the simulation reference design:

• Quartus Prime Design Suite® versions 15.1

• Simulation design example phylite_top_sim_only.par

Related Links

• AN 747: Altera PHYLite Simulation Reference Design Files

• Getting Started with the Design StoreGuideline to download and install design examples from Design Store.

1.1.2.2 Setting Up the Simulation Environment

1. Follow the guidelines in Getting Started with the Design Store to download andinstall the reference design files.

2. Open the reference design .qpf file after successfully installing the designtemplates.

3. Click on Assignments -> Settings....

4. Select EDA Tools Settings -> Simulation.



http://cloud.altera.com/devstore/platform/473/

https://cloud.altera.com/help/devstore/#collapseOne


5. At the Settings window, choose ModelSim* - Intel FPGA Edition for ToolName. You may choose VHDL, Verilog HDL or System Verilog as the outputnetlist format.

Figure 2. Simulation Settings using EDA Tools in the Quartus® Prime Software

6. Open dut_INPUT.qsys file and make sure the IP has the same configuration shownbelow:

Figure 3. Configuration for dut_INPUT Module

7. Make sure that the Capture strobe phase shift is set to 0 degrees to align theincoming data to strobe edge during data transfer.



8. Click Generate HDL... and select your desired simulation model format. Next,click Generate to generate the simulation model for the dut_INPUT module. ClickClose and Finish when the generation is complete.

Figure 4. Generating Simulation Model

9. From the Quartus® Prime software, open dut_OUTPUT.qsys file and make sure theIP has the same configuration shown below:

Figure 5. Configuration for dut_OUTPUT Module



10. Make sure the Output strobe phase is set to 0 degrees to align outgoing datawith strobe edge during data transfer.

11. Repeat step 9 to generate simulation model for dut_OUTPUT module.

12. From the Quartus Prime software, click Processing ➤ Start ➤ Start Analysis &Elaboration to compile the design.

Related Links

Getting Started with the Design StoreGuideline to download and install design examples from Design Store.

1.1.2.3 Running Simulation

1. From the Quartus Prime software, click Tools -> Run Simulation Tool -> RTLSimulation to bring up the Modelsim-Altera tool.

2. The simulation starts automatically when you launch the ModelSim - Intel FPGAEdition tool.

3. When the simulation ends, click No when the Finish Vsim window prompt appearto analyze the simulation waveform.

1.1.3 Result

The simulation result of the reference design shows the behavior of:

• Reference clock (refclk) signal

• Reset (reset_n) signal

• Interface locked (locked) signal

• Correct data counter (correct_data_counter) values

• Transmitted and received data (group_0_data) bus

• Simulation complete (done) signal




Figure 6. Design Example Simulation Flow

Simulation starts

Reference clock starts running at 200 MHz.

De-asserts reset_n signal at 70 ns.

The interface locked signal is asserted at 4805 ns to indicate PLL and the PHY circuitry are locked.

Once locked signal is asserted, data transmission begins. Correct read data values

are shown in the Transcript window.

Correct data counter starts counting at 4855 ns.

Asserts done signal to indicate simulation completed.

Simulation ends

The following shows the behavior of the signals.



Figure 7. Reset Signal De-assertion

Figure 8. Data Transfer After Locked Signal Assertion

Figure 9. Simulation Complete with Done Signal Assertion

1.2 Simple Input/Output PHYLite with Dynamic ReconfigurationHardware Reference Design

This section provides architecture description and user guide for the hardwarereference design.

1.2.1 Hardware Reference Design Architecture

The hardware reference design is an expansion of the simulation reference design.This reference design provides the ability to perform dynamic reconfiguration to thePHYLite IP cores using Nios II soft processor.

The hardware reference design consists of:

• Three instances of the Altera PHYLite IP core (dut_INPUT, dut_OUTPUT anddummy).

• Traffic generator module

• Nios II soft processor

• The In-System Sources and Probes IP core



Figure 10. Hardware Reference Design Block Diagram

DUT

dut_INPUT

dut_OUTPUT

group_0_data_to_core[31:0]group_0_rdata_valid[3:0]

core_clk_out [1]interface_locked[1]

core_clk_out[0]

interface_locked[0]

group_0_data_out[3:0]

group_0_data_from_core[31:0]

group_0_oe_from_core[15:0]

group_0_strobe_out_in[7:0]

group_0_strobe_out_en[3:0]

group_0_rdata_en[3:0]

phylite_top

Traffic Generator(tg.sv)

reset_n

Dynamic Configuration Controller(atso_dyn_cfg_ctrl)

Avalon Controller(altera_phylite_avl_ctrl)

dummy

In-system source and probes(altsource_probe)

reset_nref_clk

cfg_done

shifter

group_0_rdata_en

group_0_rdata_en

group_0_strobe_in_sepgroup_0_data_in[3:0]

avl_address[31:0]avl_byteenable[3:0]

avl_clk[1]

avl_read

avl_writedata[31:0]avl_write

avl_reset_n

pio_reset_n

avl_waitrequestavl_readdata_validavl_readdata[31:0]

reset_nref_clk

avl_clk[0]

correct_data_counter[15:0]pass

avl_reset_n

locked

done

locked

pass

group_0_strobe_out

Altera PHYLIte IP core

User logic

1.2.2 Hardware Design Example User Guide

1.2.2.1 System Requirements

The following are the software and hardware requirements to run the hardwarereference design.

Software Requirements

• Quartus Prime Design Suite version 15.1

• Quartus II software version 13.1

• Hardware reference design phylite_top_1DQS_2DQ_800MHz.par file

Hardware Requirements

• Arria 10 FPGA development kit

• Loopback FPGA mezzanine (FMC) daughter card

• Intel® FPGA Download Cable II



Related Links

• AN 747: Altera PHYLite with Dynamic Reconfiguration Reference Design Files

• Getting Started with the Design StoreGuideline to download and install design examples from Design Store.

1.2.2.2 Setting Up the Development Kit

The following steps are to setup the Arria 10 FPGA development kit before running thereference design.

1. Make sure the Arria 10 FPGA development board switches settings are shown asbelow.

Figure 11. Switch Settings for Arria 10 FPGA Development Kit

2. Connect the Intel FPGA Download Cable to the Arria 10 FPGA development kit andyour host machine.

3. Follow the guidelines in Getting Started with the Design Store to download andinstall the reference design files.

4. Open the reference design .qpf file after successfully installing the designtemplates.

5. In the Quartus Prime software, open dut_INPUT.qsys and dut_OUTPUT.qsysfiles. Make sure the Altera PHYLite IP core has the configuration shown below:



https://cloud.altera.com/devstore/platform/474/



Figure 12. Configuration for dut_INPUT Module

Figure 13. Configuration for dut_OUTPUT Module

6. Click Tools -> Programmer to program the <project directory> /master_image/top.sof and <project directory>/master_image/max5.pof files into the Arria 10 FPGA development board.

7. In the <project directory>/core/ folder directory, copy the clk_gui.zipfolder to your local machine.

8. In your local machine Quartus II software installation version 13.1 folder, go to<installation directory>\win64\nios2eds\Nios II CommandShell.bat and execute NIOS II Command Shell.bat.



9. In the command shell, specify the clk_gui folder path with the command: cd<directory to the copied clk_gui folder>.

10. Use the command java -jar clk_cont.jar to launch the clock control GUI.

11. In the clock control GUI, set the target frequency as 50MHz for Si570 (X3)window. Click Set New Frequency.

Figure 14. Clock Control Setup

Related Links

Getting Started with the Design StoreGuideline to download and install design examples from Design Store.

1.2.2.3 Generating Executable and Linking Format (.elf) Programming File

Follow the steps below to generate an executable and linking format (.elf)programming file. These steps are necessary if you modify thephylite_dynamic_reconfiguration.c,phylite_dynamic_reconfiguration.h and hello_world.c files.




1. In the Quartus Prime software version 15.1, select Tools ➤ Nios II SoftwareBuild Tools for Eclipse .

2. Create a new workspace when the Select a workspace window prompt appears.

3. A Nios II - Eclipse window appears. Select File ➤ New ➤ Nios II Applicationand BSP from Template .

4. In the SOPC Information File name parameter, browse to the location ofphylite_nios.sopcinfo file in your host machine. Click OK to select the fileand Eclipse automatically loads all CPU settings.

5. In the Project name parameter, specify your desired project name. This exampleuses phylite_nios_1DQ2DQS_new.

6. Choose Hello World as the project template.

7. Click Finish to generate the project. Quartus Prime software creates a newdirectory named software in the specified project location.

Figure 15. Nios II Application and BSP from Template Settings

8. Replace the following files from <project directory>/software referencedesign with the files located in your new software directory.



• hello_world.c

• phylite_dynamic_reconfiguration.c

• phylite_dynamic_reconfiguration.h

9. In the Nios II - Eclipse window, press F5 to refresh the window and reload the newfiles into the project.

10. Click Project ➤ Build Project.

11. Make sure the phylite_nios_1DQ2DQS_new.elf file is generated in the new<project directory>/software/phylite_nios_1DQ2DQS_new/ directory.

1.2.2.4 Running the Hardware Reference Design

Follow the steps below to run dynamic calibration and start the data transfer for thehardware reference design.

1. In the Quartus Prime software installation directory in your host machine anddouble click on Nios II Command Shell.bat to launch the command promptwindow (command prompt A). Repeat this step to launch the second commandshell (command prompt B).

Command prompt A is to display the dynamic calibration result. Command promptB is used to run Nios II commands.

2. In command prompt A, use the following command to run the Nios II terminalapplication for result printouts.

nios2-terminal

3. In command prompt B, go to the project top directory.

cd <project directory>

4. Run the issp.tcl script once to reset the system and clean up the instructionmemory in the Nios II soft processor.

quartus_stp -t issp.tcl top.qpf 1 1

Note: Ignore the failing dynamic calibration result displayed in command promptA. This is the result from the original executable code in the Nios II memoryand is not relevant to the design example.

5. In command prompt B, download the executable(phylite_nios_1DQ2DQS_new.elf) file into the FPGA and start the dynamiccalibration process with the following command:

nios2-download -r -g software/phylite_nios_1DQ2DQS_new/phylite_nios_1DQ2DQS_new.elf

You may observe the passing dynamic calibration result displayed in commandprompt A.

6. When the Nios II instruction memory is cleaned and calibration is done, run thefollowing command in command prompt B to reset the system, start the randomdata transfer and capture internal signals.

quartus_stp -t issp.tcl top.qpf 1 1 1

Note: You will see sent and received data displayed in command prompt B afterrunning the command.



1.2.3 Result

The hardware reference design provides:

• Dynamic calibration result

• Random data transfer result

1.2.3.1 Dynamic Calibration Result

The following screen capture shows the dynamic calibration result of the hardwarereference design.



Figure 16. Dynamic Calibration Result

The screen capture includes:

• Sent and received data.

• Indication of dynamic calibration has passed.

• Indication that the configuration is done.

• The value of the window start phase, window end phase, centered output phaseand the strobe enable window width.



1.2.3.2 Random Data Transfer Result

The result log from the random data transfer process displays the following:

• The number of words being transferred

• The sent data value

• The expected data value

• The received data value

• The passing/failing status of the test

Figure 17. Example of Random Data Transfer Result Log

1.3 Functional Description

Device Under Test (DUT) Module

The DUT module consists of two Altera PHYLite IP instances:

• 4-bit dut_INPUT module

• 4-bit dut_OUTPUT module

The function of the dut_INPUT module is to:

• Receives data aligned to strobe edge from external I/O interface.

• Receives rdata_en signal from traffic generator.

• Transmits data from external I/O interface to the traffic generator.

The function of dut_OUTPUT is to:

• Receives data, strobe, and output enable from the traffic generator.

• Transmits edge aligned data and strobe to external I/O interface.

The DUT module in the hardware reference design also consists of a PHYLite AvalonController. The functions of the PHYLite Avalon controller includes:

• To perform address translation for each reconfigurable feature of the PHYLite IP.

• To cache all necessary settings for each reconfigurable feature of the PHYLite IP.

• To translate Nios II soft processor commands into PHYLite commands.



Traffic Generator

The traffic generator module is called tg and is located in the tg.v file.

The functionality of the traffic generator includes:

• Continuously generates data to dut_OUTPUT module through Linear FeedbackShift Register.

• Asserts rdata_en signal to dut_INPUT module to read the loopback data fromdut_OUTPUT module.

• Compares received data against the regenerated/transmitted data.

• Increments correct_data_counter for every correct data received. Thecorrect_data_counter is a 15-bit counter.

• Asserts the done signal to indicate all data has completely received correctly.

In the hardware design example, the traffic generator sends out loopback data forcomparison after NIOS II processor completes the calibration process.

NIOS II Soft Processor

The Nios II soft processor calibrates read and write operations. The Nios II interfaceswith the DUT module through the Avalon Controller.

Dummy PHYLite

Due to the limitation of the Arria 10 development board, this module is required toenable the design example to connect a reference clock to the DUT module data pins.

In-System Sources and Probes (altsource_probe) Module

This module is an in-system debugging IP. You can use this module to drive andcapture the behavior of the internal signals in the design example. This module is onlyused in the hardware design example.

Design Example Software

The hardware design example requires hello_world.c,phylite_dynamic_reconfiguration.c andphylite_dynamic_reconfiguration.h files to run.

The hello_world.c file function is to identify the strobe enable window. Thephylite_dynamic_reconfiguration.c andphylite_dynamic_reconfiguration.h are the library files used byhello_world.c file. The find_strobe_enable_window() function in thehello_world.c performs calibration algorithm as follow:

• Read the initial output strobe phase from ODELAY CSR.

• Configure and update new output strobe phase delay.

• Verify the new output strobe phase delay with test data.

• Sweep across a range of output strobe phase delays to identify valid strobecapture window.

• Find the center output strobe phase from the valid strobe capture window.



You can configure the delay for DQS, DQ[0] and DQ[1] values to achieve betterresults. This reference design, configures only the DQS value.

Related Links

Altera PHYLite for Parallerl Interface IP Core User Guide

1.4 Document Revision History

Table 1. Document Revision History

Date Version Changes

May 2017 2017.05.08 Rebranded as Intel.

January 2016 2016.01.19 Updated reference design file links andsteps to download and install thereference design files.

December 2015 2015.12.11 Initial release.



https://documentation.altera.com/#/link/bhc1410942178562/bhc1410941851660/en-us

AN 747: Implementing PHYLite in Intel® Arria® 10 Devices ... · • Three instances of the Altera...

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