Altera JESD204B IP Core and ADI AD9625 HardwareCheckout Report

2016.06.13

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The Altera® JESD204B IP core is a high-speed point-to-point serial interface intellectual property (IP).

The JESD204B IP core has been hardware-tested with a number of selected JESD204B-compliant ADC(analog-to-digital converter) devices.

This report highlights the interoperability of the JESD204B IP core with the AD9625 converter evaluationmodule (EVM) from Analog Devices Inc. (ADI). The following sections describe the hardware checkoutmethodology and test results.

Related Information

• JESD204B IP Core User Guide• ADI AD9625 Datasheet

Hardware RequirementsThe hardware checkout test requires the following hardware and software tools:

• Stratix V Advanced Systems Development Kit with 15 V power adaptor• Arria 10 GX FPGA Development Kit• ADI AD9625 EVM• Mini-USB cable• Clock source card capable of generating device clock frequencies

Hardware Setup for Stratix V Advanced Systems Development KitA Stratix V Advanced Systems Development Kit is used with the ADI AD9625 daughter card moduleattached to the FMC connector of the development board.

• The AD9625 EVM derives power through the development kit FMC connector.• The ADC device clock is supplied by external clock source card through the SMA connector on the

AD9625 EVM.• The AD9625 divides the sampling clock by four and supplies this divided clock through its DIVCLK

pins to the FPGA.• For subclass 1, the FPGA generates SYSREF for the JESD204B IP core as well as the AD9625 device.

© 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos aretrademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified astrademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performanceof its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to anyproducts and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of devicespecifications before relying on any published information and before placing orders for products or services.

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Figure 1: Hardware Setup

Stratix V Advanced Systems Development KitADI AD9625 EVM

FPGA 1FPGA 2

2.5 GHzExternal Clock

Transceiver Lanes

Device Clockrx_dev_sync_nsysrefSPIPower

Figure 2: System-Level Block Diagram

ADC

SMA2.5 GHz

jesd204b_ed.svDesign Example

FMC AD9625 EVM

AD9625

4 Wire

3 Wiresysref_out(19.5313 MHz)

rx_dev_sync_n

device_clk (625 MHz)

link_clk (156.25 MHz)

sclk, ss_n[0], miso, mosi

rx_serial_data[7:0](6.25 Gbps) L0 - L7

Qsys System

Avalon-MMInterfaceSignals

global_rst_n

mgmt_clk jesd204b_ed_top.sv Stratix V FPGA #1

SignalTap II

JTAG toAvalon Master

Bridge

Avalon-MMSlave

Translator

PIOJESD204B

MegaCore IPL = 8, M = 1, F =1

SysrefGenerator

ConversionCircuit

SPI Slave

Clock andSync

The system-level block diagram shows how the different modules connect in this design. In the setupdepicted above, LMF=811 and the data rate of transceiver lanes is 6.25 Gbps. An external clock sourcecard provides 2.5 GHz sampling clock to the AD9625 device and the ADC supplies 625 MHz FPGAdevice clock through its DIVCLK pin.

Related InformationJESD204B IP Core and AD9625 Configurations on page 11For more information about other configurations.

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Hardware Setup for Arria 10 GX FPGA Development KitFigure 3: Hardware Setup

An Arria 10 FPGA Development Kit is used with the ADI AD9625 daughter card module attached to theFMC connector on the development board.

• The AD9625 EVM derives power from the Arria 10 FMC connector.• Both the FPGA and ADC device clock must be sourced from the same clock source card with two

different frequencies, one for the FPGA and one for ADC.• An internal on-board oscillator present on the AD9625 EVM provides 2.5 GHz device clock to the

ADC.• The AD9625 divides the sampling clock by four (625 MHz) and supplies this divided clock through its

DIVCLK pins to the FPGA.• For subclass 1, the FPGA generates SYSREF for the JESD204B IP core as well as the AD9625 device.

Arria 10 GX FPGA Development Kit

ADI AD9625 EVM

SYNC_N SYSREFFPGA Device Clock

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Figure 4: System Diagram

The system-level diagram shows how the different modules connect in this design.

In this setup, where LMF=811, the data rate of the transceiver lanes is 6.25 Gbps. An on-board internalclock oscillator on the EVM board provides 2.5 GHz sampling clock to the ADC and divides the 2.5 GHzdevice clock by four to provide the clock (625 MHz) to the FPGA.

Sysref(19.5313 MHz) Sysref (19.5313 MHz)

AD9625

4 Wire 3 Wire

rx_dev_sync_n

device_clk(62.5 MHz)

Arria 10 GX FPGA Development Kit AD9625 Evaluation ModuleFMC

rx_serial_data[7:0](6.25 Gbps)

sclk, ss_n[0], miso, mosi

mgmt_clk

100 MHzjesd204b_ed_top.sv

jesd204b_ed.sv

Design Example

JESD204B IP Core

(Duplex)L=8, M=1, F=1

Avalon-MMInterface

signals

global_rst_n

frame_clk (156.25 MHz)

link_clk (156.25 MHz)

ADCAvalon-MM Slave

Translator

Qsys System

JTAG to AvalonMaster Bridge

PIO

SignalTap IIL0 – L7

Sysref Generator

PLL

SPISlave

device_clk2.5 GHz

ConversionCircuit

Oscillator

Hardware Checkout MethodologyThe following section describes the test objectives, procedure, and the passing criteria. The test covers thefollowing areas:

• Receiver data link layer• Receiver transport layer• Descrambling• Deterministic latency (Subclass 1)

Receiver Data Link LayerThis test area covers the test cases for code group synchronization (CGS) and initial frame and lanesynchronization.

On link start-up, the receiver issues a synchronization request and the transmitter transmits /K/ (K28.5)characters. The SignalTap II Logic Analyzer tool monitors the receiver data link layer operation.

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Code Group Synchronization (CGS)

Table 1: CGS Test Cases

Test Case Objective Description Passing Criteria

CGS.1 Check whethersync request isdeasserted aftercorrect receptionof foursuccessive /K/characters.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

• jesd204_rx_pcs_data[(L*32)-

1:0]

• jesd204_rx_pcs_data_valid[L-

1:0]

• jesd204_rx_pcs_kchar_

data[(L*4)-1:0] (1)

The following signals in <ip_variant_name>.v are tapped:

• rx_dev_sync_n

• jesd204_rx_int

The rxlink_clk is used as theSignalTap II sampling clock.

Each lane is represented by 32-bit databus in jesd204_rx_pcs_data signal.The 32-bit data bus is divided into 4octets.

• /K/ character or K28.5 (0xBC)is observed at each octet of thejesd204_rx_pcs_data bus.

• The jesd204_rx_pcs_data_valid signal is asserted toindicate data from the PCS isvalid.

• The jesd204_rx_pcs_kchar_data signal is assertedwhenever control characterslike /K/, /R/, /Q/ or /A/characters are observed.

• The rx_dev_sync_n signal isde-asserted after correctreception of at least foursuccessive /K/ characters.

• The jesd204_rx_int signal isdeasserted if there is no error.

CGS.2 Check full CGS atthe receiver aftercorrect receptionof another four8B/10Bcharacters.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

• jesd204_rx_pcs_

errdetect[(L*4)-1:0]

• jesd204_rx_pcs_disperr[(L*4)

-1:0] (1)

The following signal in <ip_variant_name>.v are tapped:

• jesd204_rx_int

The rxlink_clk is used as theSignalTap II sampling clock.

The jesd204_rx_pcs_errdetect,jesd204_rx_pcs_disperr, andjesd204_rx_int signals shouldnot be asserted during CGS phase.

(1) L indicates the number of lanes.

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Initial Frame and Lane Synchronization

Table 2: Initial Frame and Lane Synchronization Test Cases

Test Case Objective Description Passing Criteria

ILA.1 Check whetherthe initial framesynchronizationstate machineenters FS_DATAstate uponreceiving non /K/characters.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

• jesd204_rx_pcs_data[(L*32)-

1:0]

• jesd204_rx_pcs_data_valid[L-

1:0]

• jesd204_rx_pcs_kchar_

data[(L*4)-1:0] (2)

The following signals in <ip_variant_name>.v are tapped:

• rx_dev_sync_n

• jesd204_rx_int

The rxlink_clk is used as theSignalTap II sampling clock.

Each lane is represented by 32-bit databus in jesd204_rx_pcs_data. The32-bit data bus is divided into 4 octets.

• /R/ character or K28.0 (0x1C) isobserved after /K/ character atthe jesd204_rx_pcs_data bus.

• The jesd204_rx_pcs_data_valid signal must be assertedto indicate that data from thePCS is valid.

• The rx_dev_sync_n andjesd204_rx_int signals aredeasserted.

• Each multiframe in ILAS phaseends with /A/ character orK28.3 (0x7C).

• The jesd204_rx_pcs_kchar_data signal is assertedwhenever control characterslike /K/, /R/, /Q/ or /A/characters are observed.

(2) L indicates the number of lanes.

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Test Case Objective Description Passing Criteria

ILA.2 Check theJESD204Bconfigurationparameters fromADC in secondmultiframe.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

• jesd204_rx_pcs_data[(L*32)-

1:0]

• jesd204_rx_pcs_data_valid[L-

1:0] (2)

The following signal in <ip_variant_name>.v is tapped:

• jesd204_rx_int

The rxlink_clk is used as theSignalTap II sampling clock.

The system console accesses thefollowing registers:

• ilas_octet0• ilas_octet1• ilas_octet2• ilas_octet3

The content of 14 configuration octetsin the second multiframe is stored inthese 32-bit registers—ilas_octet0,ilas_octet1, ilas_octet2, and ilas_octet3.

• /R/ character is followed by /Q/character or K28.4 (0x9C) atthe beginning of secondmultiframe.

• The jesd204_rx_int signal isdeasserted if there is no error.

• Octets 0–13 read from theseregisters match with theJESD204B parameters in eachtest setup.

ILA.3 Check the lanealignment

The following signals in <ip_variant_name>_inst_phy.v are tapped:

• jesd204_rx_pcs_data[(L*32)-

1:0]

• jesd204_rx_pcs_data_valid[L-

1:0] (2)

The following signals in <ip_variant_name>.v are tapped:

• rx_somf[3:0]• dev_lane_aligned• jesd204_rx_int

The rxlink_clk is used as theSignalTap II sampling clock.

• The dev_lane_aligned signalis asserted upon the last /A/character of the ILAS isreceived, which is followed bythe first data octet.

• The rx_somf signal marks thestart of multiframe in user dataphase.

• The jesd204_rx_int signal isdeasserted if there is no error.

Receiver Transport LayerThe ADC is configured to output ramp or PRBS-23 test data pattern to check the data integrity of thepayload data stream through the RX JESD204B IP core and transport layer. The ADC is also set to operatewith the same configuration as in the JESD204B IP core. The ramp or PRBS checker in the FPGA fabricchecks the data integrity for one minute.

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Figure 5: Data Integrity Check Using Ramp or PRBS Checker

This figure shows the conceptual test setup for data integrity checking.

TX TransportLayer

TX PHY and Link Layer

Ramp/PRBSChecker

RX TransportLayer

RX JESD204B IP Core

PHY and Link Layer

ADC

FPGA

Ramp/PRBSGenerator

The SignalTap II Logic Analyzer tool monitors the operation of the RX transport layer.

Table 3: Transport Layer Test Case

Test Case Objective Description Passing Criteria

TL.1 Check thetransport layermapping usingramp test patternor PRBS-23 testpattern.

The following signal in altera_jesd204_transport_rx_top.sv aretapped:

• jesd204_rx_data_valid

The following signals in jesd204b_ed.sv are tapped:

• data_error

• jesd204_rx_int

The rxframe_clk is used as theSignalTap II sampling clock.

The data_error signal indicates apass or fail for the ramp checker.

• The jesd204_rx_data_validsignal is asserted.

• The data_error and jesd204_rx_int signals are deasserted.

Related InformationJESD204B IP Core and AD9625 Configurations on page 11For more information about the test data pattern settings.

DescramblingThe ramp or PRBS checker at the RX transport layer checks the data integrity of the descrambler. TheSignalTap II Logic Analyzer tool monitors the operation of the RX transport layer.

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Table 4: Descrambler Test Case

Test Case Objective Description Passing Criteria

SCR.1 Check thefunctionality ofthe descramblerusing ramp test orPRBS-23 testpattern.

Enable scrambler at the ADC anddescrambler at the RX JESD204B IPcore.

The signals that are tapped in this testcase are similar to test case TL.1

• The jesd204_rx_data_validsignal is asserted.

• The data_error and jesd204_rx_int signals are deasserted.

Deterministic Latency (Subclass 1)Figure below shows the block diagram of deterministic latency test setup. A SYSREF generator provides aperiodic SYSREF pulse for both the AD9625 and JESD204B IP core. The SYSREF generator is running inlink clock domain and the period of SYSREF pulse is configured to the desired multiframe size. TheSYSREF pulse restarts the LMF counter and realigns it to the LMFC boundary.

Figure 6: Deterministic Latency Test Setup Block Diagram for Stratix V FPGA

ADC

SMA2.5 GHz

jesd204b_ed.svDesign Example

FMC AD9625 EVM

AD9625

4 Wire

3 Wiresysref_out(19.5313 MHz)

rx_dev_sync_n

device_clk (625 MHz)

link_clk (156.25 MHz)

sclk, ss_n[0], miso, mosi

rx_serial_data[7:0](6.25 Gbps) L0 - L7

Qsys System

Avalon-MMInterfaceSignals

global_rst_n

mgmt_clk jesd204b_ed_top.sv Stratix V FPGA #1

SignalTap II

JTAG toAvalon Master

Bridge

Avalon-MMSlave

Translator

PIO

JESD204BMegaCore IP

L = 8, M = 1, F =1

SysrefGenerator

ConversionCircuit

SPI Slave

Clock andSync

DeterministicLatency

Measurement

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Figure 7: Deterministic Latency Test Setup Block Diagram for Arria 10 GX FPGA

Sysref(19.5313 MHz) Sysref (19.5313 MHz)

AD9625

4 Wire 3 Wire

rx_dev_sync_n

device_clk(62.5 MHz)

Arria 10 GX FPGA Development Kit AD9625 Evaluation ModuleFMC

rx_serial_data[7:0](6.25 Gbps)

sclk, ss_n[0], miso, mosi

mgmt_clk

100 MHzjesd204b_ed_top.sv

jesd204b_ed.sv

Design Example

JESD204B IP Core

(Duplex)L=8, M=1, F=1

Avalon-MMInterface

signals

global_rst_n

frame_clk (156.25 MHz)

link_clk (156.25 MHz)

ADCAvalon-MM Slave

Translator

Qsys System

JTAG to AvalonMaster Bridge

PIO

SignalTap II

L0 – L7

Sysref Generator

PLL

SPISlave

device_clk2.5 GHz

ConversionCircuit

DeterministicLatency

Measurement

Oscillator

Figure 8: Deterministic Latency Measurement Timing Diagram

USER_DATAILAS

n - 1 n1 2 3

Link Clock

State

SYNC~

RX Valid

Link Clock Count

With the setup above, three test cases were defined to prove deterministic latency. By default, theJESD204B IP core does a single SYSREF detection. The SYSREF single-shot mode is enabled on theAD9625 for this deterministic latency measurement.

Table 5: Deterministic Latency Test Cases

Test Case Objective Description Passing Criteria

DL.1 Check the FPGASYSREF singledetection.

Check that the FPGA detects the firstrising edge of SYSREF pulse.

Read the status of sysref_singledet(bit[2]) identifier in syncn_sysref_ctrlregister at address 0x54.

The value of sysref_singledetidentifier should be zero.

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Test Case Objective Description Passing Criteria

DL.2 Check theSYSREF capture.

Check that the FPGA and ADCcapture SYSREF correctly and restartthe LMF counter for every reset andpower cycle.

Read the value of rbd_count(bit[10:3]) identifier in rx_status0register at address 0x80.

If the SYSREF is captured correctlyand the LMF counter restarts, forevery reset and power cycle, therbd_count value should only varyby two integers due to the wordalignment.

DL.3 Check the latencyfrom start ofSYNC~ deasser‐tion to first userdata output.

Check that the latency is fixed forevery FPGA and ADC reset andpower cycle.

Record the number of link clockscount from the start of SYNC~deassertion to the first user dataoutput, which is the assertion ofjesd204_rx_link_valid signal. Thedeterministic latency measurementblock in Figure 6 has a counter tomeasure the link clock count.

Consistent latency from the startof SYNC~ deassertion to theassertion of jesd204_rx_link_valid signal.

JESD204B IP Core and AD9625 ConfigurationsThe JESD204B IP core parameters (L, M and F) in this hardware checkout are natively supported by theAD9625 device. The transceiver data rate, sampling clock frequency, and other JESD204B parameterscomply with the AD9625 operating conditions.

The hardware checkout test implements the JESD204B IP core with the following parameter configura‐tion.

Stratix V FPGA

Table 6: Parameter Settings for Stratix V FPGA

Configuration Setting

LMF 118 214 412 611 811

HD 0 0 0 1 1

S 4 4 4 4 4

N 16 (3) 12 12 12 12

(3) This 16-bit test pattern is an output from the JESD204X test pattern block in the AD9625 device.

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Configuration Setting

N’ 16 16 16 12 16

CS 0 0 0 0 0

CF 0 0 0 0 0

ADC Device Clock (MHz) 2500 625 1250 2500 2500

ADC Sampling Clock (MHz) 156.25 625 1250 2500 2500

FPGA Device Clock (MHz) (4) 625 156.25 312.5 625 625

FPGA Management Clock(MHz)

100 100 100 100 100

FPGA Frame Clock (MHz) (5) 78.125 156.25 312.5 156.25 156.25

FPGA Link Clock (MHz) (5) 156.25 156.25 156.25 156.25 156.25

Character Replacement Enabled Enabled Enabled Enabled Enabled

Data Pattern Ramp Ramp Ramp Ramp Ramp

Arria 10 GX FPGA

Table 7: Parameter Settings for Arria 10 GX FPGA

Configuration Setting

LMF 118 214 412 611 811

HD 0 0 0 1 1

S 4 4 4 4 4

N 16 (6) 16 (6) 16 (6) 12 12

N’ 16 16 16 12 16

CS 0 0 0 0 0

CF 0 0 0 0 0

(4) The device clock is used to clock the transceiver.(5) The frame clock and link clock is derived from the device clock using an internal PLL.(6) This 16-bit test pattern is an output from the JESD204X test pattern block in the AD9625 device.

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Configuration Setting

ADC Sampling Clock (MHz) 2500 2500 2500 2500 2500

FPGA Device Clock (MHz) (7) 625 625 625 625 625

FPGA Management Clock(MHz)

100 100 100 100 100

FPGA Frame Clock (MHz) (5) 78.125 156.25 312.5 156.25 156.25

FPGA Link Clock (MHz) (5) 156.25 156.25 156.25 156.25 156.25

Lane Rate (Gbps) 6.25 6.25 6.25 6.25 6.25

Character Replacement Enabled Enabled Enabled Enabled Enabled

Data Pattern (8) PRBS-23

Ramp

PRBS-23

Ramp

PRBS-23

Ramp

PRBS-23

Ramp

PRBS-23

Ramp

Test ResultsThe following table contains the possible results and their definition.

Table 8: Results Definition

Result Definition

PASS The Device Under Test (DUT) was observed to exhibit conformant behavior.

PASS with comments The DUT was observed to exhibit conformant behavior. However, an additionalexplanation of the situation is included, such as due to time limitations only aportion of the testing was performed.

FAIL The DUT was observed to exhibit non-conformant behavior.

Warning The DUT was observed to exhibit behavior that is not recommended.

Refer to comments From the observations, a valid pass or fail could not be determined. Anadditional explanation of the situation is included.

Stratix V FPGA

The following table shows the results for test cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1with different values of L, M, F, K, subclass, data rate, sampling clock and link clock frequencies.

(7) The device clock is used to clock the transceiver.(8) The ramp pattern is for deterministic latency measurement test cases DL.1, DL.2, DL.3 only.

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Table 9: Results for Test Cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1 (Stratix V FPGA)

Setnumber

L M F Subclass SCR K Data rate(Mbps)

ADCSampling

Clock(MHz)

FPGALink

Clock(MHz)

Result

1 1 1 8 0 0 16 6250 156.25 156.25 Pass

2 1 1 8 0 1 16 6250 156.25 156.25 Pass

3 1 1 8 0 0 32 6250 156.25 156.25 Pass

4 1 1 8 0 1 32 6250 156.25 156.25 Pass

5 1 1 8 1 0 16 6250 156.25 156.25 Pass

6 1 1 8 1 1 16 6250 156.25 156.25 Pass

7 1 1 8 1 0 32 6250 156.25 156.25 Pass

8 1 1 8 1 1 32 6250 156.25 156.25 Pass

9 2 1 4 0 0 16 6250 625 156.25 Pass

10 2 1 4 0 1 16 6250 625 156.25 Pass

11 2 1 4 0 0 32 6250 625 156.25 Pass

12 2 1 4 0 1 32 6250 625 156.25 Pass

13 2 1 4 1 0 16 6250 625 156.25 Pass

14 2 1 4 1 1 16 6250 625 156.25 Pass

15 2 1 4 1 0 32 6250 625 156.25 Pass

16 2 1 4 1 1 32 6250 625 156.25 Pass

17 4 1 2 0 0 16 6250 1250 156.25 Pass

18 4 1 2 0 1 16 6250 1250 156.25 Pass

19 4 1 2 0 0 32 6250 1250 156.25 Pass

20 4 1 2 0 1 32 6250 1250 156.25 Pass

21 4 1 2 1 0 16 6250 1250 156.25 Pass

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Setnumber

L M F Subclass SCR K Data rate(Mbps)

ADCSampling

Clock(MHz)

FPGALink

Clock(MHz)

Result

22 4 1 2 1 1 16 6250 1250 156.25 Pass

23 4 1 2 1 0 32 6250 1250 156.25 Pass

24 4 1 2 1 1 32 6250 1250 156.25 Pass

25 6 1 1 0 0 20 6250 2500 156.25 Pass withcomments

26 6 1 1 0 1 20 6250 2500 156.25 Pass withcomments

27 6 1 1 0 0 32 6250 2500 156.25 Pass withcomments

28 6 1 1 0 1 32 6250 2500 156.25 Pass withcomments

29 6 1 1 1 0 20 6250 2500 156.25 Pass withcomments

30 6 1 1 1 1 20 6250 2500 156.25 Pass withcomments

31 6 1 1 1 0 32 6250 2500 156.25 Pass withcomments

32 6 1 1 1 1 32 6250 2500 156.25 Pass withcomments

33 8 1 1 0 0 20 6250 2500 156.25 Pass

34 8 1 1 0 1 20 6250 2500 156.25 Pass

35 8 1 1 0 0 32 6250 2500 156.25 Pass

36 8 1 1 0 1 32 6250 2500 156.25 Pass

37 8 1 1 1 0 20 6250 2500 156.25 Pass

38 8 1 1 1 1 20 6250 2500 156.25 Pass

39 8 1 1 1 0 32 6250 2500 156.25 Pass

40 8 1 1 1 1 32 6250 2500 156.25 Pass

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Table 10: Results For Deterministic Latency Test (Stratix V FPGA)

Test L M F Subclass K Data rate(Mbps)

ADCSampling

Clock(MHz)

FPGA LinkClock(MHz)

Result

DL.1 1 1 8 1 32 6250 312.5 156.25 Pass

DL.2 1 1 8 1 32 6250 312.5 156.25 Pass

DL.3 1 1 8 1 32 6250 312.5 156.25 Pass withcomments.

Link clockobserved = 323

DL.1 2 1 4 1 32 6250 625 156.25 Pass

DL.2 2 1 4 1 32 6250 625 156.25 Pass

DL.3 2 1 4 1 32 6250 625 156.25 Pass withcomments.

Link clockobserved = 163with FPGALMFC offset =0x1C at IP coreregister 0x54.

DL.1 4 1 2 1 32 6250 1250 156.25 Pass

DL.2 4 1 2 1 32 6250 1250 156.25 Pass

DL.3 4 1 2 1 32 6250 1250 156.25 Pass withcomments.

Link clockobserved = 99-100 with ADCLMFC offsetregister set to0x14.

DL.1 6 1 1 1 32 6250 2500 156.25 Pass

DL.2 6 1 1 1 32 6250 2500 156.25 Pass

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Test L M F Subclass K Data rate(Mbps)

ADCSampling

Clock(MHz)

FPGA LinkClock(MHz)

Result

DL.3 6 1 1 1 32 6250 2500 156.25 Pass withcomments.

Link clockobserved = 67with ADCLMFC offsetregister set to0x02.

DL.1 8 1 1 1 32 6250 2500 156.25 Pass

DL.2 8 1 1 1 32 6250 2500 156.25 Pass

DL.3 8 1 1 1 32 6250 2500 156.25 Pass withcomments.

Link clockobserved = 67with ADCLMFC offsetregister set to0x02.

The following figure shows the SignalTap II waveform of the clock count from the deassertion of SYNC~to the assertion of the jesd204_rx_link_valid signal, the first output of the ramp test pattern (DL.3 testcase). The clock count measures the first user data output latency.

Figure 9: Deterministic Latency Measurement Ramp Test Pattern Diagram (Stratix V FPGA)

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Arria 10 GX FPGA

The following table shows the results for test cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1with different values of L, M, F, K, subclass, data rate, sampling clock,link clock, and SYSREF frequencies.

Table 11: Results for Test Cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1 (Arria 10 GX FPGA)

Test L M F Subclass SCR K DataRate

(Gbps)

SamplingClock(GHz)

LinkClock(MHz)

Result

1 1 1 8 1 0 16 6.25 2.5 156.25 PASS2 1 1 8 1 1 16 6.25 2.5 156.25 PASS3 1 1 8 1 0 32 6.25 2.5 156.25 PASS4 1 1 8 1 1 32 6.25 2.5 156.25 PASS5 2 1 4 1 0 16 6.25 2.5 156.25 PASS6 2 1 4 1 1 16 6.25 2.5 156.25 PASS7 2 1 4 1 0 32 6.25 2.5 156.25 PASS8 2 1 4 1 1 32 6.25 2.5 156.25 PASS9 4 1 2 1 0 16 6.25 2.5 156.25 PASS10 4 1 2 1 1 16 6.25 2.5 156.25 PASS11 4 1 2 1 0 32 6.25 2.5 156.25 PASS12 4 1 2 1 1 32 6.25 2.5 156.25 PASS13 6 1 1 1 0 20 6.25 2.5 156.25 PASS with

comments14 6 1 1 1 1 20 6.25 2.5 156.25 PASS with

comments15 6 1 1 1 0 32 6.25 2.5 156.25 PASS with

comments16 6 1 1 1 1 32 6.25 2.5 156.25 PASS with

comments17 8 1 1 1 0 20 6.25 2.5 156.25 PASS18 8 1 1 1 1 20 6.25 2.5 156.25 PASS19 8 1 1 1 0 32 6.25 2.5 156.25 PASS20 8 1 1 1 1 32 6.25 2.5 156.25 PASS

The following table lists the results for test cases DL.1, DL.2, DL.3 with different values of L, M, F, K,subclass, data rate, sampling clock, link clock, and SYSREF frequencies

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Table 12: Results for Deterministic Latency Test (Arria 10 GX FPGA)

Test L M F Subclass K Data Rate(Gbps)

SamplingClock(GHz)

Link Clock(MHz)

Result

DL.1 1 1 8 1 32 6.25 2.5 156.25 PASSDL.2 1 1 8 1 32 6.25 2.5 156.25 PASSDL.3 1 1 8 1 32 6.25 2.5 156.25 PASS with

comments.

Link clockobserved = 319with RBD offsetregister set to 5.

DL.1 2 1 4 1 32 6.25 2.5 156.25 PASSDL.2 2 1 4 1 32 6.25 2.5 156.25 PASSDL.3 2 1 4 1 32 6.25 2.5 156.25 PASS with

comments.

Link clockobserved = 187with RBD offsetregister set to 9.

DL.1 4 1 2 1 32 6.25 2.5 156.25 PASSDL.2 4 1 2 1 32 6.25 2.5 156.25 PASSDL.3 4 1 2 1 32 6.25 2.5 156.25 PASS with

comments.

Link clockobserved = 99with ADCLMFC offsetregister set to 0.

DL.1 6 1 1 1 32 6.25 2.5 156.25 PASSDL.2 6 1 1 1 32 6.25 2.5 156.25 PASSDL.3 6 1 1 1 32 6.25 2.5 156.25 PASS with

comments.

Link clockobserved = 67with ADCLMFC offsetregister set to 0.

DL.1 8 1 1 1 32 6.25 2.5 156.25 PASSDL.2 8 1 1 1 32 6.25 2.5 156.25 PASS

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Test L M F Subclass K Data Rate(Gbps)

SamplingClock(GHz)

Link Clock(MHz)

Result

DL.3 8 1 1 1 32 6.25 2.5 156.25 PASS withcomments.

Link clockobserved = 67with ADCLMFC offsetregister set to 0.

The following figure shows the SignalTap II waveform of the clock count from the deassertion of SYNC~to the assertion of the jesd204_rx_link_valid signal, the first output of the ramp test pattern (DL.3 testcase). The clock count measures the first user data output latency.

Figure 10: Deterministic Latency Measurement Ramp Test Pattern Diagram (Arria 10 GX FPGA)

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Test Result CommentsIn each test case, the RX JESD204B IP core successfully initialize from CGS phase, ILA phase, and untiluser data phase. Except for LMF=611 test cases, no data integrity issue is observed by the ramp checkerand PRBS checker. For LMF=611 test cases, no data integrity check is performed because Altera transportlayer does not support N'=12 configuration.

In deterministic measurement test case DL.3, the link clock count in the FPGA depends on board layoutand the LMFC offset value set in the ADC register. The link clock count varies by only one link clockwhen the FPGA and ADC are reset or power cycled. The link clock variation in the deterministic latencymeasurement is caused by word alignment, where control characters fall into the next cycle of data sometime after realignment. This makes the duration of ILAS phase longer by one link clock some time afterreset or power cycle. For LMF=214 and LMF=118 test cases, the LMFC or RBD offset value is tuned at theFPGA IP core instead of at the ADC for consistent latency.

AN 712 Document Revision HistoryDate Version Changes

June 2016 2016.06.13 • Added Arria 10 FPGA hardware setup and test results.• Updated the Deterministic Latency Measurement Ramp

Test Pattern Diagram for Stratix V FPGA.• Split the test results section to Stratix V and Arria 10 GX

FPGA.

October 2014 2014.10.13 Initial release.

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