amstl ws 5.1.1.0 - iczhiku.com

AMS Methodology Kit Version 5.1.1.0

AMS Top-Level Simulation Flow Workshop 5.1.1.0 Software BOM

IC5141_USR3 IUS57 FCS

ASSURA 3.1.4_5141_USR2

AMS Methodology Kit

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Cadence AMS Methodology Kit The flow workshop you are about to take is a component of the Cadence AMS Methodology Kit. The Cadence AMS Methodology Kit is a complete front-to-back reference example that can be used to better understand a comprehensive “Advanced Custom Design Methodology”, which you can leverage for techniques and methods to apply to your own design. The Kit is composed of three primary design flows, all of which are demonstrated on the same reference design, interact and work together for a complete front-to-back solution. These include top-level simulation and analysis – “AMS Top-level Flow”, top-level physical design – “Analog Driven Physical Implementation”, and block creation – “AMS Block Creation with Migration and Reuse”.

The Reference Design used is a 10/100 Ethernet Phy, which contains approximately 30K analog transistors and 60K digital gates. The “AMS Top-level Flow” walks through the creation of a top-level simulation strategy, relying on mixed-level techniques. This includes a strategy to take advantage of parasitics throughout the design process. In addition, the methodology to manage multiple power supplies through the use of inherited connections is demonstrated. The “Analog Driven Physical Implementation Flow” provides an example of top-level physical design digital implementation of a standard cells based block – along with its subsequent integration with the “analog-driven” design. The “AMS Block Creation Flow with Migration and Reuse” provides a front-to-back example of a Sample and Hold block which is part of a larger 6-bit ADC circuit. This includes methodologies for both initial block creation and subsequent migration and reuse. Migration and reuse are demonstrated using two methods:

AMS Top-level Flow

Analog-Driven Physical

Implementation Flow

AMS Block Create w/ Reuse

Flow

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♦ starting with layout migration ♦ starting with a more automated circuit sizing and layout synthesis approach

In addition to this workshop example, the Cadence AMS Methodology Kit also contains migration and reuse examples of the full 6-bit Flash ADC circuit - a bigger, more hierarchical block. Further information, including flow and methodology whitepapers and datasheets are available at http://www.cadence.com/products/Kits/ams/index.aspx. The Cadence AMS Methodology Kit (including this workshop data) is available for distribution through your account manager, and consists of:

♦ The Ethernet PHY reference design (transistors, layouts, schematics, behavioral models and more)

♦ (3) design flows explained above, complete with step-by-step documentation, simulation plans and associated examples

♦ 6-bit Flash ADC example for reuse and migration ♦ 90 nm generic process design kit ♦ 5 days Applicability Consulting, where AMS experts will help map the

methodology and techniques to your design. Enjoy your flow workshop!

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Overview AMS Top-Level Simulation Flow Workshop Version 5.1.1.0 Welcome to the AMS Top-Level Simulation Flow Workshop. The Virtuoso AMS Top-Level Simulation Flow is the solution for top-level mixed-signal chip level verification. It provides for both top down and bottom up verification methodologies to help customers verify chip level designs in each of the design stages, from architectural level through silicon. Based on the Advanced Customer Design Methodology, (http://www.cadence.com/whitepapers/Virtuoso_methodlogyWP.pdf) This flow relies on the “meet in the middle” approach providing simultaneous implementations of top down and bottom up capabilities. It allows for a continuous evolutionary approach where the top level can be consistently validated against continuous updates of block level data as they become available. At any given point in time, the top-level simulation suite can predict issues within block level data regardless whether the formats used are behavioral models, transistors level descriptions, or calibrated models. We will be demonstrating the following capabilities:

• Top-down and bottom-up mixed-signal SOC design methodology • Highly configurable designs using the Hierarchy Editor • ADE simulation and debugging Environment for mixed signal • How to improve Verilog-AMS behavior module • Solution for design with multiple power supplies • Parasitic early estimation and verification on critical nets • Top level parasitics verification with digital SDF backannotation

The AMS Top-Level Flow is the front-end integration level piece of the AMS methodology Kits. As such, it relies on inputs from the other AMS methodology Kits including: ADPI -- Analog-Driven Physical Implementation AMS block level design and IP re-use We will use these inputs in a top-level context. The figure below shows the flow diagram.

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The key pieces that this flow relies on are block level descriptions (transistor level and calibrated behavioral models) from the AMS block creation flow, RFIC content (if applicable) from the RFIC flow, and top-level parasitics from the ADPI flow. With these inputs, as they are created through the design process, a simulation strategy that most effectively uses this collateral at the earliest moments in the design process can be created. Optionally, this flow can use system design collateral to extend the mixed level capabilities – this is available through the Virtuoso System/IC flow. The other flows (block creation, RFIC) primarily rely on the top down behavioral models created during this design process, and are passed down to the other flows for use in that context. The other flows pass back the bottom-up descriptions for the circuit blocks. This workshop will demonstrate how the AMS top-level flow can be used to setup, simulate and observe results from multiple configurations of the Ethernet Phy design. This design contains approximately 30K analog transistors and 100K digital gates and is highly dependent on the mixed signal contents. It is very difficult to run simulations that handle the analog and digital sections separately, making this an excellent case to determine a simulation strategy from architecture through post-layout verification from a top-level perspective. The workshop will proceed through 9 sections:

Section 1: Introduction of Ether Phy Design Section 2: Developing a top-level simulation plan Section 3: Dealing with multiple power supplies Section 4: High level behavior simulation and behavior model improvement.

Simulation Strategy Dev

VSDE (ADE)

HDL Sim AMS Designer

Mixed Level Simulation AMS Designer

System Level IP From System/IC Flow

Transistor Level Block Descriptions From AMS Block Creation Flow

Calibrated HDL Models From AMS Block Creation Flow

RFIC Content From RFIC Flow

To AMS Block Creation Flow To RFIC Flow

RC Parasitics From ADPI flow

Spectre Ultrasim NC

Hierarchy Editor

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Section 5: Low-level behavior simulation and simulation debugging methods. Section 6: IP reuse - Mixed behavior and Calibrated table model SPICE netlist integration for mixed-signal verification Section 7: Parasitic early estimation/simulation on critical nets Section 8: Mixed behavior and verilog gate level simulation with SDF Section 9: Mixed behavior and Transistor schematic

Section 10: Full analog transistors with behavior DSP core Section 11: Top-level parasites with DSP gates and SDF backannotation

Section 1: Introduction of Ether Phy Design Before we start this workshop, we will first do some initial setup: Action1.1: Open workshop database: gtar –zxvf amstl_flow_workshop_5.1.1.0.tgz Action1.2: source amskit_setup.csh Action1.3: cd ./amstl_flow_workshop/workarea Action1.4: run script “compile.cmd” Compile connect rules/modules Compile cds_alias module from basic library Action1.5: Invoke tool icfb CIW window appears...

Action1.8: In CIW, open Tools -> LibManager

Library Manager Window appears…

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In this workshop, we are going to use the top-level design with different configurations The name of top-level design is: “ether_sims:top_sim” (red arrow point to) Action1.9: Open “ether_sim.top_sim:schematic_ams”

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This is ether_sim top-level schematic. This chip is an IEEE802.3u compliant 10/100Base Ethernet Phy design. It supports both 10Base-T and 100Base-TX applications. The MII data and management interface between Ethernet PHY and Ethernet MAC is also integrated. The design utilizes 90nm Cadence generic design kits. In this workshop, we are going to verify the Ether Phy in 100Base mode. The internal clock frequency is 125MHZ instead of 100MHZ. This compensates for the overhead caused by 4B/5B encoding in 100Base mode. Standard MII mode Data Flow

The self-contained top-level test bench used in the workshop will automatically verify the simulation results. However, we will pick up the resulting signal from the final stage of the dataflow (as indicated by the red arrow above) and bring it up in the waveform display. There are three blocks in this level. The block in the upper side is a Verilog digital test bench. It is also a self-contained providing the self-checking capability of digital signal simulation results. The middle block is an analog and mixed-signal top-level DUT. We will discuss further details in the next section. The bottom block is the transmission line providing the loop back between the transmitter and receiver. Note: There are two supplies 1.0V and 2.5V in this design. Action 1.10: Descend down to DUT sub level schematic In top-level schematic window, select DUT (instance I0) Design -> Hierarchy -> Descend Read

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This is the top-level DUT. It essentially consists of six major blocks: DSP block instance I45 Pure digital RTL X-mit block instance I46 analog/mixed Receive block instance I44 analog/mixed Top_common block containing the PLLs instance I22 analog/mixed BIAS block instance I36 analog/mixed Analog Control Block instance I42 analog/mixed All are driven by our test bench/stimulus, the MII bus, which is captured as an RTL block and emulates the handshake mode.

Section 2: Developing a Top-Level Simulation Plan The most important step in a mixed-signal verification process is developing a top-level simulation plan, to take full advantage of the capabilities available through the AMS methodology Kits. The top-level simulation plan spells out, per simulation run/test bench, the mixed level configurations that will be used. In this workshop example, we will develop a simulation plan for one top-level test of the Ether Phy design containing an analog and digital loop back. We are making the following assumptions:

• We have digital RTL from our digital design team. The RTL block will map to gate level digital standard cells during logic synthesis.

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• We are starting with a full behavioral level simulation, as the blocks have yet to be designed at this stage. These results will be used for comparison as much more accurate results are obtained from the bottom up process.

• We will swap in the transistor level descriptions for one block, the ADC. The ADC is the first block in which we get transistor level schematics.

• Our block designers are using the Virtuoso AMS Block Creation Flow, and thus we delivered design collateral from this flow to be used to exercise the simulation plan. We will run full analog transistors + Digital behavioral verification.

• We have critical interfaces issues between two blocks, top_common and analg_cntl. Our physical design group is using the ADPI Flow and there for has a first cut of top-level route. This allows us to use top-level parasitics between these two blocks as part of our simulation plan. We can verify the top-level parasitics between these two transistor level blocks with the rest of blocks in behavior/transistors level.

• Our block level designers have done all the transistors level implementation for all analog block, so that we can verify all analog transistors level design under the top-level test bench.

• The full parasitics simulation on all analog transistors is somewhat costly in simulation time. We will consider the analog transistors level plus digital behavior plus top-level parasitics as a “final” verification for this reason.

With the scenario outlined above, we can determine a set of configurations to facilitate the verification of this test continuously throughout the design process. Our first simulation will be the top-level behavioral simulation. Here, each block is described in high-level behavioral form to verify the design at the architectural level. Second, our high level behavior is partitioned into the low level behavior. The ports, cell names and hierarchy name exactly match the block level schematics to be implemented. This will be delivered as detail specifications and required result for each of block to the block design team. Third, we address the calibrated model in the PLL design. The calibrated model can be done based on the schematic or extracted layout. It is provided by the characterization team by using the AMS Block Creation Flow. Calibrated model provides great speed and accuracy at transistor level. Forth, our adc_top transistor level block from our block design group is available. We need to verify this transistor level block in the top-level context, with the rest of the design described as behavior.

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Fifth, the top_common and Bias_port blocks are provided from our block design group; this is our scenario where these two blocks have interface issues that need to be verified. We will get the top-level parasitics between these blocks based on the first cut of top-level routing, which has been implemented by layout group, so that we could simulate these two transistor level blocks with early top-level parasitics under the top-level context. This allows us to use these parasitics before all the other blocks are completed at transistor level. The sixth, our digital implementation group accomplished the digital DSP block. The gate level verilog and SDF are ready. We will replace the DSP RTL verilog with DSP gate level verilog plus SDF and simulate in the full mixed-signal chip context. The seventh simulation occurs when the block design team completes the entire transistor level schematic. We want to verify the whole transistors level design with the digital behavior in top-level context. Finally, the top-level layout routing is implemented and checked to be LVS clean. We wish to verify the full transistor schematic with digital verilog gate plus SDF and top-level RC parasitics. The table below summarizes our approach: Simulation Plan Name Test bench DUT (Design Under Test) High level Behavior RTL Verilog High level Behavior verilogams Low level Behavior RTL Verilog Low level behavior verilogams Mixed behavior and calibrated model /SPICE netlist

RTL Verilog Behavior model + PLL calibrated table model / PLL SPICE netlist.

Top level critical nets RTL Verilog Behavior model + top_common schematic + Bias_port + parasitics RC on critical nets in between.

Mixed-behavior with Verilog gate level +SDF

RTL Verilog Analog behavior + DSP verilog gate + SDF backannotation

Mixed behavior and transistor level

RTL Verilog Behavior model + top_adc transistors + DSP verilog RTL

Full analog Transistor RTL Verilog Full transistor schematic netlist + DSP behavior RTL

Top level parasitics RTL Verilog Transistor level schematic + top-level parasitics + DSP gate level verilog block + SDF

We are going to execute this simulation plan in this workshop from section 4 to section 10.

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Section 3: Dealing with Multiple Power Supplies Challenge: Multiple Power Supplies crossing the boundaries of A/D. Multiple Power Supplies are common practice in mixed-signal design. The challenge occurs when different voltage domain nets cross the analog and digital boundary. In such scenario, connect modules need to know whether the logic 1 should be converted to 2.5V or 1V, or if the electrical 1V should be converted to logic 0 or logic 1. In this section, we demonstrate 2 different solutions of dealing with multiple supplies on A/D boundaries. Using simple examples, the two solutions are demonstrated in the next couple of sections. The second example is the implementation used in the Ethernet Phy design. Note: In this workshop final section 11, we will demonstrate Discipline-Based Connect rule solution (Scope-based) for multiple supplies and multiple vth (es) Section 3.1 Simple example of SupplySensitivity + Inherited Connection Setup requirement:

• Add inherited connection and supplySen/groundSen in the digital text module.

• Add supplySen/groundSen attribute in the connect module. • netSet value to be defined in the adjacent digital cell or upper level

hierarchy.

Action 3.1.1: Invoke icms From LibManager open

example_inhcon_supplySen.inhcon_SupplySen:config_ams (open schematic only)

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In this simple example, the clock signal drives 4 different buffer chains The 1st branch (top) The digital block (5V) drives the spice subckt. Once the digital block is implemented in the silicon, the output high voltage should be 5V. In Cadence AMS Designer, the inserted connect module is on the port of digital cell. Digital port A (connect module) ------------net-------------Analog port . The supply voltage in the connect module must align with the netSet value on digital cell instead of analog cell. This makes the digital cell consistent between behavior level and silicon level. The 2nd branch The digital block (3V) drives a second spice block. This is similar to the first branch; the high value of net in between should be 3V. The 3rd branch The digital block (3V) drives a VerilogA (5V) block, which in turn drives a digital block (3V). The signal high value of C1_3V should be 3V and C2_5V should be 5V. The 4th branch The digital block (5V) drives a transistor level schematic (3V) which drives a digital block (5V) that drives a transistor level schematic (3V).

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The signal high value of D1_5V/D2_3V/D3_5V should be 5V/3V/5V respectively. What makes the connect module to be aware of the supply voltages?

1. Inherited connection attribute and SupplySen attributes in the digital cell. 2. SupplySen attribute in connect module.

How does supply value propagate to the connect module in this example? The netSet value overwrites the default inherited connection value in digital cell. -> The inherited connection value passes to the supplySen on digital cell’s port. -> The supplySen value pass to the connect module on digital port

Action 3.1.2: In schematic window, select instance BUF_A1 and descend down to the verilog module

Note: The red arrow points to the SupplySen attribute. The blue arrow points to the inherited connection attribute. Action 3.1.3: View supplySen connect module text files: Open $AMS/../FLOW_ETHER_CDK090/share/connect_lib/E2L_ss.vams $AMS/../ FLOW_ETHER_CDK090/share/connect_lib/LE2_1_ss.vams In the snapshot below: The red arrow indicates the SupplySen attribute in the connect module. The blue arrow indicates where vdd is a parameter, not a fixed value.

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(SupplySen E2L connect module)

(SupplySen L2E connect module) Action 3.1.4: Invoke ADE from schematic In schematic window,

Tools-> Analog Environment; ADE window appears…

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Action 3.1.5: Choose simulator and project directory Setup -> Simulator/Directory … Simulator: ams Project Directory: simulation Action 3.1.6: Load the existing state Sessions->Load state; ADE state form appears… Select state name: state_inhconn_supply and click OK in the form.

(Load state form in ADE) Action 3.1.7: Run AMS simulation In ADE, Simulation-> Netlist and Run Simulation takes about 10 seconds to finish Action 3.1.8: Once simulation done, the wavescan waveform display pops up.

In Wavescan window, Axis-> Turn on “strips”

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Check the simulation results and ensure the results meet our expectation!

Section 3.2 Simple example of AICM + Inherited Connection Setup requirement:

• Add inherited connection attribute in connect module • netSet value to be defined in the upper level design hierarchy

Action 3.2.1: Invoke icms Open “example_inhcon_AICM.AICM_top:config (Open schematic only) Schematic window appears…

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Similar to the example in section 3.1, this case has a clock signal driving four different branches with two supply voltages, 5V and 3V. Action 3.2.2: Examine the instances in schematic window.

Descend down to the instances I30, I29, I28 and I27. 1st Branch: I30 The digital verilog drives a spice subckt. There is no netSet value for hSup on instance I30, so the supply voltage in the connect module will take the default of vdd! =3V. The simulation result of I30.C1_3V should be a 0-3V pulse. 2nd Branch: I27 The digital verilog drives a spice subckt. The netSet value of hSup defined on I27 is vdd2! = 5V. It overwrites the default value in connect module. The simulation result of I27.B1_5V should be a 0-5V pulse. 3rd Branch: I28 The digital verilog drives a verilogA behavioral module generated from DCM, which drives a digital verilog block in the end. There is no netSet value for hSup on instance I28, so the supply voltages in CM will take the default of vdd! = 3V. The simulation result of I28.C1_3V and C2_3V should be a 0-3V pulse. 4th Branch: I29

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The digital verilog drives a transistor level schematic that drives a digital verilog block, which in turn drives a transistor level schematic. The netSet value of hSup defined on I29 is vdd2! = 5V. The simulation result of I29.D1_5V, I29.D2_5V and D3_5V should be a 0-5V pulse. Note: The netExpression in the transistor level schematic, verilogA and connect module are same. Action 3.2.3: View Inherited connection connect module file: $AMS/../FLOW_ETHER_CDK090/share/connect_lib/E2L_sample_inh.vams $AMS/../ FLOW_ETHER_CDK090/share/connect_lib/LE2_1_sample_inh.vams In the snapshot below:

� The red arrow indicates an inherited connection attribute in the connect module. � The blue arrow indicates where vdd is a parameter instead of a fixed value.

(E2L Inherited Connection Connect Module)

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(L2E Inherited Connection Connect module) Supply value propagating flow form this example: The netSet value in upper level hierarchy overwrites the default value of netExpression in connect module. Action 3.2.4: Invoke ADE from schematic window

Tools - > Analog Environment Action 3.2.5: Choose simulator and project dir Setup -> Simulator/Directory … Simulator: ams Project Directory: simulation Action 3.2.6: Load existing state Sessions->Load state; Form appears. Select state name: example_inhcon_AICM Click OK in the form. Action 3.2.7: Check the connect rule setup In ADE window -> Setup -> Connect Rules.

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Action 3.2.8: Run Simulation In ADE window as below, Simulation -> Netlist and Run

Action 3.2.9: Viewing the results

When the simulation completes, the wavescan waveform display pops up. In the Wavescan window, Axis-> Turn on “strips”.

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Section 3.3 Apply AICM + Inherited Connection Solution in Ether Phy design. In this section, we are going to use AICM + Inherited connection solution on the real Ether Phy design. Under certain configurations of the ether_sim.top_sim:config_inhconn, there are multiple supply connect modules needed on the boundaries of D/A. We are going to run a quick simulation (stop time =160n) instead of full simulation (stop time = 30u), to verify if multiple supplies work at the D/A boundary. Similar to section 3.2.2, the connect modules have an inherited connection attribute. The default value is VDD!, the property name is DVDD Like the simple example in section 3.2, the supply voltage in connect module will look for the netSet value of VDD in the upper level hierarchy. Action 3.3.1: Invoke icms

Open “ether_sims.top_sim:config_inhconn” from LibManager, Bring up both schematic and HED window.

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Action3.3.2: In schematic window, descend down to I0.I42

The instance I49 is highlighted in the schematic. Action 3.3.3: In schematic window,

Select I49 and Edit -> Properties, the form pops up You can see the netSet value of DVDD is defined as VDD. VDD connects to the 1V vsource in the top-level schematic.

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Action 3.3.3: In schematic window,

Descend down to I49. Design -> Hierarchy -> Descend Read Sub level schematic window appears.

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Action 3.3.4: View the netSet value on highlighted instance I5 In schematic window, select instance I5 (as indicated by the red arrow) Edit -> Properties -> Objects

In instance I5, the netSet value of DVDD is VDDRX. VDDRX connect to the 2.5V vsource in the top-level schematic. With the neSet defined, the Connect modules under top.I42.I49.I5 will pick up VDDRX as the supply voltage with a value of 2.5V. Additionally, top.I43.I49 (excluding top.I42.I49.I5) will pick up VDD as the supply voltage with a value of 1.0V. Action 3.3.5: In schematic window invoke ADE Tools -> Analog Environment Action 3.3.6: Choose simulator and project dir Setup -> Simulator/Directory … Simulator: ams Project Directory: simulation Action 3.3.7: Load existing state Sessions->Load state; Form appears. Select state name: config_ams_inhconn Click OK in the form

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Action3.3.8: Check the connect rule setup in ADE In ADE window, Setup-> Connect Rules Form appears…

Choose the user defined connect rule “connectLib.mps_inh: connect” via browser and add it. Action 3.2.8: Run Simulation In ADE window, Simulation -> Netlist and Run Action 3.2.9: View simulation result When the simulation completes, the Wavescan window appears. Axis -> Turn on “Strips”

In this design configuration:

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/I0/I42/I49/I5/net15<0> is driven by a logic clock, the supply voltage is 2.5V. /I0/I42/I49/net129 is driven by a logic clock, the supply voltage is 1.0V. The simulation results demonstrate the use of multiple supplies on the boundaries of A/D is correct. Action 3.2.10 Keep CIW and LibManager windows open and close the rest of windows.

Section 4: Behavioral level Simulation This section runs the full behavior level simulation for the analog/mixed-signal loop back test. All of the analog blocks are described using Verilog-AMS. However, they could also be described in VHDL-AMS or mixed languages. This is the first simulation we are running and the result provides a golden reference for the verification of transistor level blocks as they are completed. We will use AMS Designer with the Spectre solver and interactive mode(Simvision) to perform the simulation. Section 4.1 Setup and Run high level behavior Simulation Action 4.1.1: Open Ether Phy behavior level design Invoke icms. In DFII window, Tools-> Library Manager. LibManager Window appears …

In the Library Manager, select Library ether_sims; cell top_sims;

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Double click on View config_ams_beh.

The Open Configuration Window appears…

Select “yes” for both the Configuration and Top Cell view and click OK Hierarchy Editor Window and top-level schematic window appear…

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Action 4.1.2: View top-level verilog test bench.

In schematic window, select the instance tc, a test bench block indicated by the red arrow

Design -> Hierarchy -> Descend Read behavioral view.

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The Verilog RTL test bench is displayed in the X window. Near the end of the test bench, you can see there is a “SPEEDUP” flag, which define the wait time to be 3us instead of 30us.

The SPEEDUP flag will be setup during the NC Compilation stage. Note: In this workshop from section 4 to section 8, SPEEDUP flag will be used. Action 4.1.3: Invoke ADE simulation Environment In the top-level schematic window, Tools -> Analog Environment ADE window appears…

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Action 4.1.4: In ADE window , Choose simulator and project dir Setup -> Simulator/Directory … Simulator: ams Project Directory: simulation Action 4.1.5: In ADE window, Load existing state Sessions->Load state; Form appears. Select state name: config_ams_beh Click OK in the form This procedure completed all setup in ADE. Action 4.1.6: Check the SPEEDUP flag and Micro include directory setup in Compilation

form. In ADE window, Simulation -> Options -> Compile … Compile Options form appears … In the Compile options form:

As indicated by the red arrow, the “-define SPEEDUP” is a compilation option. Simulation is set up to be in the “wait 3us mode” based on the test bench. This demonstrates the flexibility of AMS Designer permitting additional flag(s) in same top-level test bench.

As the blue arrow indicates, the macro include path is defined. This allows the design to find any macro in named directory. Our design uses “myfunction.vams”.

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Action 4.1.7 Check the AMS simulation solver setup In ADE window, Simulation -> Solver …

The Spectre Solver is selected. We are using AMS-Spectre to run the simulation. Action 4.1.8: Check Analysis options In ADE window, Analysis -> Choose You will see: Transient analysis is enabled Stop time = 30u . Note: In this workshop, from section 4 to section 11, the simulation stop time are all set to 30us

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Action 4.1.9 In ADE Window, Simulation -> Run Options .. Ensure the Interactive mode (Debug mode) is on . Action 4.1.10: Check “profile” option in simulation options form In ADE window, Simulation -> Options -> AMS Simulator... AMS Simulation options form appears …

Action 4.1.11: Run simulation In ADE window, Simulation -> Netlist and Run It takes about five minutes to complete the simulation using high level

behavioral modules. Action 4.1.12: Watch waveform display

When AMS complete netlisting/compilation and elaboration, Simvision Environment GUI Appears,

In Simvision Waveform window , Simulation -> Run Watching the simulation waveform marching …

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Once simulation reaches 100%, Zoom into 20us -21us area

Please compare these results to the figure of “Ethernet Phy standard MII mode data flow” in section 1.

The simulation results match the standard!

Section 4.2 Coding style for Verilog-AMS behavior models Coding style is very important in Verilog-AMS behavior modules creation. It has a significant impact on simulation performance, DC convergence and X/Z state situation. In this section, we will examine cases study on the behavior model in the Ether Phy design. Case A. Logic signal in cross statement Section 4.2.1: Check the simulation cost

Remember the “-profile” is setup in the AMS simulator options form from section 4.1.8. This option will dump the profile of the simulation costs.

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Open file ./simulation/top_sim/ams/config_ams_beh/netlist/ncprof.out In the “event and operators” section:

Look at the report in ncprofile file. This is perfect! None of nets significantly dominates the total simulation cost. The highest cost is net top_sim.I0.I44.blw_outp_E2L_logic with 3.6% of the total simulation cost. Action 4.2.2: Change to the bad Verilog-AMS coding example Open ether_sims.top_sim:config_ams_bad_beh_1 from LibManager.

The difference between config_ams_bad_beh_1 and config_ams_beh is as follows: config_ams_bad_beh_1: Ether.PI._interp is bound to the verilogams_bad view

config_ams_beh: Ether.PI._interp is bound to the verilogams view

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Only one line is different between the verilogams and verilogams_bad modules. Line 34 of verilogams: always@(IN[0]) begin -- This is good coding style Line 34 of verilogams: always@(cross(IN[0],1) begin -- This is bad coding style If we run the AMS simulation on “config_ams_bad_beh_1”, the simulation result would be correct. However, the simulation would take 50 minutes. That is approximately 10 times slower than config_ams_beh configuration. Action 4.2.3: View profile output Open file from ./simulation/top_sim/ams_config_ams_bad_beh_1/netlist/ncprof.out

The profiles output file points out exactly which line is most costly in the simulation. It indicates that line 10 of verilogams_bad costs 75.6% of all analog activities. In our example, IN[0] is evaluated as a logic signal. A logic signal in the cross statement will significantly slow down the simulation! Avoid putting logic signals in the cross statements!

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Case B Analog continuously changing signals in transition statements Action 4.2.4: Compare “PLL_250MHZ” verilogams_bad with verilogams module

View file: $AMS/../FLOW_ETHER_CDK090/design/data/cdba/ether/PLL_250MHZ/ verilogams_bad/verilog.vams

Examine the analog section in the end of the module.

(Bad Verilog-AMS Coding Style) View file: $AMS/../FLOW_ETHER_CDK090/design/data/cdba/ether/PLL_250MHZ/ verilogams/verilog.vams

(Good Verilog-AMS module) The behavior of verilogams_bad module actually is same as behavior verilogams. The problems with the verilogams_bad module are the I(IEXT_25u), I(IEX_100u) and I(IPLY_25u) signals. These continuously changing signals cause the transition statement to constantly re-evaluate the expression every time the value of those signals updates.

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Under special context, such as behavior block connecting to the transistor schematic; this will cause simulation slow down and lead to DC convergent problem.

The verilogams module demonstrated the better coding style! Case C Dealing with X/Z state under mixed-signal context Action 4.2.3 Compare “tenbt_rec” verilogams_bad and verilogams module View the verilogams_bad module $AMS/../FLOW_ETHER_CDK090/design/data/cdba/ether/tenbt_rec/verilogams_bad/ verilog.vams

(Bad Verilog-AMS coding style) View verilogams module $AMS/../FLOW_ETHER_CDK090/esign/data/cdba/ether/tenbt_rec/verilogams/ verilog.vams

(Good Verilog-AMS coding Style) At the behavioral level, the Ether Phy simulation runs fine using either the “verilogams_bad” or the “verilogams” module. However, the problems occur when the “verilogams_bad” module connects to the transistor level block during the mixed behavioral and transistor level simulation. A connect module is automatically inserted between the net from the transistor block to the behavior block. Using “= = “when the A

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to D connect module introducing the X/Z states, it causes X/Z state errors in the simulation stage. Use “= = =” Instead of “= = “as shown below: A = (B === 1b’1)? C: D Instead of A = (B)? C: D Section 5: Lower Level Behavior with Simvision Debugging Environment In this section, we will do partition for adc_top, transforming single high-level behavior module into multiple sub blocks behavior modules The behavior module of sub blocks will exactly match the port name, cell name and design hierarchy of the transistors level block, which will be implemented. This provides details as to the functional specifications for each of sub block under adc_top. The transistor level designer implements each of the sub level schematics to replace the behavioral blocks eventually. Before the transistors level schematic design stats, we need to verify the adc_top lower level behavioral module in the top-level context. In addition to what has been described above , we will leverage this simulation module to demonstrate the debugging method via Simvision environment. We use AMS Designer (with the Spectre solver) to perform the simulation in interactive model. Action 5.1 View the difference between high level behavior and low level behavior of adc_top cell Invoke icms and open “ether_sims.top_sims:config_ams_beh” Here is a snapshot of adc_top high level behavior configuration from the HED

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The high-level behavior of adc_top stops at the verilogams block. Open “ether_sims.top_sims:config_ams_beh_struct” Here is a snapshot of adc_top lower level behavioral configuration from the HED

The low-level behavior of adc_top contains the sub blocks: ADC_DECODE , ADE_WO_DECODE etc.

Action 5.2 Open schematic from config_ams_beh_struct In config_ams_beh_struct HED window, Select ether_sims.top_sim: schematic Click Right Mouse Button -> Open Action 5.3 Invoke ADE from schematic In the top-level schematic window, Tools -> Analog Environment ADE window appears… Action 5.4 Choose simulator and project dir Setup -> Simulator/Directory … Simulator: ams Project Directory: simulation Action 5.5 Load existing state Sessions->Load state; Form appears. Select state name: config_ams_beh_struct Click OK in the form This procedure completes all the necessary simulation setup in ADE. Action 5.6 Turn on the interactive simulation mode In ADE window, Simulation -> Run Options … Ensure the Interactive box (debugger) is on as below. We are running the simulation in interactive mode with Simvision debugging environment.

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Action 5.7 Run simulation In ADE window, Simulation -> Netlist and Run Simvision GUI will come up after 1 min. Simvision Environment includes

a. Simvision Design Browser

b. Simvision Waveform Display

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c. Simvision Console

Action 5.8 In Simvision Design Browser window, Expand the hierarchy by click icon + -> Select signals -> Click right mouse button -> send to waveform.

Here is the list of signals need to be selected Top_sim.XTAL25 Top_sim.I0.I45.BASE100TX_DIS Top_sim.I0.I45.CLKPLL_SC Top_sim.I0.I45.MLT3_TDATA[1:0] Top_sim.I0.I45.ADC[5:0]

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Action 5.9 In Waveform window -> Simulation -> Run Monitor the waveform marching …. The simulation takes about 8 mins. In waveform window, select TPIP_0 and TPIN_0 Go to View -> Zoom -> Full Y in Waveform window, Zoom into 20us -> 25us area, you will see the waveform displaying as below

The Simulation results look good!

Action 5.10 Keep CIW and LibManager windows open and close the rest of the windows

You can sign-off on adc_top low-level behavior design in top-level context! Following sections describe the powerful simulation debugging capability in Simvision Environment Action 5.9 In Simvision waveform window, Simulation -> Reinvoke Simulator Reinvoke form pops up -> click on Yes . Now simulation time back to T=0 Action 5.10 In Simvision Console window, Reference to Action 5.7 c> simvision console window. Type in TCL command

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Ncsim> run 10us Action 5.11 Once simulation time reaches T=10us, In Simvision Console window type in TCL commands as shown below

Ncsim> save -overwrite :S1 // Save the simulation snapshot up to 10us Ncsim > analog –show // display analog simulation options being used Ncsim > analog –reltol 1e-5 // change the reltol to 1e-5 for much small tolerance This flexibility enable user setup large tolerance in the chip power up session say 0<= T< =10us and change to more accurate option after T> 10us which could speed up the simulation. Ncsim > analog –stop 31us // change the stop time Action 5.12 In Simvision console window, type in TCL command Ncsim > analog –show You will see the reltol and stop time have been changed to new values Action 5.13 In Simvision Console window , type in Ncsim > run 5us Action 5.14 Once Simulation reach T=15us, In Simvision Console window, Simulation -> Restart from checkpoint Simvision Restart from Checkpoint form appears

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Simulation snapshot ether_sim.top_sim:S1 was saved by our TCL command Ncsim> run 10us ncsim> save –overwrite :S1 in Action 5.11.

Now when we restart the simulation, we do not need to go back to T=0 , we can actually restart from T=10us to save the simulation time.

In Restart from checkpoint window, Select snapshot ether_sim.top_sim:S1 and click on Restart Type in TCL command Ncsim > time You will see we back to the T=10us . Action 5.15 in Simvision Design Bowser window ,

select top_sim.I0.I44.ADC[5:0] signal , click on right mouse button and select “Send to Schematic Tracer”. Simvision schematic Tracer window appears ..

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The schematic Tracer will greatly help users for debugging design by looking into the signal driving-end and loading-end. This is extremely useful to debug the signal crossing analog and digital boundaries. Action5.16 In Simvision Design Browser window, Select DSP block top_sim.I0.I45 Click right button of mouse and select “Send to Source Browser”.

Simvision Source Browser appears …

Simvision Source Browser enables you to debug the design in text level.

Section 6: IP verification in Mixed-signal chip A. Mixed behavior and Calibrated Verilog-AMS Table model We have a calibrated Verilog-AMS table model from the existing schematic/SPICE netlist. Cadence VSdE-DCM provides the capability to “extract” the Verilog-AMS table model from transistor level design. The Verilog-AMS table model will significantly reduces the simulation time (up to 500X) while maintaining the accuracy within 1% relative to simulation run at transistor level.

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Using the calibrated table model allows us to QUICKLY verify the existing IP (schematic/SPICE netlist) to see if it can be re-used in the new design. In this section, we use the veriloga_tb view (Verilog-AMS table model) of PLL_PFD in the PLL_250MHZ block and verify it in the top-level context. We use AMS Designer (with the spectre solver) to perform this verification. Actions 6.1 Open the ether_sims.top_sim:config_ams_tb (both schematic and HED)

You can see the PLL_PFD is bound to the veriloga_tb view as the red arrow indicates Action 6.2: Browse verilogams table model In HED window, Move cursor on veriloga_ta and click on open

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Verilog-AMS table model will look up the parameter through the $table_model call. Action 6.3: View the table data file All the table data file are located in the same lib.cell:view directory. For PLL_PFD cell, you can see all the table files under $AMS/../FLOW_ETHER_CDK090/design/data/cdba/ether/PLL_PFD/veriloga_tb/*.vat Action 6.4: Invoke ADE from schematic window, In ADE window, Tools –> Analog Environment Action 6.5: Choose simulator and project dir Setup -> Simulator/Directory … Simulator: ams Project Directory: simulation Action 6.6 Load existing state Sessions->Load state; Form appears. Select state name: config_ams_tb Click OK in the form This procedure completed all simulation setup in ADE. Action 6.7 Run simulation

Note: Due to the time limitation, We do not recommend you to run the simulation in workshop session. This simulation takes about 40 mins to complete.

In ADE window, Simulation -> Netlist and Run . Action 6.8 Watch waveform display Once the simulation completes, the wavescan window pops-up Note: You can also plot existing simulation result. In ADE window, Results -> Plot Outputs -> Transient...

In Wavescan window, Turn on “strips” and zoom into the signal TPIP_0 in 20us – 22us area

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6.9 Keep DFII and LibManager window up and close the rest of the windows You can sign-off on PLL_PFD in top-level context! We can reuse the existing PLL_PFD transistor level design!

B. SPICE netlist integration for mixed-signal verification We have a SPICE netlist, which represents the PLL_250MHZ block. This block came from block level design group or third party IP vendor. This SPICE block needs to be verified in the top-level chip context. In order to do that, we need to integrate the SPICE block into the top-level config first then run AMS simulation. We use AMS Designer (with the UltraSim solver) to perform this verification. Action 6.10 From LibManager, Open the ether_sims.top_sim:config_ams_hspice_netlist (both schematic and HED)

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Action 6.11 In HED window, Select ether_sim.I0.I22.I30 (PLL_250MHZ), Click right mouse button , select -> Set Instance View -> Source file Enter the source file location form comes up ..

Action 6.12 Click on Browser button of above form and choose the PLL_250MHZ.hspiceD SPICE netlist file and click OK Now , the ether_sim.I0.I22.I30 binds to the HSPICE netlist. Based on the same use model we also support all industry standard spectre/HSPICE/SPICE netlist. Action 6.13: Invoke ADE from schematic window, In ADE window, Tools –> Analog Environment Action 6.14: Choose simulator and project dir Setup -> Simulator/Directory … Simulator: ams Project Directory: simulation Action 6.15 Load existing state Sessions->Load state; Form appears.

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Select state name: config_ams_hspice_netlist Click OK in the form This procedure completed all simulation setup in ADE. Action 6.16 In ADE window, Simulation -> Solver. Ensure Ultrasim Solver is selected . Note : This simulation takes more than 1 hour, due to the time limitation, we do not recommend you to run the live simulation in the workshop session. If you can access this database after the workshop session , you can run the simulation by click on ADE-> Simulation -> Netlist and Run Action 6.17 . Plot Simulation result

Click on the waveform icon in the bottom right of ADE window. The selected signal in ADE window will be plotted in the Wavescan. The TPIP_0/TPIN_0 signal slowly ramp up after 20.5us and get stable around 26us.

Zoom into 26us to 29us

This result looks good. Action 6.18 Keep DFII and LibManager window up and close the rest of the windows You can sign-off on SPICE block PLL_250MHZ in top-level context!

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Section 7: Top Level parasitic early simulation on critical net We have identified the potential critical signal I_REXT_REF100 between the top_common and Bias_port blocks. We would like do parasitic early simulation to determine the quality of the top-level floor plan/placement and first cut of routing. These two blocks transistor level have been completed in the blocks design team, the rest of the blocks are still behavior level in this early stage. The ADPI physical implementation team has been working on initial top level floor plan/placement and first cut routing based on the estimation then leverage on the Assura black boxes LVS and RCX (selected nets extraction) to extract the parasitic on the critical nets and provide the Assura extracted view. In this section, we are going to perform parasitic early simulation on critical net to determine the quality of the physical implementation in early stage. We have much transistor content in this config. In order to speed up simulation, we will use . UltraSim solver . Running simulation in batch mode(Wavescan) from ADE. Note: For those who are interested how to run Assura black boxes LVS and RCX, you will learn that from section 11. Action 7.1 From DFII LibManager , Open ether_sims.top_sim:config_ams_critical_net_postl (both schematic and HED)

Notice the top-level design ether_sim.I0 is bound to the layout-extracted view, “av_rcx_crit_net_es1” which is from our RCX run. Action 7.2: Invoke ADE from schematic window, In ADE window, Tools –> Analog Environment

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Action 7.3: Choose simulator and project dir Setup -> Simulator/Directory … Simulator: ams Project Directory: simulation Action 7.4 Load existing state Sessions->Load state; Form appears. Select state name: config_ams_crit_net_post1 Click OK in the form This procedure completed all simulation setup in ADE. Action 7.5 In ADE window, Simulation -> Solver. Ensure Ultrasim Solver is selected . Action 7.6 Run simulation Note : This simulation takes more than 1 hour. Due to the time limitation, we do not recommend you to run the live simulation in the workshop session. If you can access this database after the workshop session , you can run the simulation by click on ADE-> Simulation -> Netlist and Run Action 7.7. Plot Simulation result

Click on the waveform icon in the bottom right of ADE window. The selected signal in ADE window will be plotted in the Wavescan. .

Zoom into 20us to 25us

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The waveform results look good. The critical net I_REXT_REF100 are stable in 1.0V and TPIP_0/TPIN_0 signals are showing “3 steps” waveform. We have good quality of top-level floorplan/placement and first cut of routing Section 8: Mixed behavior and gate level Verilog with SDF The digital block designers are using ADPI flow and complete the DSP digital block from RTL to the Physical implementation. Now we have DSP gate level from RTL compiler (logic synthesis) and SDF parasitics comes from the physical design. SDF file include both Cell delays from timing dot lib file and interconnect delays from delay calculator based on SPEF extracted from layout. In this section, we are going to verify the top-level mixed-signal design with digital gate level verilog + SDF backannotation. We will use spectre solver and running simulation in interactive mode (Simvision debugger). Actions 8.1 Compile SDF file In your current working dir , $AMS/workarea cd ./SDF dir and run command as below ncsdfc top_1_port_pnr_si.sdf The raw SDF file is “top_1_port_pnr.si.sdf” ncsdfc compile this raw SDF file and create compiled SDF file “ top_1_port_pnr.si.sdf.X” Action 8.2 SDF command file preparation View SDF_CMD_FILE under the ./SDF dir COMPILED_SDF_FILE = “../../../../../SDF/top_1_port_pnr_si.sdf.X // this line provides the location of compiled SDF file. AMS in ADE will consider the current dir in ./simulation/top_sim/ams/config_ams_verilog_gate/netlist, so that we need to add relative path “../../../../../SDF” SCOPE = top_sim.I0.I45.I144 // The SCOPE line defines instance path to the digital block , So that SDF backannotation process will find the “target digital block” in the chip context. // In this case, our verilog gate level core block is top_sim.I0.I45.I144 in the chip context.

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Action 8.3 Schematic wrapper preparation. From LibManager

Open ether_digital.top_1_port_pnr:config_gate_SDF (both schematic and HED)

Notice that there is a schematic wrapper with 0 delay behavior buffers sounding the DSP verilog block ports. This serves the purpose of the SDF backannotation on digital ports on mixed-signal boundaries. Action 8.4 From LibManager

Open ether_sim.top_sim:config_ams_verilog_gate (HED config only )

In HED window , select top_sim.I0.I45 , Click right mouse button -> Set Instance View -> select config_gate_SDF

Action 8.5 In HED window , FILE -> Save

Select the ether_sims.top_sim:schematic_ams in HED -> click right mouse button -> select Open .. schematic window appears …

Action 8.6: Invoke ADE from schematic window, In ADE window, Tools –> Analog Environment

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Action 8.7: Choose simulator and project dir Setup -> Simulator/Directory … Simulator: ams Project Directory: simulation Action 8.8 Load existing state Sessions->Load state; Form appears. Select state name: config_ams_verilog_gate_SDF Click OK in the form This procedure completed all simulation setup in ADE. Action 8.9 SDF backannotation in ncelab stage In ADE window, Simulation -> Options -> Elaborator … We setup SDF command file in the SDF ANNOTATION section as below

Action 8.10 Run simulation Simulation -> Solver , ensure spectre solver is selected Simulation -> Run Options , ensure the interactive mode is selected Simulation -> Netlist and Run It takes around 3 mins to complete the netlisting/compilation and elaboration, then Simvision debugging GUI will appear Action 8.11 In ADE window, Check the ncelab log file to see SDF backannotation report

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Simulation -> Output Log -> Elaborator Log .. Notice there is no SDF warning in ncelab process SDF report section in ncelab.log as below

Action 8.12 In Simvision Waveform window, File -> Source Command Script Source command script Select restore.tcl.sv file under the netlist dir. We restore the TCL signal probing setup by simply source the existing saved command file . So that we do not have to select signal manually again in different simulation run. Previously selected signals are appearing in the Simvision Waveform window … Action 8.13 In Simvision Waveform window , Simulation -> Run Action 8.14 Watch waveform Once simulation reaches 100%, Zoom in 21us -> 25us

Simulation results look good.

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Action 8.15 Keep DFII and LibManager windows up and close the rest of the window You can sign-off on DSP gate level block with SDF in top-level context!

Section 9: Mixed Behavior and Transistor level Schematic The block creation designers have implemented the adc_top at the transistor level In this section, we are going to verify the adc_top transistor level in the top-level context. We use AMSUltra (UltraSim solver) to perform this verification. Action: 9.1 open ether_sims.top_sims:config_ams_mixed from LibManager. Turn on both schematic and HED. In HED window, adc_top binding to the schematic view, all the sub cell under adc_top are transistor level schematic (as red arrow point to)

Action 9.2: Invoke ADE from schematic window, In ADE window, Tools –> Analog Environment

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Action 9.3: Choose simulator and project dir Setup -> Simulator/Directory … Simulator: ams Project Directory: simulation Action 9.4 Load existing state Sessions->Load state; Form appears. Select state name: config_ams_mixed Click OK in the form This procedure completed all simulation setup in ADE. Action 9.5 Run simulation Note: Please do not run the simulation during the workshop session; it takes about 2 hours to complete. In ADE window, Simulation -> Netlist and Run Action 9.6 Watch waveform display Plot existing simulation results: In ADE window, Results -> Plot Outputs -> Transient... Wavescan window appears...

In wavescan window, Turn on “strips” and zoom into the signal TPIP_0 in 20us – 22us area

The simulation results look good. Action9.7 Keep the CIW and Library Manager Window open. Close the remaining windows.

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You have just sign-off on adc_top transistor level in top-level context!

Section 10: Full analog transistors level with RTL DSP Core At this point in our scenario, we have received the transistors level descriptions for all the analog blocks. Now a verification run is in order consisting of transistor level analog blocks with a digital RTL block. Due to the large number of transistors, we use AMSULTRA (UltraSim solver) to perform the verification. Action 10.1 Open design Open ether_sims.top_sim:config_ams_transistor via LibManager Turn on both config and schematic, HED and Schematic windows appear. Action 10.2 Setup UltraSim simulation options and speed dial In HED window, View -> Properties (turn on simulation properties) Below are the recommendations for setup simulation mode and speed options

General customer digital blocks (transistors) sim_mode=df, speed = 5 (default) Critical customer digital blocks (transistors) sim_mode=da, speed = 5 General Analog blocks sim_mode=ms, speed = 5 Critical analog block (VCO) sim_mode=ms, speed =2

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A graphical overview of the UltraSim accuracy and speed options is below:

Please see additional explanations of UltraSim simulation mode in Appendix A. Action 10.3: Invoke ADE from schematic window, In ADE window, Tools –> Analog Environment Action 10.4: Choose simulator and project dir

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Setup -> Simulator/Directory … Simulator: ams Project Directory: simulation Action 10.5 Load existing state Sessions->Load state; Form appears. Select state name: config_ams_mixed Click OK in the form This procedure completed all simulation setup in ADE. Action 10.6 Run simulation Note: Please do not run the simulation during the workshop session; it takes about 6 hours to complete In ADE window, Simulation -> Netlist and Run Action 10.7 Watch waveform display Plot existing simulation result: In ADE window, Results -> Plot Outputs -> Transient... Wavescan window appears... Turn on “Strips” and look into signal “TPIP_0”

Action 10.8 Zoom into 25u – 30u area Relative to the ideal behavioral level result, the signal TPIP_0 has about 2us delay before it starts to ramp up. It is stable after 26us. These are good results.

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Action 10.9 Keep CIW and LibManager windows up and close the rest of the windows You can sign-off all analog transistors level design in the top-level context! Section 11: Top-Level Parasitics with DSP verilog gate and SDF We have reached the parasitic stage. The layout team has delivered the block level layout and finished the top routing. Most of the critical nets will be in the top level due to: 1. Many long routing paths at the top-level layout 2. Digital and analog layout blocks are far apart with the critical nets between these

different domains. Additionally, the Physical design of digital DSP block is implemented via Cadence’s SOC encounter platform. The STA passed with SDF back annotation completed. Also, the analog block designers have completed the block level layout. The parasitics simulation at the block level was successful.

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It is reasonable for us to consider a top-level parasitic simulation as a final verification. Note: If you are not interested in ASSURA LVS/RCX , you can go directly to Action 11.9 , we will use the existing extracted view to perform the final simulation. Action11.1 Open top-level layout Invoke icfb (Note: we have to use icfb for physical verification tools) Open “ether.top: layout” via LibManager Layout window appears as bellows: Action 11.2 In layout window Design -> Options -> Display... Setup the display stop level to “1” Now you can see the layout window showing as below:

This is a hierarchical layout. The top-level layout has six blocks Bias_port (analog), anlg_cntl(analog), top_common(analog) Top_1_port_receiver (analog), top_1_port_transmit (analog) Top_1_port_pnr (digital DSP core) --- Red arrow points to DSP block implemented from ADPI flow The top-level parasitic approach is to extract the top-level interconnect parasitics and

perform the full chip verification.

In order to do that, we need to run a black box LVS and RCX to get the top-level extracted view. Action 11.3 Run top-level hierarchical LVS

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In layout window, Assura -> LVS Assura LVS form appears... Load State -> ether_top_6blackbox_demo

Action 11.4 View avParameters definition In LVS form click on Modify avParameters… LVS avParameters form appears … The Red arrow points to the black box cells definition entry

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Note: To be able to run the black-box LVS, the black-box cells must be defined via the avParameters form. The red arrow points to the avParameter “blackBoxCell”. All six blocks in the top level layout are defined as black box cells in the LVS form. An important note regarding hierarchical layout is that it MUST follow the hierarchical rule as follows: The routing paths MUST be PIN TO PIN, if there is a routing layer on top, which directly connects to a layer inside the black box, the hierarchical LVS will report errors. The result will be floating nets in the netlist. This occurs in black box LVS/RCX, because the internal layers in the black box cells are no longer visible one level up. Only the pins of the black box cells are recognized by black box LVS/RCX. Action 11.5 Watch the Black boxes LVS result After the LVS complete the LVS Debug window appears

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The schematic and layout MATCH ! Action 11.6 RCX extraction Assura -> Run RCX “No Technology directly found” dialogue box appears , click on Close

RCX form appears … Load State: RCX_demo

The ether.top:av_top_connect_rcx view will be generated when RCX completes.

Action 11.7 Check the Extraction setup In RCX form, Click on Extraction Tab, Extraction setup form appears… The extraction is setup as follows: RC extraction mode is on Full chip all nets is on

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Action 11.8 View Netlisting Setup In RCX form, click Netlisting Tab, Netlisting setup form appears…

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Note: We are using the standard parasitics capacitor and resistor model. The options for parasitic cap and parasitic res are set to “include as comment”. Otherwise, RCX will add process-based res and cap model names such as “cmodel” and “rmodel” in database of the extracted view. Action 11.9 From LibManager, Open ether_sims.top_sim:config_ams_xtors_rcx_gate_sdf” (Both schematic and HED config) HED window appears …

Notice the top-level design is bound to the layout-extracted view, “av_rcx_intcon”, from RCX run. Action 11.10 View the Verilog-AMS parasitics netlist

Open file $AMS/workarea/simulation/top_sim/ams/config_ams_xtors_rcx_gate_sdf/netlist/ ihnl/ether/top/av_rcx_intcon

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Look into the Verilog-AMS netlist. Due to the RC parasitics components, the nets have been broken into multiple segments, such as \2: \:5 etc. All the capacitors and resistors in this netlist are parasitics, which have been extracted from the top-level layout.

Action 11.11: Dealing with Multiple power supplies based on Scope-based discipline. At this stage, all analog content in the design have been implemented as xtors level schematic and layout. Our digital block has been implemented on 1V stand cell lib. We have implemented level shifter circuits to bridge the voltage gap between analog 2.5 blocks and digital 1.0V. Inside chip: Analog blocks 2.5 V -> Xtors Lever Shifter (2.5V -> 1.0V) -> Connect Module(1.0V) -> Digital Block (1.0V) -> Connect Module(1.0V) -> Xtors Lever Shifter(1.0V -> 2.5V) -> Analog Blocks On top level, we have input signals from digital verilog test bench. The required voltage to some of the ports in ether_sim.I0 is 2.5V. Here is the list I0.XTAL25 I0.BGTRIM I0.SIDDQ I0.DISABLE10 I0.DISABLE100 I0.RESETN_0 Therefore, the Supply Voltage in the Connect Module should be 2.5V between test bench and ports listed above. We will use the discipline-based solution to handle multiple powers 2.5V for 6 ports in above list and 1.0V for the rest of A/D boundary in whole chip. The discipline-based solution requires two things 1. Discipline-based connect rule 2. Scope based discipline assign to the design. It can be Library/Cell/Cell terminal/instance/instance terminal/Net In this section, we are going to use Discipline-based connect rule + assigning discipline to the cell terminal. Action 11.12 Prepare the discipline-based connect rule Go to dir : cd $AMS/../FLOW_ETHER_CDK090/share/connect_lib Open discipline-based connect rule file MPS_CR.v

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Please notice that we defined the discipline-based rule above. The Connect module supply voltage will be 2.5V only if the discipline on digital port is specifically defined as logic25, the default discipline on the digital ports is logic and will be 1.0V. Action 11.13 In ADE window Invoke ADE from schematic window,

In ADE window, Tools –> Analog Environment

Action 11.14 In ADE window Setup -> Simulator/Directory … Simulator: ams Project Directory: simulation Action 11.15 Load existing state Sessions->Load state; Form appears… Select state name: config_ams_xtors_rcx_gate_sdf Click OK in the form Action 11.16 Prepare the discipline assignment to cell terminal In schematic Window, Now, AMS button appears in the schematic tool bar. AMS -> Default Discipline Selection -> Cell Terminal

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We assigned the logic25 to all 6 ports listed above. See top-level schematic as below ,

For those 6 highlighted nets on the A/D boundaries , they are 2.5V and the rest of the A/D boundaries in whole chip are 1.0V

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Action 11.17 Run simulation Due to time limitations, running this simulation during the workshop session is not recommended. Simulation -> Netlist and Run Action 11.18 Watch waveform display Plot the existing simulation results: In ADE window, Results -> Plot Outputs -> Transient... Wavescan window appears...

Turn on “Strips” and look into signal “TPIP_0

Action 11.19 Zoom into 26u – 28u area The signal TPIP_0 starts to ramp up at 21us and is stable after 26us. Relative to the ideal behavioral result, it is a good result

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Action 11.20 Parasitic simulation result vs. Behavior simulation result Go to working directory , cd $AMS/workarea Invoke Simvision by just type simvision & Simvision GUI appears …. Action 11.20.1 Open parasitic simulation database In Simvision Design Browser window -> File -> Open Database Select parasitic simulation database from Simvision GUI in following path. ./simulation/top_sim/ams/config_ams_xtors_rcx_gate_sdf/psf/psf.trn Action 11.20.2 Open behavior simulation database In Simvision Design Browser window -> File -> Open Database Select parasitic simulation database from Simvision GUI in following path. ./simulation/top_sim/ams/config_ams_beah/psf/psf.trn

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a. psf contains parasitic simulation waveform database b. psf(2) contains behavior simulation waveform database

Action 11.20.3 Select signals form two databases Click on icon + to expand the database hierarchy -> Select following signals form both psf and psf(2) databases -> click on right mouse button -> send signals to waveform Top_sim.TPIP_0 Top_sim.I0.I45.RESET Top_sim.I0.I45.CLKPLL_IN Top_sim.I0.I45.MLT3_TDADA[1:0] Action 11.20.4 Create the signal group In Simvision waveform window, Use Ctrl button to select signal pairs. For example : psf.TPIP_0 and psf(2).TPIP_0 In Simvision waveform window, Edit -> Group, Signal psf.TPIP_0 and psf(2).TPIP_0 belong to the same group

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The digital signals (green) are almost same from these two databases except the phrase shift caused by delay. Compare analog signal psf.top_sim.TPIP_0 parasitic one vs. psf(2) TPIP_0 behavior one. The waveforms are all 3-steps shape. Parasitics waveform slowly ramp up from 20.4us and get stable around 26us due to significant RC effect. The parasitic simulation results look GOOD.

Sign-off on the design in top-level parasitics context!

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Appendix A UltraSim Simulation Mode

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Appendix B– Definitions, Acronyms and Abbreviations ADE Analog Design Environment AICM Automatically Insertion Connect Module AMS Analog and Mixed-Signal CIW Cadence Information Window DUT Design under Test HED Hierarchy Editor RCX RC extraction LVS Layout vs. Schematic. MPS Multiple Power Supplies PDK Process Design Kits CM Connect Module CR Connect Rule

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