Amplifier Circuits - Philadelphia University · 2013. 11. 6. · The cascode configuration has one...

Module: Electronics II Module Number: 650321 Electronic Devices and Circuit Theory, 9th ed., Boylestad and Nashelsky

Philadelphia University Faculty of Engineering

Communication and Electronics Engineering

Amplifier Circuits

Multistage Amplifier Analysis:

- Cascaded Systems: Based on the two-port approach, the multistage amplifier is clearly shown

in the figure below. Each of these stages could be one of the previously studied BJT, FET transistor amplifiers.

The loaded voltage gain of an amplifier is always less than the no-load level. From the Figure shown above let the under loaded system voltage gain

is , where . Then the total current gain could be

found as

TvA

nT vvvvvAAAAA

321

L

iv

ii

Lo

i

oi R

ZA

ZVRV

IIA

TT

1

.

The no-load parameters can be used to determine the loaded gains as

follows:

Fig. 5.77 Substituting the internal elements for

the two-port system of Fig. 5.76 Fig. 5.76 Two-port system

Lecturer: Dr. Omar Daoud Part I 1

Fig. 5.80 Including the effects of the source resistance Rs. Fig. 5.79 Applying a load to the two-port system of Fig. 5.77.


Applying the voltage-divider rule to the output circuit of Fig 5.79 results

in

oL

Lv

ov

oL

Livo

RRRA

ViVA

RRRVAV

NL

NL

The fraction of the applied signal reaching the input terminals of the

amplifier of Fig 5.80 is also determined by the voltage-divider rule again

si

iv

s

ov

ivvo

si

isi

RRRA

VVA

VAAVRR

RVVNLs

NL

and

At the existence of both of Rs and RL, the voltage gain equation will be

modified as:

oL

L

si

iv

s

ov RR

RRR

RAVVA

NLs

For the current gain

L

sivi

L

ivi

is

s

i

isi

RRRAAand

RRAA

RRV

RVII

ss

The larger the source resistance and/or smaller the load resistance, the less the overall gain of an amplifier

Ex. For the given single-stage amplifier, with RL=4.7 k and Rs=0.3 k, determine: (a) Avs, (b) Av , (c) Ai. The two-port parameters for the fixed-bias configuration are Zi=1.071k, Zo=3k, and AvNL=-

80.11.

2



Ex: The two-stage system of the given Fig. employed a transistor emitter-follower configuration prior to a common-base configuration to ensure that the maximum percent of the applied signal appears at the input terminals of the common-base amplifier. In this

d for each system, with the exception of Z and Z for Fig., the no-load values are provide i o lues. For the given configuration, determine: the emitter-follower, which are the loaded va

(a) The loaded gain for each stage. (b) The total gain for the system, Av and Avs. (c) The total current gain for the system. (d) The total gain for the system if the emitter-follower configuration were removed.



Ex.: For the given RC-coupled BJT amplifier given below, calculate the

gain and the output voltage

erall gain if a 10-k load is applied to the second stage and compare it to the

c) the input impedance of the first stage and the output once of the second stage.

following a) the no-load voltage

b) the ovresults of (a)



Note: The name of RC-coupled is derived from the fact that the coupling capacitor is combined with the input

impedance of the next stage to perform the load on the stage itself. The coupling capacitor prevents the two

a) The DC analysis of both transistors gives

stages from DC viewpoint.

Solution

V108651025106.34

46.3385.6

2.2

//(//

3)(

2

2

1

ivo

e

cv

e

ic

e

Lcv

VAV

krRA

rRZR

rRRA

NLT

b) The overall gain with the 1b) The overall gain with the 1

106.343.102

5.62.665)////

5.6426 and A,20A4

V4

V7.47.415

20

36

3

21

)(

v

e

eE

BE

EE

BEBE

B

A

rR

mmrIIm

RVI

-VV

V

NLT

0k load applied is

0k load applied is

15

V

33 104.28106.342.210)(

oL

Lv

i

ov ZR

RAVVA

NLTT

c) The

10

input impedance of the first stage

6.953//// 211 ei rRRZ

Whereas the output impedance for the second stage is

kRZ co 2.22



Ex. 8.16: Calculate the dc

i s voltage gain, input

impedance, and resulting

output voltage for the

S find the Q-values,

equation

b a ,

impedance, output

cascade amplifier shown in

the Fig. 8.49. Calculate the

load voltage if 10-k load

is connected across the cade amplifier circuit for Example 8.16. Fig. 8.49 Casoutput.

olution: Using the dc biasing techniques to

plot the curve of the Shockley2

1

P

GSDSSD V

VI I

GS loop, in this case VGS=-ISRS

and IDQ=2.8mA.

plot the dc load line from the

From these two plots VGSQ=-1.9V

mSVVIg GSDSSm 6.21

2

V PP

he two JFET stages are CS, thus t

T he voltage gain for each of them is

4.38

24.6

24.6//

2

2

Tv

Dmv

DmGiLDm ARgA

RgRRRRg 1

vA

The input impedance Zi=RG=3.3M

The output impedance Z =R =2.4k assuming that r is

o D d

The resulting output voltage Vo= AvVi =384mV

The output voltage across the load resistor

310

oL

LoL ZR

RVV mV

Ex. 8.17: For the cascade

amplifier of Fig.8.50, use the

dc bias calculated in the

previous examples to

calculate input impedance,


Fig. 8.50 Cascaded JFET-BJT amplifier for Example 8.17


output impedance, voltage gain and resulting output voltage.

Solution:

kZMZ

VAV

o

i

ivo

2.23.3

V6.0

A

rRA

RgrRRRRgA

e

Cv

DmeLDmv

1.59946.338

77.15.953////////

2

1 21

vT

- ascoded Systems:

The cascode configuration has one of two configurations. In each case

the collector of the leading stage is connected to the emitter of the

following stage.

to ensure minimum input Miller

ance, whereas the following CB stage provides an excellent

C

The arrangements provide relatively high-input impedance with low

voltage gain for the first stage

capacit

high-frequency response.

Fig. 5.86: Cascode configuration.


Fig.5.87: Practical cascode circuit for Example 5.19.


ode configuration of

Fig. 5.87.

Applying the voltage-divider rule to find the Base voltages,

Ex. 5.19: Calculate the no-load voltage gain for the casc

Solution:

8.68.3e

r

26

V8.108.66.57.4

6.57.4182B

V

Note: The loading on the first transistor is the input of the second one. The

h the input impedance of a CB configuration

A8.3

1.125.4V27.47.0V95.4

8.66.57.47.418

11 EBEBm

kIVVV

result is the replacement of RC wit

(RC=re).

For the first stage (CE), the voltage gain could be calculated as:

11

e

cv r

RA

While the voltage gain for the second stage (CB) is

2652

e

cv r

RA

The overall no-load gain is

26521

vvv AAA T

Note: The CE stage provides higher input impedance than can be expected from the CB

stage.

Power

the cycle. Thus, this requires the Q-point to be biased at a level so that at least half the signal swing of the

Amplifier Classes:

- Class-A Power Amplifier :

The output signal varies for a full 360° of



pply voltage level or too low to approach the lower

It has a very poor efficiency, especially with small input signals, when

very little ac power is delivered to the load. In fact, the maximum tween 25% to 50% which is due to that it uses a good

, even with no input signal and the dc

1) Series-Fed

output may vary up and down without going to a high-enough voltage to be limited by the susupply level, or 0 V in this description.

efficiency of a class A circuit, occurring bebased on the circuit configuration. This isamount of power to maintain biasbias is at the half of the supply voltage level.

There are two types of configuration:

Main Specifications: - In this type we can use the simple

fixed-bias circuit connection as shown in the Fig,

- To be used as a power transistor, it is used in the range of a few to tens of Watts,

- Capable of handling large power or

arge-signal amplifier because of oor power efficiency.

-


put signal will cause the base current to vary above and below the dc bias point, which will then cause the collector current (output) to vary from the dc bias poi e collector–emitter voltage to vary around its dc bias value.

- As the input signal is made larger, the output will vary further around the

- An input ac signal is applied to the amplifier, thus the output will vary from its dc bias operating voltage and current as shown in the Fig. 12.4.

- A small in

nt set as well as th

established dc bias point until ??? (either the current or the voltage reaches a limiting condition; for the current this limiting condition is either zero current at the low end or VCC/RC at the high end of its swing. For the collector–emitter voltage, the limit is either 0 V or the supply voltage, VCC).

Power Considerations:

- The power into an amplifier is provided by the supply Wi no input signal, the dc current is the collector bias current, ICQ, The power then drawn from the

Pi(dc)= VCCICQ - Even with an ac signal applied, the average current drawn from the supply remains

the same, so that it represents the input power supplied to the class A series-fed amplifier.

Output Power:

. th drawn

supply is

- The larger the input signal, the larger the output swing, up to the maximum set by

- The ac power delivered to the load (RC) can be expressed in a number of ways. a) Using rms signals:

the circuit.

peak signals: b) Using

c) Using peak-to-peak signals:



Efficiency:

- The efficiency of an amplifier represents the amount of ac power delivered (transferred) from the dc source.

efficiency could be- Maximum calculated as follows: aximum power output can be calculated as The m

C

CCacoC

C

CCCE VPR

VI

VV2

max

max

C

C R8)( max

The maximum power input can be calculated using the dc bias current set to one-half the maximum value:

C

CCC

CC

CCCCCdci RVR

VVIVP

22

2

)( maxmax

The maximum efficiency is

A series-fed amplifier is thus seen to be 25%. The maximum efficiency of a class Since this maximum efficiency will occur only for ideal conditions of both voltage swing and current swing, most series-fed circuits will provide efficiencies of much less than 25%.

Ex. Calculate the input power, output power, and efficiency of the amplifier circuit in the given Fig. below for an input voltage that result in a base current of 10 mA peak.



Solution: The Q-point can be determined to be

a2) TrMa

nsformer-Coupled in Specifications: A form of class A amplifier havinmaximum efficiency of 50% uses

- g a l

transformer to couple the output signato the load as shown in Fig.



Operation of Amplifier Stage:

a) DC Load line - The transformer (dc)

winding resistance determines the dc load line for the circuit. Typically, this dc resistance is small (ideally=0) and, as shown in the given Fig., a 0 dc load line is a straight vertical line.

- A practical transformewinding resistance would

- here is no dc voltage drop

tance, and the load line is drawn straight vertically from the

b) Signal Swing and Output AC Power

r

be a few ohms, but only the ideal case will be considered in this discussion. Tacross the 0 dc load resisvoltage point, VCEQ = VCC.

imary can be calculated

using

- The ac power developed across the transformer pr

The ac power calculated is that developed across the primary of the transformer. Assuming an ideal transformer (a highly efficient transformer has an efficiency of well over 90%), the power delivered by the secondary to the load is approximately that calculated using the previous Eq.

- The output ac power can also be determined using the voltage delivered to the load. The voltage delivered to the load can be calculated



The power across the load can then be expressed as

The output ac power then calculated using

where the load current

Ex. Calculate the ac power delivered to the 8 speaker for the given circuit. The circuit component values result in a dc base current of 6 mA, and the input signal (Vi) results in a peak base current swing of 4 mA.



Efficiency:

- The input (dc) power obtained from the supply is calculated from the supply dc voltage and the average power drawn from the supply:

Pi(dc) = VCCICQ



r-coupled amplifier, the power dissipated by the ll (due to the small dc resistance of a coil

- For the transformetransformer is sma ) and

present calculations. Thus the only power loss t dissipated by the power transistor

will be ignored in the considered here is tha (as a heat)

Pi(dc) - Po(ac)

nsformer-coupled amplifier, the maximum oes up to 50%. Based on the signals obtained efficiency can be expressed as

and calculated using.PQ =

- For a class A tratheoretical efficiency gusing the amplifier, the

The larger the value of VCEmax and the smaller the value of VCEmin, the closer the efficiency approaches the theoretical limit of 50%.

Ex. For the circuit in the previous example, calculate the dc input power, power dissipated by the transistor, and efficiency.

Solution:

Ex. Calculate outputs of

(a) V(p) (b) V(p)(c) V(p) =2 V.

Solution

the efficiency of a transformer-coupled class A amplifier for a supply of 12 V and :

= 12 V. = 6 V.

:



s-B Power Amplifier

A class B circuit provides an output signal varying over one-

int for class B is therefore at 0 V, with the output then varying from this bias point for a half-cycle.

ide operation on the nega ycle are necessary. The combined

- Clas

half the input signal cycle, or for 180° of signal.

The dc bias po

Obviously, the output is not a faithful reproduction of the input if only one half-cycle is present. Two class B operations—one to provide output on the positive-output half-cycle and another to prov

tive-output half-chalf-cycles then provide an output for a full 360° of operation (This type of connection is referred to as push-pull operation).

Class B operation, with no dc bias power for no input signal, can be

put (DC) Power:

shown to provide a maximum efficiency that reaches 78.5%.

In

The amount of this input power can be calculated using Pi(dc) = VCCIdc

where Idc is the average or dc current drawn from the power supplies. Note: In class B operation, the current drawn from a single power supply has

the form of a full-wave rectified signal, while that drawn from two power supplies has the form of a half-wave rectified signal from each supply.

In either case, the value of the average current drawn can be expressed as

Then the dc power input results in

Output (AC) Power: The output power can be calculated as



Efficiency:

(using I(p)=VL(p)/RL). The previous equation shows that the larger the peak voltage, the higher the circuit efficiency, up to a maximum value when VL(p)=VCC, this maximum efficiency then being

Power Dissipated by Output Transistor:

The power dissipated (as heat) by the output power transistors is the difference between he load.

P2Q= Pi(dc) - Po(ac)

where P2Q is the power dissipated by the two output power transistors. The dissipated each transistor is then half of the P2Q.

V, determine the input power, output power, and circuit efficiency.

the input power delivered by the supplies and the output power delivered to t

power handled by

Ex. For a class B amplifier providing a 20-V peak signal to a 16 load (speaker) and a power supply of VCC = 30



ations:

Maximum Power Consider

For cla maximum output power is delivered to the load when VL(p) = CC:

ss B operation, the

V

The corresponding peak ac current I(p) is then

so that the maximum value of average current from the power supply is

Using this current to calculate the maximum value of input power results in

The maximum power dissipated by the two output transisvoltage across the load is

tors occurs when the output

for a maximum transistor power dissipation of

Ex. For a class B amplifier using a supply of VCC=30 V determine the maximum input power, output power, and trans

and driving a load of 16, istor dissipation.



Ex. Calculate the efficiency of a class B amplifier for a supply voltage of VCC =24 V with peak output voltages of:

(a) VL(p) = 22 V. (b) VL(p) = 6 V.

C -

cla B. This is to reduce the crossover distortion that

Class AB operation still requires a push-pull

thbaas

swn

v rage power supplied by each source and the average power dissipated in each transistor are larger than the one for class B, which results in less power efficiency.

Power Considerations:

lass-AB Power Amplifier :

An amplifier may be biased at a dc level above the zero base current level of class B and

e one-half the supply voltage level of abovss A; this bias condition is class A

happened in class B.

connection to achieve a full output cycle, but e dc bias level is usually closer to the zero se current level for better power efficiency,

s r bed shortly. de c iFor class AB operation, the output signal

ing occurs between 180° and 360° and is i h r class A nor class B operation. e t e

The a e

- Each transistor draws current for a half-cycle, then

the dc current is

Cdc

II

Then the input power delivered by the source is

CCCdcCCdci

IVIVP )(

- The ac output power could be calculated as

422)()( pacooormsaco

CCCCCEQ IVIvPivP



Efficiency:

- Class-C Power Amplifier :

The output of a class C amplifier is biased for operation at less than

180° of the cycle and will operate only with a tuned (resonant) circuit, which provides a full cycle of operation for the tuned or resonant frequency. This operating class is therefore used in special areas of tuned circuits, such as radio or communications.

The power dissipated of the transistor is low because it is ON for a small percentage only of the input cycle.

The Basic Concept of Operation:

A common emitter class C amplifier with a resistive load is shown in the given figure.

It is biased below cutoff with the negative VBB supply. The ac source has a peak value that is slightly greater than VBB+VBE so that the base voltage exceeds the barrier potential of the BE-

e positive peak of each cycle. ring this short interval the transistor is turned ON and then

junction for a short time near th Du

the ideal maximum collector current is IC(sat) and the ideal minimum collector voltage is VCE(sat).

The Power Dissipation:

CE(sat)ring the ON could be defined as

If the output swings over the entire load, the maximum collector current is

IC(sat) and the ideal minimum collector voltage is V , therefore the power dissipation du



PD(ON)= IC(sat) VCE(sat)

)sat()sat()()( CECon

onDon Pt avgD VIT

tT

P

Ex. A Class C amplifier is driven by a 200kHz signal. The transistor is ON for 1s, and the amplifier is operating over 100 percent of its load line. If the IC(sat)=100mA and VCE(sat)=0.2V, what is the average power dissipation? Solution:

4mV0.2V100mAs5s15

2001

)(

avgDPskHz

T

Tuned Operation:

The resistively loaded Class C power amplifier is of no value in linear applications. ???? (The output is not a replica of the input

). Thus, class C with

parallel resonant circuit appears as shown in the figure.

The short pulse of collector current on each cycle of the input initiates and sustains the oscillation of the tank circuit so that the output sinusoidal voltage is produced.



The resonant frequency of the circuit is determined by the formula of

LCfr 2

1 .

The current pulse charges the capacitor to approximately VCC. After the pulse, the capacitor quickly discharges, thus charging the inductor. Then, after the capacitor completely discharges, the inductor's magnetic field collapses and then quickly recharges C to near VCC in a direction opposite to the previous charge (This completes one half-cycle of the oscillation

).

The capacitor discharges again, increasing the inductor's magnetic field. The

inductor then quickly recharges the capacitor back to a positive peak slightly less than the previous one??? (due to energy loss in the winding resistance), which completes one full cycle and then the peak-to-peak voltage is therefore approximately equal to 2VCC.

Note: The amplitude of each successive cycle of the oscillation is less than that of

the previous cycle ??? (Because of energy loss in the resistance of tank circuit) and the oscillation will eventually die out. However, the regular recurrence of the collector pulse re-energizes the resonant circuit and sustains the oscillation at constant amplitude.



When the tank circuit is tuned to the frequency of the input signal, re-

the tank. A class C amplifier operates as a energizing occurs on each cycle of frequency multiplier. By tuning the resonant tank circuit to higher harmonics.




UMaximum Output Power and Efficiency: The voltage developed across the tank circuit has a peak-to-peak value of

approximately 2VRCCR, the maximum output power can be expressed as:

C

CC

C

CC

C

rmsout R

VR

VR

VP2

707.0 222

where RRCR is equivalent parallel resistance of the collector tank circuit and represents the parallel combination of the coil resistance and the load resistance.

The total power that must be supplied to the amplifier is PRTR=PRoutR+PRD(avg)

Therefore, the efficiency is

1 approachesclosely efficiency C class the , )()(

avgDoutavgDout

out PPwhenPP

P

- Class-D Power Amplifier :

This operating class is a form of amplifier operation using pulse (digital) signals, which are on for a short interval and off for a longer interval.

Using digital techniques makes it possible to obtain a signal that varies over the full cycle (using sample-and-hold circuitry) to recreate the output from many pieces of input signal.

The major advantage of class D operation is that the amplifier is on (using power) only for short intervals and the overall efficiency can practically be very high.

Class D operation can achieve power efficiency over 90% and provides the most efficient operation of all the operating classes.

Multistage Amplifier Analysis: Power Amplifier Classes:

Amplifier Circuits - Philadelphia University · 2013. 11. 6. · The cascode configuration has one...

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