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Amkor TechnologyAdvanced Package SolutionsAmkor TechnologyAdvanced Package Solutions

Enabling aMicroelectronic

World®

Robert Lanzone – SVP Engineering Solutions

Confab 2013 Las Vegas

• R&D Focus

• Core Technologies

• Focus on Package Integration

R&D TopicsR&D Topics

Amkor Confidential Information Jul-132


R&D Focus : R&D Focus : Profitable Growth From New Profitable Growth From New Package TechnologiesPackage Technologies

In the Right MarketsIn the Right Markets


End Market Summary


Communications

52%

Consumer

19%

Computing

10%

Networking

11%

Other

8%

Smartphone

Tablet

Wireless LAN

Gaming

Television

Set Top Box

PC / Laptop

Hard Disk Drive

Peripherals

Server

Router

Switch

Automotive

Industrial

4

Note: Percentages represent share of LTM 1Q13 Net Sales

$112

$80

$100

$120

$140

t R

eve

nu

es (

$ in

bill

ion

s)

Mobile Communications Driving Semi Growth

Growth - $43BCAGR - 10%


Growth - $15B

Semiconductor IndustryGrowth

2012 - $292B2017F - $380BGrowth - $88B

CAGR - 5%


$69

$36

$68

$47

$25

$47 $42

$74

$62

$32

$58

$0

$20

$40

$60

Mobile Phones & Tablets

Consumer Computing Networking Automotive Other*

Se

mic

on

du

cto

r M

ark

et R

5

Source: Prismark Partners. February 2013* Other includes Medical, Industrial, Military and Aerospace

2012

2017F





R&D Focus : Customer & Market SegmentR&D Focus : Customer & Market Segment


R&D Focus : Critical Customer AlignmentR&D Focus : Critical Customer Alignment


• R&D Focus






Amkor’s Core Technology & Advanced Amkor’s Core Technology & Advanced Integration SchemesIntegration Schemes

Thermal &Thermal &

Cu PillarCu Pillar

TSVTSV


WLFOWLFO

Thermal &Thermal &Adv. MaterialsAdv. Materials

HighHigh--End FCEnd FC

Amkor’s Core Technology & Adv. Integration Amkor’s Core Technology & Adv. Integration SchemesSchemes

Thermal &Thermal &

Cu PillarCu PillarCu PillarCu Pillar

TSVTSV


WLFOWLFO



Interconnection : Fine Pitch Cu PillarInterconnection : Fine Pitch Cu Pillar

•• Copper Copper Pillar PlatformPillar Platform

� Foundation for most of future advanced packaging platforms

� Potential cost reduction on substrate

� Better electrical performance

� Larger die in a given body size

•• Next Node ActivityNext Node Activity


•• Next Node ActivityNext Node Activity

� Reducing pitch / increasing density

� 28/20nm in Qualification

� Extending to all flip chip products

Executive Summary

Driven by Demand for Handheld, HighPerformance, Low Power Devices

Provides Significant Improvement Over Solder Bump


Launched in 2010, >200 Million Units Sold

Industry-Leading Platform Being Adopted byMultiple Customers

Enabling Technology for 2.5D and 3D Packagingwith Through Silicon Vias

� Digital Baseband

� Applications Processor

� Networking ASICs

� Digital TV ASICs

Why the Need for Fine Pitch Copper Pillar?

� Function Integration in All Three Dimensions

� Silicon Node “Shrinks” But Die Size Remains Unchanged or Grows

Technology Trends & Challenges Devices


� Power Management� Increased I/O Density

� Finer BGA Pitch

� More Demanding Warpage and Coplanarity Criteria

13

Developed and Commercialized by Amkor and TI

2004 2006 2008 2010 2012

� Early Wafer Level Copper Pillar Bumping Development

� TI Fine Pitch Development

� Thermo Compression Assembly Development

� Shape, Height, Pitch, Alloy, Reliability, Electromigration,…

� > 200 Million Units Sold to Date

� Multiple Customers in Production or Qualification


2004 2006 2008 2010 2012

� New Copper Chemistry Developed

� Product Launch in Conjunction with Texas Instruments

Sputtered Seed Layer (TiWCu)

Resist Coat

Plate Cu/Solder (SnAg)

Strip Resist

Expose and Develop

AnimationCreation of Cu Pillar


Seed Layer Etch

Strip Resist

Silicon Active Area

Reflow Solder

NCP writingheating

1. Bond Head Down Die

Thermo-Compression Bonding (TCNCP)Animation


1. Bond Head Down

2. Bond force then head temperature is going up to solder melting point : 220 �

3. Bond Head up :

Bonding completed

NCP

PCB

Cu pillarDIE

HEAD

Bump pad Solder NCP

Cu pillar

Die

PCB


Thermal &Thermal &

Cu PillarCu Pillar

TSVTSVTSVTSV


WLFOWLFO



Integration : Through Silicon Via (TSV)Integration : Through Silicon Via (TSV)

•• Current StatusCurrent Status

� World’s first mass production of TSV backside finishing

� World’s first production of fully integrated TSV package platform

� “Logic dies on Si interposer” product is being produced

� ~10 customers are engaged in active TSV development

� Target devices

� Logics on Si interposer


� Logics on Si interposer

� Logics + memories on Si interposer

� Memory / Memory stack

� Memory / Logic combination

Focus : Provide Most Cost Effective / Reliable Option

Chip on Chip“CoC-oS”

Chip on Wafer“CoW-oS”

Chip on Substrate“Co-CoS”

TSV Assembly Requires FlexibilityTSV Assembly Requires Flexibility


2.5D TSV & Interposer Supply Chain2.5D TSV & Interposer Supply Chain

• High End Products : Networking, Servers

� Silicon interposers ; < 2um L/S, < 15nsec latency, > 25k µbumps per die

� Amkor is engaged with Foundries to deliver silicon interposers today

• Mid Range Products : Gaming, Graphics, HDTV, Adv. Tablets

� Silicon or Glass interposers ; < 3um L/S, < 25nsec latency, ~10k µbumps/die

� Glass may provide cost reduction path in future


� Glass may provide cost reduction path in future

� Not actively pursuing glass interposers yet as infrastructure still immature

• Lower Cost Products : Lower End Tablets, Smart Phones

� Silicon, Glass or Laminate interposer ; < 8um L/S, low resistance, ~2k µbumps

� Must provide cost reduction path to enable this sector

� Working with laminate supply chain to enable

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Thermal &Thermal &

Cu PillarCu Pillar

TSVTSV


WLFOWLFOWLFOWLFO



• WLFO is now established as a viable alternative to conventional laminate-based and wafer-based packages

• The elimination of a conventional laminate substrate and utilization of wafer-level packaging’s advanced design and feature size capabilities provide many benefits for WLFO, including:

– Increased I/O density

– Reduced form factor

Advanced Platform : Wafer Level Fan Out (WLFO)Advanced Platform : Wafer Level Fan Out (WLFO)


– Reduced form factor (including z-height)

– Improved electrical and mechanical performance

– Multi-chip capability

– Outstanding performance

capability

– Scalability within a heterogeneous assembly platform

– Opportunity for advanced 3D structures

Wafer Level Fan-Out Revenue Forecast


• WLFO reached the $100M market valuation in 2011

• Predicted by Yole to reach $250M market valuation in the 2015/16 timeframe once demand moves from IDMs to fabless wireless IC players and the OSAT supply chain expands

Amkor Embedded Die Strategy

• All future technology roadmaps indicate a need for higher levels of integration, thinness and cost effective solutions

– Embedded die will be a key enabling package technology that addresses these roadmap requirements

• Amkor already supports embedded die in substrate

– Passive integration in high volumes already


– Passive integration in high volumes already

– Active integration just starting

• Amkor has made strategic decision to focus newest efforts in this space on a ‘Panel Level Fan-Out’ platform to address cost, integration and scalability

• Embedded die resources now focused on Panel platform development

Evolution of WLFO Evolution of WLFO

• Key enabling technologies for extensions into 3D

– Thru Mold Via (TMV®)

– Fine pitch copper pillar

– CoC possum™

TMV®3D PoP

3D Die on Pkg


Die

Die

Die

Die

Die

3D F2F 3D Stacking

Standard WLFO Structure

3D Die on Pkg


Thermal &Thermal &

Cu PillarCu Pillar

TSVTSV


WLFOWLFO


HighHigh--End FCEnd FCHighHigh--End FCEnd FC

Flip Chip & Advanced Packaging Leader

LTM 1Q13 Flip Chip & Advanced Packaging Revenue

� Migration to Flip Chip, 3D and Advanced Packaging Continues to Accelerate

� Driven by Strong Demand for Smartphones, Tablets, Consumer Electronics, Network Infrastructure

� Enhances Device Performance, Reduces Power Consumption and Form Factors

($ in millions)

$800 $870

$1,230


Power Consumption and Form Factors

� Higher Gross Margin and Returns Versus Wirebond

Non-Amkor Sources: Company Press Releases

$530

STATS SPIL ASE Amkor

• Production Status

� Increasing body size (>55mm BD)

� Increasing die size (>26mm)

� 45/40nm in HVM, 32/28nm in AVM

� Full lead free qualified at 65, 45/40, and 32/28nm

� Cu Pillar for below 150um bump pitch

� Molded FCBGA in AVM

Adv. Packages : High Performance Flip ChipAdv. Packages : High Performance Flip Chip


� Molded FCBGA in AVM

� Coreless substrate under development for 32/28nm

• Production Status

� Increasing body size (~45mm BD)

� Increasing die size (~26mm)

� 40/28nm in LVM

� Eutectic & Lead-free qualified at 40/28nm

� Eutectic & Lead-free & Cu pillar for min 150um bump pitch

� Thin core under development (<0.4mm) substrate for 32/28nm

Adv. Packages : Molded U/F FCBGA (Adv. Packages : Molded U/F FCBGA (FCmBGAFCmBGA))


� Thin core under development (<0.4mm) substrate for 32/28nm

Advanced FC Packages : Chip on ChipAdvanced FC Packages : Chip on Chip

• Next Generation of FC – CoCCoCPOSSUMPOSSUM

–– MEMs, Automotive, NetworkingMEMs, Automotive, Networking


LOGIC (780um thickness)

ASIC (60um thickness)

40um bump pitch CoC Technology

Heat Spreader

200um bump pitch

LOGIC

Substrate

Advanced FC Packages : Chip on Chip, cont.Advanced FC Packages : Chip on Chip, cont.

• 2014 targeted production


ASIC (60um thickness)

Cu pillar with LF solder + microbumpCu pillar with LF solder + microbump


Cu PillarCu Pillar

TSVTSV

Thermal &Thermal &Thermal &Thermal &


WLFOWLFO

HighHigh--End FCEnd FCMUFMUF

Thermal &Thermal &Adv MaterialsAdv Materials

Thermal &Thermal &Adv MaterialsAdv Materials

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Adaptive

Learning

Adaptive

Learning

Advanced Packaging & Technology IntegrationAdvanced Packaging & Technology Integration


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Amkor’s Advanced MaterialsAmkor’s Advanced Materials


Thermal

MUFDA��EFA��

8W/mK3W/mK 5W/mK• Epoxy Mold Compound

• Die Attach Paste


• Thermal Performance


• Die Attach Paste • L/F (Ag paste)• L/F (Sintered paste)• BGA

• Die Attach Film (BGA)

• TIM (Flip Chip)

• Underfill Material (FC) 1~2W/mK0.5W/mK 1W/mK

10W/mK4W/mK 6W/mK

5W/mK1W/mK 2W/mK

10W/mK4W/mK 10W/mK

60W/mK60W/mK

20W/mK8W/mK 20W/mK

* Thermal conductivity is bulk value of the material, not actual package thermal performance.


Pb free / Cu pillar

22nm28/32nm

DieDie

• Bump Alloy

• Si Node

C

Exposed Die

A

D

BE

Target package type : FCmBGA

EU

28/32nm

• Molded Underfill (MUF)


22nm28/32nm

<120um130um

<35um50um

450um500um

57.5mm50mm

>22mm20x22mm

• Si Node

• Bump Pitch (C)

• Bump Gap (D)

PackagePackage

• Die Size (A)

• Mold edge to substrate (B)

• PKG size (D) 50mm

28/32nm

150um

60um

19x16mm

600um

45mm

40um

400um

55mm


• Next Generation Underfill Development Strategy

– Capillary Based (continuous):

� High modulus and superior adhesion ; good flowability & low warpage

– Film Based :

� Pre-coated non-conductive film underfill material on wafer


Thin Die Support

Low k & bump protection

DBRC Control

UF on-die control

Easier Process flow than normal

UF

TSV Application (die to die)

support

NCF

NCF process

Wafer dicing TC bonding Post cure (optional)Pre-applied

• R&D Focus






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Wafer LevelWafer Level

Die

Board LevelBoard Level

Amkor Advanced Package IntegrationAmkor Advanced Package Integration

LOGIC LOGIC

ASIC ASIC

LOGIC

ASIC

CoCCoCpossum™possum™CoC

possum™


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Die LevelDie Level

Package MigratioPackage Migration to 3D & n to 3D & SiPSiP--MCM IntegrationMCM Integration


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Production Transition Developing

Amkor Advanced Package Integration RoadmapAmkor Advanced Package Integration Roadmap


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Die

Die

Industry Advanced Package Integration RoadmapIndustry Advanced Package Integration Roadmap


Commissioned report September 2011 courtesy of Amkor Technology and Yole Développement

Develop

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Production Transition

Amkor Aligned Adv. Package Integration RoadmapAmkor Aligned Adv. Package Integration Roadmap

Amkor RoadmapAmkor Roadmap


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Industry RoadmapIndustry Roadmap

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