Ambient Intelligence: A Gigascale Dream Facing Nanoscale ... · Ambient Intelligence: A Gigascale...

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Ambient Intelligence: A Gigascale Dream Facing Nanoscale Realities

Hugo De ManProf. K.U.Leuven

Senior Research Fellow [email protected]

© imec 2005

?

Giga-Scale Complexity Nano-Scale Realities

AmI Systems Atoms

10nm


The Ambient Intelligence Dream

Secure, trustworthy computing and communicationembedded in every-thing and every-one.

A pervasive, context aware ambient, sensitive and responsive to the presence of people


Device Classes for AmI

Stationary Nomadic Transducer

Am

bient Body

Home

OfficeCar

“UPA”

TCRF

TCRF

TCRF

UMTSWLANWPANWBANDA/VB

PDADSCDVCMP3GPSHC…

Hear, See, Feel, Show…

“More Moore” “More-than-Moore”

MIMO

Internet IPv6

100Gop/s 10 Gop/s

1Watt 100mW

‘Milliwatt’ (battery, f.c.)

10 Watt

‘Watt’ (mains)

1Top/s 10Mop/s

Gb/s

0.1Gb/s

kb/s

100µW

energy

energy

energy

(ambient)‘Microwatt’


Outline

More Moore: ultra complexity

Bridging the gaps between systems, software and atoms

More than Moore: ultra creativity

The interface challenge


Design Metrics for Ambient Intelligent Digital Devices (isscc’05, 1.2)

• Power Efficiency (PE): 10 to 200 GOPS/Watt

• Part cost < 10€ NRE cost > 50M€PE two-orders-of-magnitude > GP microprocessor

at 1/20 th of part cost

• Flexible by (downloadable) embedded softwareFrom Hw centric ASIC to Sw centric PLATFORM

• Real-time stream based processing (MM, SDR)Memory intensive (> 70% area, power)


Two Gaps between AmI-Dreams and Nano-Scale Realities…Software centric AmI specs

7th heaven of software

Hell of nano-scale physics

500M tr Platform architecture

500 processors50MB memory

1 Watt

xx nm Si IP Blocks

PlatformDesign

IPCreation

CMOSScaling

SystemDesign

SDR

MiddlewareAPI’sRTOS

Architectural gap

*Techn. Aware Design”

TAD*

ESL

UncertaintyMetrics!

Physical gapDFM


1. Hell of Nano-Scale Physics

• Leakage power starts to dominatelarger gate delay than scaling for performance predicts

• Voltage headroom shrinksmakes A&RF guys deeply worried (sub 1 Volt circuits)

• Interconnect claims the first role…challenging timing, power, synchronism, signal integrity

• Increasing device variabilityjeopardizes predictability and yield, affects design process

• New device architectures needed<65nmImpact layout style, need for DFM and IP library design


Leakage Power IssuesPsdleak ~W.Tj

2exp(-qVTH/nkTj)

PsdleakIon~ (VDD-VTH)1.5/tox

Hence “LateCMOS” devices below 65nm?

Pgateleak

tox


“LateCMOS” Device Architectures below 65nm?

• Gate leakage: Hi-k, metal gates (when?)• Mobility keeper: Strained Si (now)• SD leakage: Hi VT ⇒Hi-VDD ⇔ dyn power

Lo-VDD ⇔ variability, ↑td , ↑ //Better SCE mgmt->UTBFDSOI, Finfets

• Ion boost,SCE ↓ Multi-Gate, FINFET, DGFDSOI?

2005 2015

L=35nm

SiGe

L=35nmL=35nm

SiGe

strainstrainHfSiON2

high high --kk

NiSi

FUSIFUSI

metal gatemetal gate

CNT??UTBSOI 32nm?

BUT Late CMOS diversity must percolate to system level…


Ultra-Low Vdd for Sensor Intelligence

Leakage Ener gy ( over 1ns) Vs. Vdd

0

5

10

15

20

25

30

0 0. 2 0. 4 0. 6 0. 8 1Vdd ( V)

Elea

kage

(aJ

)

* Data for 4-bit adder (130 nm CMOS) obtained using Monte-Carlo simulations over process distribution, Vth=0.24V

Active and standby power consumptions reduce quadratically with Vdd scaling.

7X

Swi t chi ng Ener gy Vs. Vdd

0

60

120

180

240

0 0. 2 0. 4 0. 6 0. 8 1Vdd ( V)

Eswi

tchi

ng (

fJ)

9X

Source: Qin, Rabaey UCB

Switching Energy vs. Vdd Leakage Energy (1ns) vs. Vdd


Price to Pay at Ultra-Low Vdd

Del ay Var i at i on/ Mean Vs. Vdd

01020304050607080

0 0. 2 0. 4 0. 6 0. 8 1Vdd ( V)

tp V

aria

tion

/Mea

n (%

)

Delay Mean Value

• Delay variance at low voltages very dramatic

Delay Variance/Mean

* Data for 4-bit adder (0.13 µm CMOS) obtained using Monte-Carlo simulations over process distribution, Vth=0.24V

Delay Mean Vs. Vdd

00.5

11.5

22.5

33.5

0 0.2 0.4 0.6 0.8 1Vdd (V)

tp(u

s)

• Mean performance degrades exponentially below threshold

Source: Qin, Rabaey UCB

Concern over data storage: Memory Functionality / Stability


Different CMOS for Different People…

For Microprocessor, Servers

@100 Watt active power, 20W leakage acceptable ⇒ low VTH , high Ion, ABB to manage leakage yield

BUT for AmI…

Leakage mWatt nodes <10mW, µWatt sensor nodes<10µW⇒ Scaling for low leakage at expense of gate delay⇒ More GOPS from more transistors faster ones⇒ Wires more important anyway…change layout style


Scaling for Low Leakage AmI

( Courtesy: Philips Techn. Modeling Group)230 kgate Standard Cell Layout for 10pA/µm sd Leakage

BULK CMOS

SG

DG

FDSOIMUGFET

0

0.2

0.4

0.6

0.8

1

180 130 90 65 45 45 nm

WIRESCELLS

Avg

. Ene

rgy

/ Cyc

le (R

el.)

Techn. Node

1.8V

1.2 1.2 1.2

0.75

1.2

Lo-k dielectric barrier materials?Keep wires further apart Localize interconnectBack to regular layout (EDA!)

CuCu Cu7.04.0

Low k

CuCu CuCu

Low k

Hi-k

2.0

BEOL technology or layout tool work neededBelow 65nm new device architectures needed


Global Interconnect Issues

• Global Interconnect delay does not scale with logic• Synchronous zones 45nm @ 500MHz < 2*2 mm2

• Interwire capacitance jeopardizes timing closureSS SSVV VVGG

VDD

SignalVss

Source:Khatri DAC’99

• CMP Copper Thickness Variation up to 40%

Source: Preagasus Delay Variation


Random Dopant Variability …

35nm Bulk CMOSTransistorMin. size

Asenov, ESSCIRC’04

100

LeakageVariability!

σVT = Ao(L)/(WL)1/2


Variability Impacts Parametric Yield

Low Standby Power CMOS; Min size transistors

0

0.2

0.4

0.6

0.8

1

1.2

1.4

180 130 90 65 45 32Techn. Node(nm)

VDD

VT

VT+3σ∆VT

VT-3σ∆VT

BULK

VDD, VT (V)

Headroom

noise

0.5

1

1.5

2

2.5

3

180 130 90 65 45 32

Gate Delay Variability

BULK

VT+3σ∆VT

VT-3σ∆VT

Slow

Leak

y

Techn. Node(nm)gate

N

VDD

DGFDSOI DGFDSOI

Yamaoka VLSI‘04 Wfin

Lg

Hfin


Living with VT Variability in Logic

• Use min Lg only for critical delay path• Use large W when matching is critical• Use large logic depth (less pipe stages, slower

clock!)Ntdo

Fcl < 1/ Ntdopd

fpd

f

tdo

N=1

N>>1

Ntdo

Ntdo

tdσσ =

σVT = Ao(L)/(WL)1/2


Long Lg Usage Pattern in µP

Sizing matters for :

-Leakage -Variability

Mitigation!

Source: Intel ISSCC 2006 p05.3

SRAM!

Computation


Variability Impact

• A new dimension to design space (P-A-T-Y) • Statistical design, device sizing for yield crucial

• SRAM first victim…else VDD scaling problematic• Below 65nm new device architectures needed?

45nm FinFet SRAM IEDM’04

0.31µm2 6T SRAM FinFETs, FUSI gate

imec3D SRAM

Samsung isscc’05Asenov Esscirc ‘04


Reaching the end of UV litho => DFMMask design cost ↑

OPCPSM

SRAF: Sub Resolution Assist FeaturesSB : Scattering Bars

Rule Based DRC runs out of steam: 2000 pages for 22nmTowards Model Based hot-spot detection and correction Booming DFM EDA industry Towards Restricted Design Rules <45nm (Regular layout)32nm => EUV?


Sys+

Tech

Software dominated

2005-2020 Not Business as Usual!

1980 1990 2000 2010 2020

Cum

ulat

ive

Inte

rdep

ende

ntC

halle

nges

500 250 180 130 90 65 45 32 22nm … ???

ManualDesign

T+S Happy Scalingtech sys

RTL HwIP PlatformAREA TIMING

Variability

YIELD

5 3.31.8

1.2

Gate LeakageHi-k, MG

LateCMOS FINFETFDSOI

M-MetalgateHi-k,Lo-k

StrainSiGeCNW&T

RFNvmem

SUM…

NewDesign

Dynamic PowerLow Cost, Power, TTM > Fcl

1 0.5 0.2V

POWER

SD LeakageULV


2. The Architectural Gap

“Managing Giga-Complexity ”

Create SL methods, tools and skills for designing flexible, yet power-efficient platforms

(1 B uncertain devices + >10M lines of code)and for mapping real-time MULTIPLE SW applications on

them at lowest NRE cost

Challenges• Overcome Power-Flexibility Conflict• Predictable (SW) application mapping• While at the same time dealing with

the CMOS process ®evolution


Power-Flexibility Conflict

32 bit IntrinsicPE

2 1 0.5 0.25 0.13 0.07feature size(µm)

1000

100

10

1

0.1

0.01

0.001

Power Efficiency (GOPS/Watt)

AmI

SwClean

//

Reconfigurable // computingMuxed data paths

IS Computing

[Claasen isscc’99]

FGCG

µP

VDD<1VVIP

SiHiveCoolflux

AdresFeenecs


How to Reconcile PE and Flexibility?

• Cleaning software for low powerMinimize # memory transfers, operations = energyRegularize, vectorize code, min. data-sizeFactor 5 to 10 lower power but tools and skills needed

• Exploit parallelism to reduce powerBetter to use 20 processors @ 100MHz than 1@ 2GhzBut urgent need for design methods, tools and skills to support Hw/Sw co-design (devil is in the software!)

• Exploit task level dynamism for sub 1 Volt opJust enough VDD, Fcl, IL


The Devil is in the Software and the NRE cost…

Software productivity increase 5.8%/y <-> 58%/y Moore

Hw dependentReal TimeReliability

DependabilityConcurrency

HeterogeneousParallel

HardwarePlatform

Merging of hw and software cultures is people management …changing people is harder than installing and operating a new litho machine!

2 y/ tech node7y / methodology


But System Design must change…

Better than worst case design else loose advantage of scaling

Design reliable systems from uncertain components

Allow errors to happen!Shannon

1948


Ways to Cope…

1. Adapt VDD,fcl,IL at run time to whatever mother nature provides and to dynamic nature of software tasks

2. Use tile based GALS architectures, networks-on-chip, and error correcting on-chip communication techniques

3. Back to regularity (Litho, context)

RapidChip


Run Time Adaptive Design

Processor1

Processor2

Processor3

t

t

t

2

2

2

1

3

1

1

3

3

mon

itorin

g

cycle budget CB

Min Σ Eit1+t2+t3 < CB

SoftwareRTOS

HardwarePlatform

Run-Time Controler

TasksCB

Optimal SchedulingFcl ,VDD,VBB

Courtesy: Catthoor isscc03 9.1

IPMonitorstd, IL, T

Dynamic Task scheduler/assigner

Another new design dimension to mitigate leakage and variability and improve yield and performance

Pareto set of optimal task mappings


<1GHz<4mm2

<1GHz

45nm

GALS Platform of Future + NOC

I/O

peripherals

3-D stacked m

ain mem

ory

RouterBusBasedMultiPr

ME

LocalMemory Hierarchy

ErrCD

NIP

Power

TestM

gmt

SYNCH TILE

Mapping V,VT,fcl

IL,T,td

Middleware, RTOS, APIPA- Run-Time ControlerApplications SW

Clean

30Mtr

ASYNCH Low swing Network-on-chip

SS SSVV VVGG


More Moore = more than more of the same…

• Greater challenges than ever before: Managing giga-complexity faced with CMOS diversificationNew design methods, tools and skills urgently needed

• To reconcile the hell of physics with heaven of AmI dreams

But easier to install equipment than to change people’s mindNew processing nodes 2 years, new design methods take 7 years,

• Need for sharing multi-disciplinary R&D costFrom material science to computer science and societal

engineering…Open innovation alliances from software to process development

• Not for the faint of heart: few platforms by industry-R&D alliances and disciplined armies of engineers…


But there is “More than Moore”…

• Key to AmI: interfacing to the ambient and to the consumer…

• Needed are the simplest, cheapest intelligent micro-transducer nodes…

• Combining a plethora of technologies…MEMS, Displays, Energy scavenging, SiP, biosensors,

security, ULP radio protocols, ULP computing…


More than Moore Challenges

The art of ingenuity

• Get to the ultimate limits of Miniaturization (<1cm3)Cost (< 1€)Power ( < 100µW)

• Design for utmost simplicity • Interact with non-E world• A micro-system node in ad-hoc network


Heterogeneous Integration

The key art of More than Moore design:need for the renaissance engineer

RF-ID tag

Wheel speed Phone camera 3D accelerometer

Inkjet head Ultra-filter

RF-MEMS switch

Lab-on-a-Chip Nano-syringe

GSM frontend

fluidicspassives

RF

high-voltagesensors &actuators

fluidicspassives

RF

high-voltagesensors &actuators


Sensor Node Challenges

<10kb/s1%

DSP&storageSecurity

MAC

RFNon-EWorld

Sensor CE-ADC Processor PicoRadio

20µW 20µW 40µW 20µWAvg.

Power80 Mops 2nJ/b

Energy sensorPower Mgr

< 500mV CMOSULP radio

Above IC MEMS, passivesGrain size packaging

100 µWAvg power

Ambient


Sensor Radio’s

ProtocolµC

2.4 GHz Radio

ApplicationProcessor

(EEC)

Solar Cell

Antenna

(a) IMEC 1.4cm3, SiP Mote for EEC, ECG , 500µW@1%, 400b/sec

3D stack

(b) UCB PicoBeacon Tx [21.4]1.9GHz, 400µW, 5kb/s

2.4*3.9cm2Battery/

powermgmt

1 2 4 GHz

500MHz-70

-50

-30 dB

(c) IMEC 0.18µ 0.25 mm2 UWB Tx0.5nJ/bit @ 10 kb/s

BatteryPowerMgmt


More Moore and Analog/RF

• Scaling: squeezing the analog/RF designerMatching, voltage headroom, substrate noise

Inductors / passives don’t scale (Above IC WFP, SIP)Go for dirty RF/Analog, correct errors by digital

10pF == area of 8000 gates @ 45nm10 bit ADC == energy of 4 M gates @ 45nm

• < 90nm useful for > 10 GHz trend

CourtesyRuthenbar CMU


Above IC MEMS

Poly-SiGe

CMOS circuits

MEMS< 450oC

CMOS

MEMS

Yaw Sensor + ElectronicsCourtesy: BOSCH-PHILIPS-IMEC


Above IC Integration Examples (IMEC)

Above IC InductorsHighest Q, high density

Above-IC CapacitorsUp to 10 nF/mm2

Above-IC digital Interconnect TRL lines

>10 Gbit/channel

5.5GHz ESD protected LNA on 90 nm rf-CMOS

Lowest noise

5GHz VCO on 90 nm rf-CMOSLowest power & phase noise

24GHz Single-stage LNA on 90 nm rf-CMOS

Highest frequencies


Convergence on the Nano-Scale…

cmµmnm

BIOTECH

transistor

x109

NANOELECTRONICS

31nm31nm

Fromherz


Interfacing Bio to Nano-Electronics

electrical

action potential

chemical

neurotransmitter

© IMEC 2005© IMEC-HUJI 2003

© Infineon 2003

© P. Fromherz 2005

© P. Fromherz 2001

ULP Interpretation-control-transmission


4 NSF-SRC Questions for the Future…

HOW CAN WE COPE WITH INCREASED:

1. Complexity (NRE cost)2. Uncertainty (variability, reliability, noise,

workload…)3. Diversity (heterogeneous MTM systems)4. Adaptability (materials, device

architecture, 3D…)

ALL AT THE SAME TIME (Παντα Ρει)


SO:

We need to lock nano scale device, circuit and hardware /software architects together under the same roof and

address strategic application domains

And take time to talk to each other!!

Collaborative multidisciplinary research needed between Academia-industry-research institutes


THANK YOU

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