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 VHDL environment for floating point Arithmetic Logic Unit -

ALU design and simulation 

Rajit Ram Singh, Asish Tiwari

Dept of Electronics Engg

Vindhya Institute, Indore

singhrajitram@gmail.com 

Vinay Kumar Singh 

TATA Motors Ltd. Luck now -

India

vinay.singh@tatatechnologies.com 

Geetam S Tomar Machine Intelligence Research Labs,

Gwalior, India

gstomar@ieee.org

ABSTRACT: VHDL environment for floating point arithmetic

and logic unit design using pipelining is introduced; the novelty in

the ALU design with pipelining provides a high performance ALU

to execute multiple instructions simultaneously. In top-down

design approach, four arithmetic modules, addition, subtraction,

multiplication and division are combined to form a floating point

ALU unit. Each module is divided into sub- modules with two

selection bits are combined to select a particular operation. Each

module is independent to each other. The modules are realizedand validated using VHDL simulation in the Xilinx12.1i software.

 Keywords: ALU - Arithmetic Logic Unit, Top-Down design,

Validation, Floating point, Test-Vector  

I. INTRODUCTION 

Floating point describes a system for representing numbers that

would be too large or too small to be represented as integers.

Floating point representation is able to retain its resolution and

accuracy compared to fixed point representation limited word

size. Numbers in this form are represented in scaled form in

multiple of base of binary. The representation of number is of 

significant digit multiplied by its base with exponent power.For representing floating point number the IEEE 754 standard

is used in digital system. Arithmetic logic unit (ALU) is a

digital circuit that performs arithmetic and logical operations

[1] and executes the commands accordingly. The ALU is a

fundamental building block of the central processing unit

(CPU) of a computer and the inputs to the ALU are the data to

  be operated on and a code from the control unit indicating

which operation to perform. Its output is the result of the

computation. These codes are used to indicate cases such as

carry-in or carry-out, overflow, divide-by-zero, etc. Floating

Point Unit also performs arithmetic operations between two

values, but they do so for numbers in floating point

representation. And the ALU with floating point operations is

called a FPU. A pipeline is a technique used in the design of computers and other digital electronic devices to increase their 

instruction throughput (number of instructions that can be

executed in a unit of time). The fundamental idea is to split the

  processing of a computer instruction into a series of 

independent steps, with storage at the end of each step. This

allows the computer's control circuitry to issue instructions at

the processing rate of the slowest step, which is much faster 

than the time needed to perform all steps at once. The term

 pipeline refers to the fact that each step is carrying data at once,

and each step is connected to the next so that at no time

machine is idle and after few steps output is available at

each clock execution. Implementing pipeline requires

various phases of floating point operations be separated

and be pipelined into sequential stages.  We have

  proposed VHDL environment for floating point ALU

design and simulation is done for faster unit. This has

further helped in easing the description, verification

simulation and hardware realization. VHDL is widelyadopted standard and has numerous capabilities that are

suited for designs of this sort. The use of VHDL for 

modeling is especially appealing since it provides

formal description of the system and allows the use of 

specific description styles to cover the different

abstraction levels employed in this design. The

synthesis of the proposed design is done for high speed

and multiple executions to help in the management of 

large data size.

II DESIGN AND METHODS 

The main objective of this paper is implementation

of pipelining in design of the floating-point ALU usingVHDL. The sub-objectives are to design a 16-bit

floating point ALU operating on the IEEE 754

standard. Floating point representations supporting the

four basic arithmetic operations; addition, subtraction,

multiplication and division are described in this section.

The second sub-objective is to model the behavior of 

the ALU design using VHDL the Specifications for a

16-bit floating-point ALU design are:

i.  Input A and B and output result are 16-bit binaryfloating point.

ii.  Operands A and B operate as follows

A (operation) B=results

Operation can be addition (+), subtraction (-),

Multiplication (*), division (/)

iii.  ‘Selection’ a 2-bit input signal that selectsALU operation and operate as shown in table1.

iv.  Status- a 4-bit output signal work as flag amicroprocessor.

v.  Clock pulse is only provided to the module 

which is selected using demux. vi.  Concurrent processes are used to allow

 processes to run in parallel hence pipelining isachieved by this execution. 

2011 International Conference on Communication Systems and Network Technologies

978-0-7695-4437-3/11 $26.00 © 2011 IEEE

DOI 10.1109/CSNT.2011.167

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allow  processes to run in parallel hence pipelining isuseful to speed up the operations. 

Selection  Operation 

00  Addition 01  Summation 10  Multiplication 11  Division 

Table1: select ALU operation. 

Fig:1 top level view of the ALU design

Table 2: Status Signals

ALU operations are divided into smaller modules: addition,

subtraction, multiplication and division and is controlledthough demux and mux. The major module is further 

subdivided into smaller modules as shown in figure No. 1. It

consists of four functional arithmetic modules, three

demultiplexers and two multiplexers. The input operands and

the clock signal are routed through multiplexers and

demultiplexers to the correct functional modules along with

status signals. The other modules used are as per their specific

tasks and performance. The addition module has two paths and

selection is done by control circuitry.

Fig. 2: View of Add Module Selection Unit

Addition module has two 16 bit inputs and one16 bitoutput selection input is used to enable or disable the

module this module is further divided into 4 sub

modules zero check, align, add_ sub and normalize

module. The zero check module detects zero operands

early in the operation and based on the detection result

it has two status signals, which eliminates the need of subsequent processes to check for the presence of zero

operands. The align module checks status signal from previous stage.

Pipeline floating point subtraction module: 

Subtraction module has two 16-bits inputs and one 16-

 bit output. Selection input is used to enable/ disable theentity depend on the operation. This module is divided

further into four sub-modules: zero-check aligns

add_sub and normalize module. The subtraction

algorithm differs only in the add_sub module where the

subtraction operator changes the sign of the result.

Fig: 3 pipeline floating point addition

III .SIMULATION AND DISCUSSION 

Design is verified through simulation, which is done

in a bottom –up fashion. Small modules are simulated

status 0000   Normal operation 0001  Overflow 0010  Underflow 0100  Result zero 1000  Divide by zero 

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in separate test benches before they are integrated and tested asa whole. The results are shown for each module separately infigures below.

Align RTL1

RTL of Demux: 

Simulation Result of Align:

Simulation Result of DeMux

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RTL Mux

Simulation Result of MUX

Same way the results of Division, subtraction and other 

functional modules were obtained and are in

accordance to expectation.

IV. COCLUSION

On simulation of various designs of dependent modules

of ALU for floating point based operations the results

obtained are satisfactory and are in accordance to

theoretical expectations. The design can be downloaded

on ALTERA package and viewed for space and speed

  performance. The proposed design is having better 

  performance when viewed on the basis of simulation

results obtained.

V. REFERENCES

[1] M. Daumas, C. Finot, "Division of Floating PointExpansions with an Application to the Computation of the

Determinant”, Journal of Universal Computer Science, Vol. 1 No.6, pp 323-338, June 1999.

[2]AMD Athlon Processor techmcal brief, Advance MicroDevices Inc., Publication no. 22054, Rev. D, Dec. 1999.

[3]S. Chen, B. Mulgeew, and P. M. Grant, "A Clustering

techmque for digital communications Channel equalization

using radial basis function Networks,'' IEEE Trans. Neural

 Networks, vol. 4, pp. 570-578, July 1993.

[4] Mamu Bin Ibne Reaz, MEEE, Md. Shabiul Islam, MEEE, Mohd.S. Sulaiman, MEEE. ICSE2002 Proc. 2002,penang-Malaysia.

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