Samuel Silverstein, Stockholm University

Alternatives for TileCal digital readout to FEX

Background

Phase-1 eFEX and jFEX receive digital EM layer data from LAr DPS But equivalent Tile data path not available

before Phase 2 So: need to extract digital hadronic tower

sums produced from the current analog sums sent to L1Calo

Three points where this can be done See next slide

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Alternatives

EM calorimeterdigital readout

Muon detector

Analog sums from Tile/LAr nMCM

CMX

CMX

JEM

Endcap sector logic

Barrel sector logic

MuCTPi

Muon Trigger

L1Topo CTP

CORE

DPS

eFEX

jFEX

PreProcessor

Topological info

CTP outputNew/upgradedHardware

Central Trigger

L1Calo Trigger

JEP

CP

Receiverstations

EM data to FEX

Hadronic data to FEX

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2 3

Can extract Tile tower sums from:1.Tile receiver stations2.PreProcessor modules3.JEM modules in JEP

Tile tower“DPS”

Considerations

Latency Dynamic range

Current L1Calo towers have 8 bit dynamic range with 1GeV/LSB

Would like 9 or 10 bits, if possible Cost to implement Risk of disruption to existing system

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Option 1: Tile Rx stations

Signals extracted at arrival point in USA15, so latency cost is minimal

Must build a new system to digitize and process analog signals No constraints on dynamic range Cost is high – essentially need to build new

receiver and PreProcessor systems High risk of disruption to current L1Calo:

Analog data path ahead of L1Calo rearranged Where do we fit the new systems that do this?

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Option 2: PreProcessor

New MCM (Phase 0) FPGA based tower processing Can drive higher-speed data to the

LVDS link driver card(blue arrows)

Replacement link card (Phase 1) Send tower data electrically to CP

and JEP (same as now) An FPGA and parallel-optic

transmitter (e.g. minipod) produce hadronic output to FEX

Fiber ribbon takes data from link card to an MTP/MPO output port (probably on front panel)

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nMCM prototype

Option 2: PreProcessor

Minimal latency: Essentially equal to option 1;

Can extend dynamic range: nMCM can drive outputs at higher rates, so

more bits per tower possible ‘Easy’ to get 9 bits, 10 bits probably possible

Relatively low cost nMCM will already exist A few (small) LVDS link boards Possibly need to replace some PreProcessor

mother boards (8 layers, low component count) Low disruption: Only upgrading existing boards

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Option 3: JEM Upgrade

Double-ratetower data fromupgraded PPM

(960 Mbit/s)

High-speed links to FEXfrom input cards to frontpanel (lowest latency)(hadronic tower sums)

Upgraded input cards

Option 3: JEM upgrade

Higher latency: Serial transmission from PPr to JEP adds

multiple BCs to latency Limited dynamic range:

BCMUX protocol consumes some bandwidth 9 bits possible (by removing parity), 10 bits

probably not possible Similar cost to Option 2

PreProcessor nMCM and link cards still get replaced (but not PPr mother boards?)

Plans to upgrade JEM daughter boards anyway Low disruption: Again, similar to Option 2

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L1Calo does not favor option 1

Significant risk of disrupting the current analog data path to L1Calo

The proposed new system would have essentially the same functinality as the existing L1Calo PreProcessor And where does it all fit?

No latency advantage over the PreProcessor And highest cost

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Option 2 favored over 3

Lower latency Fewer boards in the hardware chain

Everything on the PreProcessor Easier to expand/change dynamic range When would we use option 3?

Only if we can’t get optical data out of the PreProcessor directly.

Options being considered…no show-stoppers seen yet

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