ALTERA MAX+PLUS II NOTES - Pearson...

Copyright © 2010 by Gregory L. Moss 1

QUARTUS NOTES by Gregory L. Moss

Schematic capture of maxplus2 functions page 2

Drawing signal buses page 3

Sequential circuit simulation page 5

Schematic capture of megafunctions page 6

Simulation of state machines page 12

Measuring time intervals in simulations page 14

Clock frequency divider page 18


Schematic capture of maxplus2 functions

Many standard IC chips have been designed that contain common types of logic functions such as decoders, encoders, multiplexers, adders, registers, and counters. These have been used for many years to more easily and quickly design more complex logic systems. Quartus II provides an extensive set of pre-designed blocks called Maxplus2 functions that duplicate many of these common logic functions. Maxplus2 functions can be used in design files as easily as gates and flip-flops. Most of these functions are named with the equivalent standard 74-series part number. Functional descriptions and operational information on 74XXX macrofunctions can be obtained from the data sheets for the equivalent standard part devices. Altera has also defined several additional useful functions. The desired function is selected with the Symbol dialog box (click the Symbol Tool button or double-click the left mouse button anywhere in the drawing area). Open the set of folders for libraries, others, and maxplus2 and select the desired function from the list. Click OK. Place and wire all devices in the schematic as you did for gates and flip-flops.


Drawing signal buses

An individual signal line is called a Node line. Signal lines can be grouped together in buses for convenience. A bus is essentially an array of signal lines that are related to one another. Input signals contained in a bus can be “ripped” (split) out into individual signal lines, and individual output logic signals can be merged into a bus. A wide solid line indicates a bus in a bdf file. To create a bus, toggle the Orthogonal Bus Tool button on and draw using the cursor. If you start drawing a wiring line from a bus, it will automatically be drawn as a bus (wide line). If instead, you start drawing a wiring line from an individual signal, it will automatically be drawn as an individual signal line (narrow line). A drawn line can be changed from a Node line to a Bus line and vice versa by selecting the line and clicking the right mouse button to open the menu. Choose the desired line type from the menu and the highlighted line width will change appropriately.

A bus must be labeled if it is split or merged. A bus does not have to be labeled if there are no individual signals broken out of the bus. A bus label has a group name that consists of the bus identifier followed by the numerical signal range in brackets, such as Q[3..0]. The signal range indicates the labels for the individual signals going into or coming out of the bus. The range of numbers also will indicate the width of the bus (i.e., number of signals contained in the bus). The individual signal lines going into or coming out of a bus must also be identified with the desired individual signal name, such as Q[3] or Q[2], etc. To label buses and signal lines, click the left mouse button while pointing at the line and then type the desired Bus or Node Name. Input and output ports that are connected to a labeled bus should have a “PIN_NAME” that is the same as the bus label. Buses and Nodes may be labeled with names that are different than the pinstub labels inside the symbols they are connected to. Connections between signals in a bus and a group pinstub are made in the order specified by the range order inside the respective brackets. Buses can also be merged into (or split from) larger buses. Symbols for logic blocks that are defined with group inputs or group outputs will be drawn with ports represented as buses. Be very careful in labeling buses or signal lines. Any Node or Bus with the same name will be connected (shorted) together.


Sequential circuit simulation

Sequential circuit simulation is performed the same way as it is for combinational circuits. The Overwrite Clock waveform button can be used to automatically create the pattern for a clock input. Select (highlight) the desired waveform (clock) and click the Overwrite Clock button. The Clock dialog box will automatically choose a clock period equal to the specified Grid Size for the Vector Waveform File. Click OK. You can specify the frequency for a clock input by first setting the grid size equal to the period for the desired clock signal or you can specify the clock period in the Clock dialog.

Overwrite Clock button


Schematic capture of megafunctions

Useful Megafunctions for Beginners Arithmetic Gates Storage

LPM_ADD_SUB LPM_AND, LPM_INV, LPM_OR, LPM_XOR LPM_FF LPM_COMPARE LPM_CONSTANT LPM_LATCH LPM_COUNTER LPM_DECODE LPM_SHIFTREG LPM_MUX

To enter a megafunction module into a BDF file, double-click the MegaWizard Plug-In Manager in the Tasks Pane.

Select “Create a new custom megafunctions variation” and click Next.


Open the appropriate megafunction category folder from the list on the left & select the desired megafunction. The example below is an adder/subtractor megafunction from the Arithmetic folder. The correct device family should be identified. Choose an output file type (any HDL can be used). Type a unique filename for this output file. Click Next to continue with the setup for this megafunction. The details will depend on the function type.


The final MegaWizard dialog page is the Summary. Make sure the Quartus II symbol file is checked. Click Finish.


When finished defining the megafunction, double-click in the Block Editor drawing window to open the Symbol dialog. Open the Project folder and select the file for this megafunction. Click OK & place symbol in the drawing.


You must let Quartus know that this megafunction design file should be included in the current project. Double-click the “Add/Remove Files in Project” task in the Task Pane.


Click the Add All button to add megafunction design files that are located in the current project folder. or Click the Browse button to locate the megafunction design file from other

Click OK when all other design files have been added to the project.

project folders. Select the desired megafunction design file and click the Open button to return with the File name to the Settings dialog. Click the Add button.

Add All Browse


Simulation of state machines

The operation of a “buried” state machine can be included in the simulation of a logic circuit. The states for a state machine may be specified by name only. To insert the state machine in the vwf, select the “Design Entry (all names)” Filter option in the Node Finder and click list. A state machine name will be identified by a “handle” labeled “s.” Select the machine’s name and click OK. In the Insert Node or Bus dialog box, the Name for the selected state machine should be listed. The Type should be “MACHINE”, the Value should be “Enum” (abbreviation for enumerated, which means specified by name only), and Binary for Radix. Click OK. The state machine will be added to the waveform vector file.


Vector Waveform File for State Machine Design

Simulation Report for State Machine Simulation


Measuring time intervals in simulations

It is very easy to measure time intervals in Quartus simulation. Grab the handle at the top of the Master Time Bar and position it accurately at the beginning of the time period to be measured. You will need to zoom in a few times to align it accurately. Then zoom back out again, click the right mouse button to open the menu, select Time Bar, and choose Insert Time Bar. Enter a Time value that is close to the end of your desired time interval in the Insert Time Bar dialog box and click OK. Again using the handle for the new time bar, align the cursor at the end of the time period to be measured. Zoom in several times to accurately position the second time bar. The time difference between the two cursors will be given above the second time bar’s handle. An accurate measurement is dependent upon accurate placement of the two time bars.


Turn off “snap to grid” for Time Bar positioning


Clock frequency divider

Many CPLD/FPGA development boards have clock signal generator circuits built on the board for your convenience. The clock output frequencies, however, might be higher than desired to clock another design being tested. Check the manual for your CPLD/FPGA development board to determine what clocking frequencies might be produced on-board. This procedure illustrates how to create a simple clock frequency divider using a Quartus lpm_counter megafunction. It is important to note that we can only use this technique to divide a given clock signal by integer values. We cannot produce just any clock frequency out, but we might be able to create a signal frequency that is “close enough” to a desired frequency. Be sure to check the design specifications!

For this example, we will assume that our FPGA development board has a 50 MHz clock signal available. This will be the clock input signal to the lpm_counter. Next calculate the necessary “divide-by” factor to obtain the desired clocking frequency that will be used to drive another logic circuit. The divide-by factor will be the required modulus for the lpm_counter. Let’s say that our specification called for a 10 kHz clocking frequency. The calculation is:

modulus = freqclock_in ÷ freqclock_out

= 50MHz ÷ 10kHz = 5000

Thus, we will need a mod-5000 counter to obtain the desired output frequency. Next determine the number of counter bits necessary to create a mod-5000 counter. The simplest count sequence for the mod-5000 would be 0 to 4999 so the largest binary number is 1001110000111 (or 138716). This indicates that we will need a 13-bit counter for our frequency divider. The most significant counter bit q[12] will produce one waveform cycle for every 5000 input clock cycles. The frequency of q[12] will be 1/5000 of the frequency of the input clock signal.

Use the Quartus MegaWizard to create the desired counter. Choose lpm_counter from the arithmetic library folder. The output file type does not matter for this application so we will arbitrarily use AHDL. Continue through the wizard parameter settings dialogs until you reach “Finish” & generate the Block Symbol File (bsf). Place the lpm_counter symbol and complete the wiring as shown below. Add the lpm_counter design file to the current project (“Add/Remove Files in Project” task). If we connect the 50 MHz signal to clock, then clkout should be 10 kHz. If we create a symbol for this block, we can add this design file to other projects.

ALTERA MAX+PLUS II NOTES - Pearson...

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