ALTERA MAX10 Development & Education Board (DE10-Lite)

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5 5 4 4 3 3 2 2 1 1 D D C C B B A A ALTERA MAX10 Development & Education Board (DE10-Lite) CONTENT 1 Cover Page PAGE PAGE CONTENT 2 3 4 5 6 7 8 9 10 11 12 13 14 Block Diagram MAX 10 Bank 1 & 2 MAX 10 Bank 3 & 4 MAX 10 Bank 5 & 6 MAX 10 Bank 7 & 8 MAX 10 Clocks MAX 10 Configuration 15 16 17 18 19 20 21 22 23 24 25 26 Power - 5V, 1.2V Power - 1.8V, 2.5V, 3.3V MAX10 Ground MAX10 Decoupling MAX10 Power SDRAM GPIO and Arduino Interface LED, 7'Seg, User IO VGA and Accelerometer USB Blaster Title Size Document Number Rev Date: Sheet of Copyright (c) 2016 by Terasic Inc. Taiwan. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved. Cover Page A1 DE10-Lite B 1 18 Monday, September 19, 2016 Title Size Document Number Rev Date: Sheet of Copyright (c) 2016 by Terasic Inc. Taiwan. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved. Cover Page A1 DE10-Lite B 1 18 Monday, September 19, 2016 Title Size Document Number Rev Date: Sheet of Copyright (c) 2016 by Terasic Inc. Taiwan. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved. Cover Page A1 DE10-Lite B 1 18 Monday, September 19, 2016

Transcript of ALTERA MAX10 Development & Education Board (DE10-Lite)

5

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D D

C C

B B

A A

ALTERA MAX10 Development & Education Board (DE10-Lite)CONTENT

1 Cover PagePAGE PAGE CONTENT

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1011121314

Block DiagramMAX 10 Bank 1 & 2MAX 10 Bank 3 & 4MAX 10 Bank 5 & 6MAX 10 Bank 7 & 8MAX 10 ClocksMAX 10 Configuration

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1920212223242526

Power - 5V, 1.2VPower - 1.8V, 2.5V, 3.3V

MAX10 GroundMAX10 Decoupling

MAX10 Power

SDRAMGPIO and Arduino InterfaceLED, 7'Seg, User IOVGA and Accelerometer

USB Blaster

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Cover Page A1

DE10-Lite

B

1 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Cover Page A1

DE10-Lite

B

1 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Cover Page A1

DE10-Lite

B

1 18Monday, September 19, 2016

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Block Diagram A1

DE10-Lite

B

2 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Block Diagram A1

DE10-Lite

B

2 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Block Diagram A1

DE10-Lite

B

2 18Monday, September 19, 2016

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAX10 Bank 1 & 2

VCCIO = 2.5V

VCCIO = 2.5V

VCCIO = 3.3V

Analog input interface

VGA

ADC1IN3ADC1IN4

ADC1IN6ADC1IN5

ADC1IN7ADC1IN8

ADC1IN1ADC1IN2

VGA_R1

VGA_G2VGA_G3

VGA_VSVGA_B0

VGA_B3VGA_HS

VGA_B2

VGA_G0

VGA_G1VGA_B1

ADC1IN[8..1]13

VGA_R[3..0]15

VGA_G[3..0]15

VGA_B[3..0]15

VGA_HS15

VGA_VS15

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

MAX 10 Bank 1 & 2 A1

DE10-Lite

B

3 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

MAX 10 Bank 1 & 2 A1

DE10-Lite

B

3 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

MAX 10 Bank 1 & 2 A1

DE10-Lite

B

3 18Monday, September 19, 2016

MAX 10 LEFT BANKS

BANK-2BANK-1A

BANK-1B

10M50DAF484

U5A

DIFFIO_RX_L1N/ADC1IN1F5

DIFFIO_RX_L1P/ADC1IN2F4

DIFFIO_RX_L2N/ADC2IN1E4

DIFFIO_RX_L2P/ADC2IN8E3

DIFFIO_RX_L3N/ADC1IN3J8

DIFFIO_RX_L3P/ADC1IN4J9

DIFFIO_RX_L4N/ADC2IN3G4

DIFFIO_RX_L4P/ADC2IN4F3

DIFFIO_RX_L5P/ADC1IN6H3

DIFFIO_RX_L5N/ADC1IN5J4

DIFFIO_RX_L6N/ADC2IN5H4

DIFFIO_RX_L6P/ADC2IN6G3

DIFFIO_RX_L7N/ADC1IN7K5

DIFFIO_RX_L7P/ADC1IN8K6

DIFFIO_RX_L8P/ADC2IN2J3

DIFFIO_RX_L8N/ADC2IN7K4

DIFFIO_RX_L15NK8

VREFB1N0C1

DIFFIO_RX_L19NK2

DIFFIO_RX_L19PL2

DIFFIO_RX_L23NG1

DIFFIO_RX_L21PF2

DIFFIO_RX_L23PF1

DIFFIO_RX_L21NE1

DIFFIO_RX_L24NM4

DIFFIO_RX_L24PM3

DIFFIO_RX_L25NK1

DIFFIO_RX_L25PL1

DIFFIO_RX_L16PD2

IO_BANK1D1

DIFFIO_RX_L29NP4

DIFFIO_RX_L29PP5

DIFFIO_RX_L37NN3

DIFFIO_RX_L37PN2

DIFFIO_RX_L39NR4

DIFFIO_RX_L39PR5

DIFFIO_RX_L40NT1

DIFFIO_RX_L40PT2

DIFFIO_RX_L41NN8

DIFFIO_RX_L41PN9

DIFFIO_RX_L42NP1

DIFFIO_RX_L42PN1

DIFFIO_RX_L43NT3

DIFFIO_RX_L43PU2

DIFFIO_RX_L44NU1

DIFFIO_RX_L44PV1

DIFFIO_RX_L45NU4

DIFFIO_RX_L45PU5

DIFFIO_RX_L46NU3

DIFFIO_RX_L46PV3

DIFFIO_RX_L47NP8

DIFFIO_RX_L47PR7

DIFFIO_RX_L48NW1

DIFFIO_RX_L48PW2

DIFFIO_RX_L60NR1

DIFFIO_RX_L60PR2

VREFB2N0M2

IO_BANK2M1

DIFFIO_RX_L16ND3

DIFFIO_RX_L20NL8

DIFFIO_RX_L20PL9

DIFFIO_RX_L22NH1

DIFFIO_RX_L22PJ1

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAX10 Bank 3 & 4

VCCIO = 3.3V VCCIO = 3.3V

GPIO 0

Arduino Digital Interface

Digital Accelerometer

VGA

Arduino_IO3GPIO_22Arduino_IO4

GPIO_35GPIO_29GPIO_27

GPIO_28GPIO_26

Arduino_IO5GPIO_21

GPIO_9

GPIO_3

VGA_R0

VGA_R3VGA_R2

GPIO_1GPIO_7GPIO_5

GPIO_25GPIO_23GPIO_34

GPIO_10

GPIO_32

GPIO_8

GPIO_33GPIO_31GPIO_30

GPIO_6

Arduino_IO0

GPIO_4

Arduino_IO1Arduino_IO2GPIO_24

GPIO_19GPIO_17GPIO_20GPIO_18

GSENSOR_INT2

GSENSOR_CS_n

Arduino_IO7

Arduino_IO13

Arduino_IO14

GSENSOR_SDOGSENSOR_SDI

GSENSOR_INT1

Arduino_IO10

Arduino_IO9

Arduino_IO11

Arduino_IO12

Arduino_IO8Arduino_IO15

Arduino_IO6

GPIO_13

GPIO_11

GPIO_12

GPIO_16

GSENSOR_SCLK

GPIO_14GPIO_15

GPIO_[35..0]7,13

Arduino_IO[15..0]13

GSENSOR_INT115

GSENSOR_SCLK15

GSENSOR_CS_n15

GSENSOR_INT215

GSENSOR_SDI15

GSENSOR_SDO15

VGA_R[3..0]15

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

MAX 10 Bank 3 & 4 A1

DE10-Lite

B

4 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

MAX 10 Bank 3 & 4 A1

DE10-Lite

B

4 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

MAX 10 Bank 3 & 4 A1

DE10-Lite

B

4 18Monday, September 19, 2016

BANK-3 BANK-4

MAX 10 BOTTOM BANKS

10M50DAF484

U5B

DIFFIO_RX_B10NY7

DIFFIO_RX_B10PY8

DIFFIO_RX_B12NAB2

DIFFIO_RX_B12PAB3

DIFFIO_RX_B14NY3

DIFFIO_RX_B14PY4

DIFFIO_RX_B17NAA5

DIFFIO_RX_B17PAB5

DIFFIO_RX_B19NAB6

DIFFIO_RX_B19PAB7

DIFFIO_RX_B21NAA8

DIFFIO_RX_B21PAB8

DIFFIO_RX_B23NAA9

DIFFIO_RX_B23PAB9

DIFFIO_RX_B2NV4

DIFFIO_RX_B2PV5

DIFFIO_RX_B4NY1

DIFFIO_RX_B4PY2

DIFFIO_RX_B6NAA1

DIFFIO_RX_B6PAA2

DIFFIO_RX_B8NY5

DIFFIO_RX_B8PY6

DIFFIO_TX_RX_B11NW9

DIFFIO_TX_RX_B11PW10

DIFFIO_TX_RX_B13NW7

DIFFIO_TX_RX_B13PW8

DIFFIO_TX_RX_B15NR10

DIFFIO_TX_RX_B15PP10

DIFFIO_TX_RX_B16NAA6

DIFFIO_TX_RX_B16PAA7

DIFFIO_TX_RX_B1NW5

DIFFIO_TX_RX_B1PW6

DIFFIO_TX_RX_B22NY10

DIFFIO_TX_RX_B22PAA10

DIFFIO_TX_RX_B3NU6

DIFFIO_TX_RX_B3PU7

DIFFIO_TX_RX_B5NW4

DIFFIO_TX_RX_B5PW3

DIFFIO_TX_RX_B7NV7

DIFFIO_TX_RX_B7PV8

DIFFIO_TX_RX_B9NR9

DIFFIO_TX_RX_B9PP9

VREFB3N0AA3

IO_BANK3AB4

DIFFIO_RX_B25NW11

DIFFIO_RX_B25PY11

DIFFIO_RX_B27NAB10

DIFFIO_RX_B27PAB11

DIFFIO_RX_B29NAB12

DIFFIO_RX_B29PAB13

DIFFIO_RX_B35NW12

DIFFIO_RX_B35PW13

DIFFIO_RX_B38NAA14

DIFFIO_RX_B38PAB15

DIFFIO_RX_B40NAA15

DIFFIO_RX_B40PY16

DIFFIO_RX_B42NAB16

DIFFIO_RX_B42PAA16

DIFFIO_RX_B44NAB19

DIFFIO_RX_B44PAB20

DIFFIO_RX_B46NAA19

DIFFIO_RX_B46PY18

DIFFIO_RX_B50NAB21

DIFFIO_RX_B50PAA20

DIFFIO_RX_B58NAB17

DIFFIO_RX_B58PAB18

DIFFIO_TX_RX_B24NV11

DIFFIO_TX_RX_B24PV12

DIFFIO_TX_RX_B26NR12

DIFFIO_TX_RX_B26PP12

DIFFIO_TX_RX_B28NAA11

DIFFIO_TX_RX_B28PAA12

DIFFIO_TX_RX_B34NV13

DIFFIO_TX_RX_B34PW14

DIFFIO_TX_RX_B36NR13

DIFFIO_TX_RX_B36PP13

DIFFIO_TX_RX_B37NY13

DIFFIO_TX_RX_B37PY14

DIFFIO_TX_RX_B39NV14

DIFFIO_TX_RX_B39PW15

DIFFIO_TX_RX_B41NU15

DIFFIO_TX_RX_B41PV16

DIFFIO_TX_RX_B43NAA17

DIFFIO_TX_RX_B43PY17

DIFFIO_TX_RX_B45NV15

DIFFIO_TX_RX_B45PW16

DIFFIO_TX_RX_B49NY19

DIFFIO_TX_RX_B49PW18

VREFB4N0AA13

IO_BANK4AB14

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAX10 Bank 5 & 6

VCCIO = 3.3V VCCIO = 3.3V

SDRAM

LED

SWITCH

KEY

7-segment Display

DRAM_ADDR4DRAM_ADDR2DRAM_ADDR3DRAM_ADDR0DRAM_DQ5DRAM_DQ4DRAM_DQ6DRAM_ADDR1DRAM_DQ0DRAM_DQ1DRAM_CS_NDRAM_WE_NDRAM_LDQMDRAM_DQ7

DRAM_BA1DRAM_BA0DRAM_ADDR5DRAM_ADDR6DRAM_ADDR12DRAM_ADDR10DRAM_RAS_NDRAM_CAS_N

DRAM_DQ3DRAM_DQ2

DRAM_CKEDRAM_DQ8DRAM_ADDR8DRAM_ADDR7DRAM_ADDR11DRAM_ADDR9

DRAM_UDQM

DRAM_DQ10DRAM_DQ11

DRAM_DQ9DRAM_DQ14DRAM_DQ13DRAM_DQ15DRAM_DQ12

HEX43

HEX45

HEX35HEX34

HEX41HEX42HEX40

HEX44

HEX36HEX47

HEX20

HEX51

HEX32

HEX12HEX11

HEX50

HEX23

HEX26HEX24

HEX54HEX53

HEX25

HEX57

HEX46

HEX52

HEX30

HEX37

HEX56

HEX31HEX55

DRAM_ADDR[12..0]12

DRAM_CKE12 DRAM_LDQM12 DRAM_UDQM12

DRAM_WE_N12 DRAM_CAS_N12 DRAM_RAS_N12 DRAM_CS_N12 DRAM_BA012 DRAM_BA112

DRAM_DQ[15..0]12

LEDR[9..0]14

SW[9..0]14

KEY[1..0]14

HEX4[7..0]14

HEX5[7..0]14

HEX1[7..0]14

HEX2[7..0]14

HEX3[7..0]14

HEX0[7..0]14

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

MAX 10 Bank 5 & 6 A1

DE10-Lite

B

5 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

MAX 10 Bank 5 & 6 A1

DE10-Lite

B

5 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

MAX 10 Bank 5 & 6 A1

DE10-Lite

B

5 18Monday, September 19, 2016

BANK-5 BANK-6

MAX 10 RIGHT BANKS

10M50DAF484

U5C

DIFFIO_RX_R19NU19

DIFFIO_RX_R19PV18

DIFFIO_RX_R1N/RDNU17 DIFFIO_RX_R1P/RUPU18

DIFFIO_RX_R20NW22

DIFFIO_RX_R20PY22

DIFFIO_RX_R21NW20

DIFFIO_RX_R21PW19

DIFFIO_RX_R22NY21

DIFFIO_RX_R22PY20

DIFFIO_RX_R23NU20

DIFFIO_RX_R23PV20

DIFFIO_RX_R24NV22

DIFFIO_RX_R24PV21

DIFFIO_RX_R25N/DQ1RR14

DIFFIO_RX_R25P/DQ1RR15

DIFFIO_RX_R26NT22

DIFFIO_RX_R26PT21

DIFFIO_RX_R27N/DM1RT18

DIFFIO_RX_R27P/DQ1RT19

DIFFIO_RX_R28N/DQ1RR20

DIFFIO_RX_R28P/DQ1RT20

DIFFIO_RX_R29NU22

DIFFIO_RX_R29PU21

DIFFIO_RX_R2NAA22

DIFFIO_RX_R2PAA21

DIFFIO_RX_R30N/DQ1RP14

DIFFIO_RX_R30P/DQ1RP15

DIFFIO_RX_R31NN22

DIFFIO_RX_R31PP21

DIFFIO_RX_R32N/DQSN1RP18

DIFFIO_RX_R32P/DQS1RR18

DIFFIO_RX_R33N/DQ1RP20

DIFFIO_RX_R33P/DQ1RP19

DIFFIO_RX_R34NL22

DIFFIO_RX_R34PM21

DIFFIO_RX_R35NM22

DIFFIO_RX_R35PN21

IO_BANK5R22 VREFB5N0P22

DIFFIO_RX_R39NH21

DIFFIO_RX_R39PH22

DIFFIO_RX_R41NJ21

DIFFIO_RX_R41PJ22

DIFFIO_RX_R42NG19

DIFFIO_RX_R42PG20

DIFFIO_RX_R43NF22

DIFFIO_RX_R43PG22

DIFFIO_RX_R44N/DQ2RM14

DIFFIO_RX_R44P/DQ2RM15

DIFFIO_RX_R45NE21

DIFFIO_RX_R45PE22

DIFFIO_RX_R46N/DM2RN19

DIFFIO_RX_R46P/DQ2RN18

DIFFIO_RX_R47P/DQ2RM20

DIFFIO_RX_R47N/DQ2RN20

DIFFIO_RX_R48NF20

DIFFIO_RX_R48PF21

VREFB6N0D21

DIFFIO_RX_R49PD22

DIFFIO_RX_R51N/DQ2RL18

DIFFIO_RX_R51P/DQ2RM18

DIFFIO_RX_R52N/DQ2RL20

DIFFIO_RX_R52P/DQ2RL19

DIFFIO_RX_R53NF18

DIFFIO_RX_R53PE19

DIFFIO_RX_R54NE20

DIFFIO_RX_R54PF19

DIFFIO_RX_R55N/DQSN3RK15

DIFFIO_RX_R55P/DQS3RK14

DIFFIO_RX_R56ND19

DIFFIO_RX_R56PC20

DIFFIO_RX_R57N/DQ3RJ18

DIFFIO_RX_R57P/DQ3RK18

DIFFIO_RX_R58N/DQ3RK20

DIFFIO_RX_R58P/DQ3RK19

DIFFIO_RX_R59NE17

DIFFIO_RX_R59PF17

DIFFIO_RX_R60NB21

DIFFIO_RX_R60PB22

DIFFIO_RX_R61N/DM3RJ15

DIFFIO_RX_R61P/DQ3RJ14

DIFFIO_RX_R62NA21

DIFFIO_RX_R62PB20

DIFFIO_RX_R63N/DQ3RH18

DIFFIO_RX_R63P/DQ3RH19

DIFFIO_RX_R64N/DQ3RH20

DIFFIO_RX_R64P/DQ3RJ20

DIFFIO_RX_R70N/CK#_6E18

DIFFIO_RX_R70P/CK_6D18

DIFFIO_RX_R49NC22

IO_BANK6C21

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAX10 Bank 7 & 8

VCCIO = 3.3V VCCIO = 2.5V

7-segment Display

LED

SWITCH

KEY

Arduino Digital Interface

HEX07LEDR6

SW8

HEX14HEX15

HEX17HEX13

LEDR5HEX00

SW7HEX01HEX04

LEDR7

LEDR4

SW6SW2SW3

SW4

LEDR2LEDR8SW0SW1LEDR9SW5

KEY0LEDR1HEX06HEX05

LEDR3KEY1LEDR0

HEX16HEX10HEX27

HEX22

HEX21

HEX02HEX03

HEX33

SW9Arduino_Reset_n

HEX1[7..0]14

HEX2[7..0]14

HEX3[7..0]14

HEX0[7..0]14

HEX4[7..0]14

HEX5[7..0]14

LEDR[9..0]14

SW[9..0]14

KEY[1..0]14

Arduino_Reset_n13

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

MAX 10 Bank 7 & 8 A1

DE10-Lite

B

6 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

MAX 10 Bank 7 & 8 A1

DE10-Lite

B

6 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

MAX 10 Bank 7 & 8 A1

DE10-Lite

B

6 18Monday, September 19, 2016

BANK-7 BANK-8

MAX 10 TOP BANKS

10M50DAF484

U5D

DIFFIO_RX_T10NA17

DIFFIO_RX_T10PA18

DIFFIO_RX_T15NC15

DIFFIO_RX_T15PC16

DIFFIO_RX_T16NA16

DIFFIO_RX_T16PB16

DIFFIO_RX_T17NJ13

DIFFIO_RX_T17PH14

DIFFIO_RX_T18NC13

DIFFIO_RX_T18PC14

DIFFIO_RX_T19NB14

DIFFIO_RX_T19PA14

DIFFIO_RX_T1NE15

DIFFIO_RX_T1PE16

DIFFIO_RX_T20NE13

DIFFIO_RX_T20PD14

DIFFIO_RX_T21PE12

DIFFIO_RX_T21ND13

DIFFIO_RX_T22NJ12

DIFFIO_RX_T22PH13

DIFFIO_RX_T23NA12

DIFFIO_RX_T23PA13

DIFFIO_RX_T24ND12

DIFFIO_RX_T24PC12

DIFFIO_RX_T25NA10

DIFFIO_RX_T25PA11

DIFFIO_RX_T26NC10

DIFFIO_RX_T26PC11

DIFFIO_RX_T27NB11

DIFFIO_RX_T27PB12

DIFFIO_RX_T28NJ11

DIFFIO_RX_T28PH12

DIFFIO_RX_T31NB8

DIFFIO_RX_T31PA9

DIFFIO_RX_T2NC17

DIFFIO_RX_T2PD17

DIFFIO_RX_T30NC9

DIFFIO_RX_T30PB10

DIFFIO_RX_T29PA7

DIFFIO_RX_T29NA8

DIFFIO_RX_T5NF15

DIFFIO_RX_T5PF16

DIFFIO_RX_T6NB19

DIFFIO_RX_T6PC19

DIFFIO_RX_T7NB17

DIFFIO_RX_T7PC18

DIFFIO_RX_T8NA19

DIFFIO_RX_T8PA20

DIFFIO_RX_T9NE14

DIFFIO_RX_T9PD15

IO_BANK7A15 VREFB7N0B15

DIFFIO_RX_T39NC7

DIFFIO_RX_T39PC8

DIFFIO_RX_T41NA6

DIFFIO_RX_T41PB7

DIFFIO_RX_T42PD8

DIFFIO_RX_T43NA4

DIFFIO_RX_T43PA5

DIFFIO_RX_T44NE9

DIFFIO_RX_T45PA2

DIFFIO_RX_T45NA3

DIFFIO_RX_T46PB3

DIFFIO_RX_T46NB4

DIFFIO_RX_T49ND5

DIFFIO_RX_T49PC5

DIFFIO_RX_T51NB1

DIFFIO_RX_T51PB2

DIFFIO_RX_T53PC3

VREFB8N0D7

IO_BANK8C6

DIFFIO_RX_T47PB5

DIFFIO_RX_T47NC4

DIFFIO_RX_T48PE8

DIFFIO_RX_T53NC2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAX10 Clock

VCCIO = 3.3V

VCCIO = 3.3V

VCCIO = 3.3V

VCCIO = 2.5V

Default: 50MHz

Default: 50MHz

Default: 24MHz

Default: 24MHz

Default : I2C Address 0xDA/0xDB

CAD Note:Place near IC power pin

CAD Note:Place near pin 3 and 5(C3 & C322)

Default: 10MHz

Default: 50MHz

Default: 50MHz

VCCIO = 3.3V

GPIO 0

SDRAM

UBT_CLK_24

ADC_CLK_10

ADC_CLK_10

DRAM_CLK

GPIO_2GPIO_0

MAX10_CLK2_50

MAX10_CLK1_50

MAX10_CLK2_50

MAX10_CLK1_50

VCC1P8 VCC3P3

VCC3P3

UBT_CLK_2418

GPIO_[35..0]4,13

DRAM_CLK12

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

MAX 10 Clocks A1

DE10-Lite

B

7 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

MAX 10 Clocks A1

DE10-Lite

B

7 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

MAX 10 Clocks A1

DE10-Lite

B

7 18Monday, September 19, 2016

C530.1u10V

C84.7u6.3V

C9 4p

DNI6.3V

R17 18.2

C560.1u10V

R10 18.2C11 4p

DNI6.3V

C520.1u10V

R9 18.2

L3 220 ohm, 0.4A

Y124.00MHz

13

24

C511n50V

C500.01u50V

U3

CDCE937PWRG4

Xin/Clk1

Xout20

S02

S1/SDA19

S2/SCL18

GN

D5

GN

D9

GN

D16

Vctrl4

VDD

3

Vddo

ut6

Vddo

ut10

Vddo

ut13

Y117

Y215

Y314

Y47

Y58

Y612

Y711

BANK-2

MAX 10 CLOCK

BANK-3

BANK-4

BANK-6

BANK-8

10M50DAF484

U5E

DIFFIO_RX_L28N/CLK0NN4

DIFFIO_RX_L28P/CLK0PN5

DIFFIO_RX_L36N/CLK1NM8

DIFFIO_RX_L36P/CLK1PM9

DIFFIO_TX_RX_B18N/CLK6NV9

DIFFIO_TX_RX_B18P/CLK6PV10

DIFFIO_TX_RX_B20N/CLK7NR11

DIFFIO_TX_RX_B20P/CLK7PP11

DIFFIO_RX_R38N/CLK2NN15

DIFFIO_RX_R38P/CLK2PN14

DIFFIO_RX_R40N/CLK3NK21

DIFFIO_RX_R40P/CLK3PK22

DIFFIO_RX_T38N/CLK4NE10

DIFFIO_RX_T38P/CLK4PE11

DIFFIO_RX_T40P/CLK5PJ10

DIFFIO_RX_T40N/CLK5NH11

DIFFIO_RX_L38N/DPCLK0P3

DIFFIO_RX_L38P/DPCLK1R3

DIFFIO_RX_L59N/PLL_L_CLKOUTNT5

DIFFIO_RX_L59P/PLL_L_CLKOUTPT6

DIFFIO_TX_RX_B57N/PLL_B_CLKOUTNW17

DIFFIO_TX_RX_B57P/PLL_B_CLKOUTPV17

DIFFIO_RX_R50N/DPCLK2/DQSn2RL15

DIFFIO_RX_R50P/DPCLK3/DQS2RL14

DIFFIO_RX_R69N/PLL_R_CLKOUTNG17

DIFFIO_RX_R69P/PLL_R_CLKOUTPH17

DIFFIO_RX_T52N/PLL_T_CLKOUTNE6

DIFFIO_RX_T52P/PLL_T_CLKOUTPD6

R19 4.7K

R57 18.2

R18 4.7K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAX10 ConfigurationJTAG Interface

VCCIO = 2.5VVCCIO = 2.5V

Design Note:Optional termination resistorfor JTAG TCK

CAD Note:Place near JTAG TCK pin

FPGA CONFIG

Boot Select

BOOT SelectDefault Disable (Jumper Open)

OPEN = configuration image 0 (Low)SHORT = configuration image 1 (High)

JTAG_ENJTAG_TCK

JTAG_TDOJTAG_TMS

JTAG_TDI

CONFIG_SELNCONFIG

NSTATUSCONF_DONE

VCC2P5

VCC2P5 VCC2P5VCC2P5 VCC2P5 VCC2P5

JTAG_TDI18

JTAG_TCK18

JTAG_TMS18

JTAG_TDO18JTAG_EN18

NCONFIG18

NSTATUS18

CONF_DONE18

CONFIG_SEL18

Title

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Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

MAX 10 Configuration A1

DE10-Lite

B

8 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

MAX 10 Configuration A1

DE10-Lite

B

8 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

MAX 10 Configuration A1

DE10-Lite

B

8 18Monday, September 19, 2016

R600DNI

R2410KDNI

R6810K

JP5

1X2 HeaderDNI

12

R7410K

R6310K

MAX 10 Configuration

BANK-1B BANK-8

10M50DAF484

U5F

DIFFIO_RX_L15P/JTAGENK9

DIFFIO_RX_L17P/TCKG2

DIFFIO_RX_L17N/TMSH2

DIFFIO_RX_L18N/TDIL4

DIFFIO_RX_L18P/TDOM5

DIFFIO_RX_T42N/DEV_CLRND9

DIFFIO_RX_T44P/DEV_OED10

NCONFIGH9

CONFIG_SELH10

DIFFIO_RX_T48N/CRC_ERRORF7

DIFFIO_RX_T50P/NSTATUSG9

DIFFIO_RX_T50N/CONF_DONEF8

R7810K

R7910K

R281K

C6112pDNI

R611K

R2310K

R6210K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAX10 Power

CAD Notes:Put the caps close to MAX10 pin.

Place filter close to VCCIO1A pins.

CAD Notes:Place the 10uF cap close to ferrite bead.Place the 0.1uF cap close to MAX10 pin.

CAD Notes:Place the 10uF cap close to ferrite bead.Place the 0.1uF cap close to MAX10 pin.

NC

ADC_VREF

REF_VCC2P5 ADC_VREF

VCC2P5_VCCADC

VCC1P2_VCC

VCC1P2_VCCD

VCC2P5_VCCA

VCC1P2_VDDADC

VCC2P5VCC2P5

VCC3P3

VCC2P5_VCCA

VCC2P5_VCCADC

VCC1P2_VDDADCVCC1P2_VCC

VCC1P2_VCCDVCC1P2_VCC

VCC2P5

VCC3P3

VCC3P3

VCC3P3

VCC3P3

VCC2P5_CORE

VCC2P5_CORE

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

MAX10 Power A1

DE10-Lite

B

9 18Monday, September 19, 2016

Title

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Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

MAX10 Power A1

DE10-Lite

B

9 18Monday, September 19, 2016

Title

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Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

MAX10 Power A1

DE10-Lite

B

9 18Monday, September 19, 2016

MAX 10 POWER

10M50DAF484

U5G

VCCN12

VCCN10

VCCM13

VCCM12

VCCM11

VCCL12

VCCL11

VCCL10

VCCK13

VCCK11

VCCD_PLL1T7

VCCD_PLL2G16

VCCD_PLL3G7

VCCD_PLL4U16

VCCA1R8

VCCA2H15

VCCA3H8

VCCA4T15

VCCINTJ7

VCCA_ADCH7

ADC_VREFH6

ANAIN1G5

ANAIN2J5

VCCIO1AL6

VCCIO1AK7

VCCIO1BM6

VCCIO1BL7

VCCIO2R6

VCCIO2P7

VCCIO2N7

VCCIO2N6

VCCIO3U9

VCCIO3U8

VCCIO3T9

VCCIO3T11

VCCIO3T10

VCCIO4U14

VCCIO4U12

VCCIO4U11

VCCIO4T13

VCCIO4T12

VCCIO5T17

VCCIO5R17

VCCIO5R16

VCCIO5P16

VCCIO5N16

VCCIO6N17

VCCIO6M17

VCCIO6L16

VCCIO6K17

VCCIO6K16

VCCIO6J17

VCCIO6H16

VCCIO7G14

VCCIO7G13

VCCIO7G12

VCCIO7F14

VCCIO7F12

VCCIO8G11

VCCIO8G10

VCCIO8F9

VCCIO8F11

C142

10u

C122

0.1u

C119

0.1u

L12 220ohm, 2.5A

C774.7u

L11 30ohm, 3A

L9

220 ohm, 0.4A300mA

C139

10u

C121

10u

C120

1u

C860.1u

L10 30ohm, 3A

C85

0.1u

C16

10u

R77 1

L4 30ohm, 3A

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAX10 Ground

1. Use REFGND as ground reference.2. Route analog input signal adjacent to AVSSREF as possible.

CAD Notes: Place this FB close to MAX10 ADC_VREF.

REFGND

Title

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Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

MAX10 Ground A1

DE10-Lite

B

10 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

MAX10 Ground A1

DE10-Lite

B

10 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

MAX10 Ground A1

DE10-Lite

B

10 18Monday, September 19, 2016

L13 30ohm, 3A

TP3

MAX 10 GROUND

10M50DAF484

U5H

GNDY9

GNDY15

GNDY12

GNDW21

GNDV6

GNDV2

GNDV19

GNDU13

GNDU10

GNDT8

GNDT4

GNDT16

GNDT14

GNDR21

GNDR19

GNDP6

GNDP2

GNDP17

GNDN13

GNDN11

GNDM7

GNDM19

GNDM16

GNDM10

GNDL5

GNDL21

GNDL17

GNDL13

DNUL3

GNDK3

GNDK12

GNDK10

GNDJ6

GNDJ2

GNDJ19

GNDJ16

GNDG8

GNDG6

GNDG21

GNDG18

GNDG15

GNDF13

GNDF10

GNDE7

GNDE2

GNDD4

GNDD20

GNDD16

GNDD11

GNDB9

GNDB6

GNDB18

GNDB13

GNDAB22

GNDAB1

GNDAA4

GNDAA18

GNDA22

GNDA1

NC2F6NC1E5

REFGNDH5

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAX10 Decoupling

CAD Note:Place capacitor near FPGA pins CAD Notes:

Place a 1uF cap close to each MAX10 VCCA pins.

CAD Notes:Place a 0.1uF cap close to each MAX10 VCCD pins.

CAD Notes:Place these caps close to MAX10 VCCIO2, VCCIO3, VCCIO4, VCCIO7 and VCCIO8 pins.

VCC1P2_VCC

VCC1P2_VCCD

VCC2P5_VCCA

VCC2P5

VCC3P3

Title

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Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

MAX10 Decoupling A1

DE10-Lite

B

11 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

MAX10 Decoupling A1

DE10-Lite

B

11 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

MAX10 Decoupling A1

DE10-Lite

B

11 18Monday, September 19, 2016

C126

1u

C73

0.1u

C104

10u

C111

22n

C108

10n

C95

10n

C74

0.1u

C1010.1u10V

C65

0.1u

C123

0.1u

C97

0.1u

C115

0.1u

C76

0.1u

C107

22n

C63

0.1u

C106

10n

C75

0.1u

C71

4.7u

C94

0.1u

C90

1u

C109

10n

C64

0.1u

C15

10u

C990.1u10V

C670.1u10V

C1130.1u10V

C72

0.1u

C70

0.1u

C156

10u

C110

1u

C1180.1u10V

C93

1u

C66

0.1u

C125

0.1u

C620.1u10V

C89

1u

C1170.1u10V

C92

1u

C88

0.1u

C69

0.1u

C116

0.1u

C114

0.1u

C91

1u

C98

4.7u

C87

0.1u

C68

0.1u

C1000.1u10V

C105

0.1u

C143

0.1u

C124

1u

C112

1u

C96

1u

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SDRAM

CAD Note:Place near IC power pin

DRAM_ADDR0

DRAM_ADDR3

DRAM_ADDR1DRAM_ADDR2

DRAM_ADDR10

DRAM_DQ0

DRAM_DQ5

DRAM_DQ3

DRAM_DQ6DRAM_DQ7

DRAM_DQ4

DRAM_DQ2DRAM_DQ1

DRAM_ADDR5

DRAM_ADDR12

DRAM_ADDR8

DRAM_ADDR6DRAM_ADDR7

DRAM_ADDR9

DRAM_ADDR4

DRAM_ADDR11 DRAM_DQ11

DRAM_DQ15

DRAM_DQ8

DRAM_DQ13

DRAM_DQ10DRAM_DQ9

DRAM_DQ12

DRAM_DQ14DRAM_CLK

DRAM_UDQM

DRAM_CKEDRAM_LDQM

DRAM_CAS_N

DRAM_BA0

DRAM_RAS_NDRAM_CS_N

DRAM_WE_N

DRAM_BA1DRAM_CKE

DRAM_CS_N

DRAM_CAS_NDRAM_RAS_N

DRAM_WE_N

VCC3P3

VCC3P3

VCC3P3

DRAM_ADDR[12..0]5

DRAM_DQ[15..0]5

DRAM_CLK7 DRAM_CKE5 DRAM_LDQM5 DRAM_UDQM5DRAM_WE_N5 DRAM_CAS_N5 DRAM_RAS_N5 DRAM_CS_N5DRAM_BA15

DRAM_BA05

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

SDRAM A1

DE10-Lite

B

12 18Monday, September 19, 2016

Title

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Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

SDRAM A1

DE10-Lite

B

12 18Monday, September 19, 2016

Title

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Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

SDRAM A1

DE10-Lite

B

12 18Monday, September 19, 2016

C1020.1u10V

C130.1u10V

R33 4.7K

RN13 4.7K1234 5

678

C1030.1u10V

C140.1u10V

U4

SDRAM 32Mx16

A023

A124

A225

A326

A429

A530

A631

A732

A833

A934

nCAS17

nRAS18

LDQM15

nWE16

nCS19

CKE37 CLK38

UDQM39

D02

D14

D25

D37

D48

D510

D611

D713

D842

D944

D1045

D1147

D1248

D1350

D1451

D1553

A1236

BA020

VDD

1

VDD

27VS

S28

VSS

41

A1022

VDD

Q3

VDD

Q9

VDD

Q43

VDD

Q49

VSSQ

6

VSSQ

12

VSSQ

46

VSSQ

52

A1135

BA121

VSS

54VD

D14

C270.1u10V

C250.1u10V

C120.1u10V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

JP8

Pin.1

JP2

Pin.1

JP3

Pin.1

JP7

Pin.1

JP4

Pin.1

Arduino Pin out

MOSIMISOSCK

SS

SCLSDA

Arduino Digital Interface

Arduino UNO Rev3

Analog input interface

TP1TP2

GPIO

Clock_inClock_in

GPIO

Arduino_Reset_n

Arduino_IO0Arduino_IO1Arduino_IO2Arduino_IO3Arduino_IO4Arduino_IO5Arduino_IO6Arduino_IO7

Arduino_IO8Arduino_IO9Arduino_IO10Arduino_IO11Arduino_IO12Arduino_IO13

ADC_IN0

Arduino_IO14Arduino_IO15

ADC_IN1ADC_IN2ADC_IN3ADC_IN4ADC_IN5

ADC_IN6

ADC_IN7

ADC_IN6

Arduino_IO12Arduino_IO11

Arduino_Reset_nArduino_IO13

Arduino_Reset_nArduino_IO15Arduino_IO14

GPIO_1GPIO_3GPIO_5GPIO_7GPIO_9

GPIO_11GPIO_13GPIO_15GPIO_17GPIO_19GPIO_21GPIO_23GPIO_25

GPIO_27GPIO_29GPIO_31GPIO_33GPIO_35

GPIO_32GPIO_34

GPIO_30GPIO_28GPIO_26

GPIO_8GPIO_6GPIO_4GPIO_2

GPIO_14

GPIO_10GPIO_12

GPIO_18GPIO_16

GPIO_22GPIO_20

GPIO_24

GPIO_0

ADC_IN5

ADC_IN0

ADC_IN1

ADC_IN4

ADC_IN2

ADC_IN3

ADC_IN7

ADC1IN6

ADC1IN5

ADC1IN7

ADC1IN8

ADC1IN1

ADC1IN2ADC1IN3

ADC1IN4

VCC5VCC3P3

VCC3P3_VCCA

VCC3P3_VCCA

VCC3P3_VCCA

VCC3P3_VCCA

VCC3P3_VCCAVCC3P3_VCCA

VCC3P3_VCCAVCC3P3_VCCA

VCC3P3_VCCAVCC3P3_VCCA

VCC5

VCC3P3

VCC3P3

VCC5

VCC5

Arduino_IO[15..0]4Arduino_Reset_n4

ADC1IN[8..1]3

GPIO_[35..0]4,7

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Arduino Expansion Header A1

DE10-Lite

B

13 18Monday, September 19, 2016

Title

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Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Arduino Expansion Header A1

DE10-Lite

B

13 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Arduino Expansion Header A1

DE10-Lite

B

13 18Monday, September 19, 2016

R81 316

R83316

R90 316

R39 10

-

+V+

V-

U8B

MCP6244-E/SL

5

67

411

R91 316

JP3

HEADER 8

12345678

R9710K

R32.2KDNI

R40 10R41 10

R82316

C1510.1u10V

C1521n50VDNI

-

+V+

V-

U8C

MCP6244-E/SL

10

98

411

R95316

R93316

C137

1p

L15 30ohm, 3A

R34 10

R84 316

-

+V+

V-

U8A

MCP6244-E/SL

3

21

411

TP1 DNI

TP_YELLOW

-

+V+

V-

U9D

MCP6244-E/SL

12

1314

411

JP1

2x20_BOX_Header

1 23 45 67 89 10

1113

1214161820222426

27

151719212325

28293133353739

303234363840

C1301n50VDNI

C135

1p

R86316

R96 316

-

+V+

V-

U9B

MCP6244-E/SL

5

67

411

JP7

HEADER 8

12345678

C1411n50VDNI

C136

1p

C1281n50VDNI

C131

1p

R89316

C1501n50VDNI

-

+V+

V-

U8D

MCP6244-E/SL

12

1314

411

R22.2KDNI

-

+V+

V-

U9A

MCP6244-E/SL

3

21

411

R94 316

C1480.1u10V

C134

1pC132

1p

JP8

HEADER 6

123456

C1471n50VDNI

-

+V+

V-

U9C

MCP6244-E/SL

10

98

411

C1531n50VDNI

C140

1p

C129

1p

TP2 DNI

TP_YELLOW

R87 316

R35 10

C1491n50VDNI

R92316

JP2

HEADER 10

12345678910

R88316

R38 10

JP4

HEADER 2x3

1 23 45 6

R85 316

R36 10R37 10

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

User IO, 7-Seg, LEDSWITCH

KEY

LED

7-segment Display

SW3SW2SW1SW0

G0

E0

B0

D0C0

A0

F0

LEDR3LEDR2LEDR1LEDR0

DP0

DP1G1

E1

B1

D1C1

A1

F1

DP2G2

E2

B2

D2C2

A2

F2

DP3G3

E3

B3

D3C3

A3

F3

HEX20HEX21HEX22

HEX30HEX31HEX32

DP4G4

E4

B4

D4C4

A4

F4

DP5G5

E5

B5

D5C5

A5

F5

HEX54

HEX46

LEDR4LEDR5LEDR6LEDR7

SW4SW5SW6SW7

LEDR8LEDR9

SW8SW9

KEY0KEY1

DP0C0B0A0

HEX07HEX02HEX01HEX00

F0G0E0D0HEX03

HEX05HEX06HEX04

DP1C1A1B1

F1

E1G1

D1

HEX17HEX12HEX10HEX11

HEX15HEX16HEX14HEX13

DP2

B2C2

A2

HEX27

F2G2E2D2

HEX25HEX26HEX24HEX23

DP3

B3C3

A3

HEX37

E5D5HEX53

G5F5

HEX56HEX55

G4

D4E4

F4

HEX44

HEX45

HEX43

A5HEX50B5HEX51C5HEX52DP5HEX57

DP4HEX47C4HEX42B4HEX41A4HEX40

D3HEX33E3HEX34G3HEX36

HEX35 F3

VCC3P3

VCC3P3 VCC3P3 VCC3P3 VCC3P3

VCC3P3

VCC3P3

VCC3P3

VCC3P3

VCC3P3

VCC3P3 VCC3P3 VCC3P3 VCC3P3

VCC3P3 VCC3P3

VCC3P3

SW[9..0]5

KEY[1..0]5

LEDR[9..0]5

HEX0[7..0]6

HEX1[7..0]6

HEX2[7..0]6

HEX3[7..0]6HEX4[7..0]6

HEX5[7..0]6

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

LED, 7'Segment, User I/O A1

DE10-Lite

B

14 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

LED, 7'Segment, User I/O A1

DE10-Lite

B

14 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

LED, 7'Segment, User I/O A1

DE10-Lite

B

14 18Monday, September 19, 2016

RN25 1K1234 5

678

RN22 1K1234 5

678

SW9

SLIDE SW

123

4

5

C1271u10V

ed

dp

c

g

b

f

a

CA1

CA2

HEX0

7Segment Display

1

23

45

6

1098

7

RN24 1K1234 5

678

ed

dp

c

g

b

f

a

CA1

CA2

HEX3

7Segment Display

1

23

45

6

1098

7

SW2

SLIDE SW

123

4

5

RN20 12012345

678

LEDR0 LEDR2 1

SW4

SLIDE SW

123

4

5

RN7 1K1234 5

678

RN26 1K1234 5

678

ed

dp

c

g

b

f

a

CA1

CA2

HEX4

7Segment Display

1

23

45

6

1098

7

RN19 12012345

678

SW3

SLIDE SW

123

4

5

LEDR1 LEDR2 1

LEDR3 LEDR2 1

RN27 1K1234 5

678

RN5 1K1234 5

678

RN6 1K1234 5

678

SW5

SLIDE SW

123

4

5

ed

dp

c

g

b

f

a

CA1

CA2

HEX5

7Segment Display

1

23

45

6

1098

7

KEY1

TACT SW

4 3

21

RN8 1K1234 5

678

KEY0

TACT SW

4 3

21

RN4 1K1234 5

678

RN15 12012345

678

RN21 1K1234 5

678

C1461u10V

SW6

SLIDE SW

123

4

5

LEDR8 LEDR2 1

RN17 330

1234 5

678

LEDR2 LEDR2 1

LEDR4 LEDR2 1

SW0

SLIDE SW

123

4

5

ed

dp

c

g

b

f

a

CA1

CA2

HEX1

7Segment Display

1

23

45

6

1098

7

RN18 330

1234 5

678

SW7

SLIDE SW

123

4

5

RN16 330

1234 5

678

LEDR5 LEDR2 1

RN23 1K1234 5

678

SW1

SLIDE SW

123

4

5

SW8

SLIDE SW

123

4

5

LEDR6 LEDR2 1

ed

dp

c

g

b

f

a

CA1

CA2

HEX2

7Segment Display

1

23

45

6

1098

7

LEDR9 LEDR2 1

LEDR7 LEDR2 1

RN14 100K1234 5

678

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VGA

Digital Accelerometer

Tie CS_n to high to I2C mode only

Default : I2C Address 0xA6/0xA7

Digital Accelerometer

VGA

VGA and Accelerometer

VGA_R1

VGA_B

VGA_R2

VGA_HSVGA_VS

VGA_R3

VGA_G

VGA_R0

VGA_G0

VGA_G2VGA_G1

VGA_G3

VGA_B0

VGA_B2VGA_B1

VGA_B3

VGA_R

GSENSOR_SDIGSENSOR_SCLK

GSENSOR_CS_n

GSENSOR_SDO

GSENSOR_INT2GSENSOR_INT1

VCC_VS

VCC3P3

VCC3P3

VCC_Gsensor

VCC_Gsensor

VCC_Gsensor

VGA_R[3..0]3

VGA_G[3..0]3VGA_B[3..0]3

VGA_HS3VGA_VS3

GSENSOR_SCLK4

GSENSOR_INT14

GSENSOR_SDI4

GSENSOR_CS_n4

GSENSOR_SDO4

GSENSOR_INT24

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

VGA and Accelerometer A1

DE10-Lite

B

15 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

VGA and Accelerometer A1

DE10-Lite

B

15 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

VGA and Accelerometer A1

DE10-Lite

B

15 18Monday, September 19, 2016

R162.2K

RN3 1K1234 5

678

R15 0

R20 120

C24.7u6.3V

RN12 2K12345

678

U1

ADXL345

VDD1

GND2

RESERVED3

GND4

GND5

VS6

CS_n7

INT18INT29NC10RESERVED_111SDO_ALT_ADDRESS12SDA_SDI_SDIO13SCL_SCLK14

C71u10V

RN1 1K1234 5

678

R4 2.2KDNI

R1410KDNI

R112.2K

DNI

RN10 2K12345

678

R132.2KDNI

L2 BEAD

R21 120

R82.2K

RN11 2K12345

678

C41u10V

C60.1u10V

R122.2KDNI

C30.1u10V

RN2 1K1234 5

678

10

11

6

1

5 15

J2 VGA

5

9

4

8

3

7

2

6

1

1716

101112131415

R7 0

L1 BEAD

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Power - 5V_DCIN / 1.2V

Overvoltage Protection Threshold Voltage : 5.4 ~ 5.6V

Ramp TimeTsoft-start = 1 msec

1.2V / 3ASwitching Frequency : 2.25MHz

Power up Sequence:VCC5--->VCC2P5, VCC3P3 --->VCC1P2_VCC

Panasonic2R5TPE330MAZB

Input Power Range: 5.4 ~ 5.6 V

5V Power from USB Port

Power GoodPower LED

5V Power LED

1P2_POK

VCC1P2_VCC

1P2_POK

3P3_POK

VCC5

VCC5

VCC1P2 VCC1P2_VCC

VCC5_USB

VCC5

VCC5

VCC5 VCC5

VCC2P5_CORE

3P3_POK17

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Power - 12V, 5V A1

DE10-Lite

B

16 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Power - 12V, 5V A1

DE10-Lite

B

16 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Power - 12V, 5V A1

DE10-Lite

B

16 18Monday, September 19, 2016

FID5

R70 1KDNI

R30 6.8K

R71470

D6

PMEG2010AEB

D4LEDG

21

C17100u6.3V

FID12

MH3MH1

C3110u10V

FID2

R26180K

R22 0.01

MH4

+ C18

2.5V330u

12

C3010u10V

D9

PMEG2010AEB

D5

BZX84C5V1

3

21

Q1HE8550G

R29330

JP6

Power - HDR

12

R76 0

D7

PMEG2010AEBR32100K

C3347u10V

FID1

C321u

DNI10V

FID6 FID4FID3

D8

PMEG2010AEB

R730

FID9

R69470DNI

Q3UTC8050DNI

1

23

R75 0DNI

VCC5

FID8

C230.1u10VDNI

R25180K

C2122p

LTC3612EUDC#TRPBF

U6

RT/SYNC2

PVIN_18

PVIN_29

PVIN_DRV13

SVIN14

RUN15

PGOOD16

MODE17

ITH19

TRACK/SS20

DDR1

SGN

D3

SW_15

SW_26

SW_311

SW_412

VFB18

PGN

D_E

PAD

21

FID7

R72 0C221u10V

VCC1P2

FID11

L5 470nH1 2

FID10

R316.8K

MH2PCB1

PCB

R42 100KDNI

C2010u10V

Q2AO3415

R27 100KDNI

D3LEDGDNI

21

C1910u10V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Power - 3.3V / 2.5VRamp TimeTsoft-start = 1 msec

3.3V / 3ASwitching Frequency : 2.25MHz

Panasonic6TPE100MAZB

Voltage Reference

2.5V / 0.5ARamp Time = 2 msec

1.8V / 0.5ARamp Time = 2 msec

3P3_POK

VCC3P3

VCC5

VCC5

VCC5

VCC3P3_VCCAVCC3P3

VCC3P3_VCCA REF_VCC2P5

VCC2P5VCC5

VCC3P3

VCC3P3

VCC1P8VCC5

VCC3P3

VCC3P3

VCC2P5_CORE

3P3_POK16

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Power - 1.8V, 2.5V, 3.3V A1

DE10-Lite

B

17 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Power - 1.8V, 2.5V, 3.3V A1

DE10-Lite

B

17 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Power - 1.8V, 2.5V, 3.3V A1

DE10-Lite

B

17 18Monday, September 19, 2016

C421u10V

C2410u10V

R45 100K

C15510u6.3V

R4310K

VCC2P5

C4410u10V

C3822u6.3V C157

4.7uDNI

C361u10V

R99 0

R53 33K

R80 10K

C462.2u10V

C3510u10V

VCC1P8

C28100u6.3V

C1540.1u10V

C2610u10V

C1330.1u10V

C144 4.7u

DNI

R46 100KDNI

+ C29

6.3V100u

12

C3410u10V

+ C145

6.3V100u

12

C391u

DNI10V

R44 52.3K

VCC3P3

U12

REF3125

VIN1

VOUT2

GND3

R4736.5K

R51 10K C43 4.7u

DNI

R48165K

REG1

LTC3025-1

BIAS1

GND2

ADJ5

OUT4

SHDN6

EP_GND7

IN3

VCC2P5_CORE

C3710u10V

R98 10KDNI

C1380.47u10V

R529.31K

REG2

LTC3025-1

BIAS1

GND2

ADJ5

OUT4

SHDN6

EP_GND7

IN3

LTC3612EUDC#TRPBF

U7

RT/SYNC2

PVIN_18

PVIN_29

PVIN_DRV13

SVIN14

RUN15

PGOOD16

MODE17

ITH19

TRACK/SS20

DDR1

SGN

D3

SW_15

SW_26

SW_311

SW_412

VFB18

PGN

D_E

PAD

21

C40

22p

C4522u6.3V

L14 30ohm, 3AL6 470nH1 2

C412.2u10V

U13

TPS22945 DNI

VIN5

VOUT1

ON4

OC3

GND2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

JTAG to MAX10 (2.5V)

Blaster Clock

Configuration LOAD

CONF_DONE

CPLD ISP

CLK_6MHz

USB_RESETn

USB_DPUSB_DM

OSC_24

PWRON

URD

UTXEUWR

URXF

UD1

SI_WU

UD2UD3

UD5UD6

UD4

UD7

UD0

EEPDATA

EEPCSEEPCLK

UBT_MAX_24UBT_CLK_24

ULED

CONF_DONE_DISP

ISP_TDI

ISP_TMSISP_TDOISP_TCK

ISP_TCKISP_TMSISP_TDIISP_TDO

ULED

PWRON

CLK_6MHz

UD7UD6UD5UD4UD3

UD1UD0

USB_RESETn

EEPCSEEPCLKEEPDATASI_WU

UD2

URXFUTXEUWRURD

UBT_MAX_24

CONF_DONE_DISP

JTAG_TCKJTAG_TMS

JTAG_EN

NCONFIGNSTATUSCONF_DONE

CONFIG_SEL

JTAG_TDIJTAG_TDO

VCC5_UBTVCC5

VCC3P3VCC5_USB VCC5_UBT

VCC3P3

VCC3P3

VCC3P3

VCC5_USB

VCC2P5

GND

VCC3P3

VCC3P3 VCC2P5VCC3P3

VCC3P3

VCC3P3

VCC3P3

VCC2P5VCC3P3

JTAG_TDI8

JTAG_TCK8,18JTAG_TMS8

JTAG_TDO8

JTAG_EN8

UBT_CLK_247

NSTATUS8

CONF_DONE8

NCONFIG8

CONFIG_SEL8

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

USB Blaster A1

DE10-Lite

B

18 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

USB Blaster A1

DE10-Lite

B

18 18Monday, September 19, 2016

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2016 by Terasic Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

USB Blaster A1

DE10-Lite

B

18 18Monday, September 19, 2016

C6010u10V

C550.1u10V

C480.1u10VDNI

R64 22

J1

Header_2x5DNI

1 23 45 67 89 10

R6 22

C540.1u10V

R49 120

C790.1u10V

C8047p50V

R5910K

C580.1u10V

R55 27

U2

EPM240T100

IO-B1-02

IO-B1-13

IO-B1-1016

IO-B1-1117

IO-B1-1218

IO-B1-1319

IO-B1-1420

IO-B1-1521

IO-B1-1626

IO-B1-1727

IO-B1-1828

IO-B1-1929

IO-B1-24

IO-B1-2030

IO-B1-2133

IO-B1-2234

IO-B1-2335

IO-B1-2436

IO-B1-2537

IO-B1-2638

IO-B1-2739

IO-B1-2840

IO-B1-2941

IO-B1-35

IO-B1-3042

IO-B1-31/DEV_OE43

IO-B1-32/DEV_CLRN44

IO-B1-3347

IO-B1-3448

IO-B1-3549

IO-B1-3650

IO-B1-3751

IO-B1-46

IO-B1-57

IO-B1-68

IO-B1-7/GCLK012

IO-B1-8/GCLK114

IO-B1-915

IO-B2-01

IO-B2-152

IO-B2-10/GCLK364

IO-B2-1166

IO-B2-1267

IO-B2-1368

IO-B2-1469

IO-B2-1570

IO-B2-1671

IO-B2-1772

IO-B2-1873

IO-B2-1974

IO-B2-253

IO-B2-2075

IO-B2-2176

IO-B2-2277

IO-B2-2378

IO-B2-2481

IO-B2-2582

IO-B2-2683

IO-B2-2784

IO-B2-2885

IO-B2-2986

IO-B2-354

IO-B2-3087

IO-B2-3188

IO-B2-3289

IO-B2-3390

IO-B2-3491

IO-B2-3592

IO-B2-3695

IO-B2-3796

IO-B2-3897

IO-B2-3998

IO-B2-455

IO-B2-4099

IO-B2-41100

IO-B2-556

IO-B2-657

IO-B2-758

IO-B2-861

IO-B2-9/GCLK262

TCK24

TDI23

TDO25

TMS22

VCC

INT

63

VCC

INT

13

VCC

IO1

9

VCC

IO1

31

VCC

IO1

45

VCC

IO2

80

VCC

IO2

94VC

CIO

259

GN

DIN

T65

GN

DIN

T11

GN

DIO

32G

ND

IO10

GN

DIO

79G

ND

IO46

GN

DIO

60

GN

DIO

93

X1

24MHz DNI

VCC4

OUT3

GND2

EN1

C5733n16V

RN9

10K

12345

678

C590.1u10V

R50 120

C100.1u10V

D2 LEDG2 1

L7 30ohm, 3A

R66 100KDNI

U11

TPD2EUSB30D-

2D+1

GND3

C8310u6.3V

L8 30ohm, 3A

DNI

C820.1u10V

C840.1u10V

C547p50V

R58 1.5K

C1 0.1u10V R54

10K

VBUSGND

D-D+

J3USB B-TYPE

4

32

1

5 6

D1 LEDG2 1

U10

FT245BL

LQFP-32

USBDP7

TEST31

AVC

C30

RXF#12

EEDATA2

VCC

3

D421D322D223D124D025VC

C26

XTIN27

XTOUT28

GN

D17

D718D619D520

RD#16

WR15

TXE#14

VCC

IO13

AGN

D29

EECS32 EESK

1

RESET#4

SI/WU11

PWREN#10

RSTOUT#5

3V3OUT6

USBDM8

GN

D9

C810.1u10V

R65 100K

R5 0DNI

R67 330C470.1u10V

R1 1M

C490.1u10V

R56 27

C780.1u10V