Alpha AXP Alpha AXP ArchitectureArchitecture Dr. Richard L. SitesDr. Richard L. Sites

Digital Technical Digital Technical JournalJournal

Volume 4, Number 4Volume 4, Number 4

Special Issue 1992Special Issue 1992Shyam Bukka Shyam Bukka

Friday, January 30, 2004Friday, January 30, 2004

Dr. Richard L. SitesDr. Richard L. Sites EmploymentEmployment

• IBMIBM• Hewlett-PackardHewlett-Packard• BurroughsBurroughs• Digital Equipment Corporation (1980) significant Digital Equipment Corporation (1980) significant

contributor to the Alpha AXP architecturecontributor to the Alpha AXP architecture EducationEducation

• B.S. in Mathematics form MITB.S. in Mathematics form MIT• Ph.D. in Computer Science from Stanford Ph.D. in Computer Science from Stanford

UniversityUniversity• Post-doctoral work at the University of North Post-doctoral work at the University of North

Carolina (computer architecture)Carolina (computer architecture)

ALPHA AXP DESIGN ALPHA AXP DESIGN GOALSGOALS

1. High Performance.1. High Performance.

2. Longevity.2. Longevity.

3. Capability Of run both VMS and Unix 3. Capability Of run both VMS and Unix Operating Systems.Operating Systems.

4 Easy migration from VAX and MIPS 4 Easy migration from VAX and MIPS architectures.architectures.

1.1. PAL ( Privileged Architecture Library )code lets PAL ( Privileged Architecture Library )code lets Alpha AXPAlpha AXP

Implementations run the full Open VMS AXP and Implementations run the full Open VMS AXP and DEC OSF/1 and Windows NT AXP operating DEC OSF/1 and Windows NT AXP operating systems.systems.

PAL CodePAL Code

It is a Privileged Architecture Library It is a Privileged Architecture Library (PAL Code) (PAL Code)

1. It contains a set of Subroutines that are specific 1. It contains a set of Subroutines that are specific to ato a

particular Alpha AXP Operating System particular Alpha AXP Operating System Implementation.Implementation.

PAL Code is written in Standard Machine Code.PAL Code is written in Standard Machine Code.2. It provides the Operating System Primitives like 2. It provides the Operating System Primitives like

Context Switching , Interrupts , exceptions and Context Switching , Interrupts , exceptions and Memory Management. Memory Management.

3. It is written in a standard machine code language 3. It is written in a standard machine code language and it is accessible by implementation hardware or and it is accessible by implementation hardware or CALL_PAL instructions. CALL_PAL instructions.

Performance And LongevityPerformance And Longevity

Performance : Performance :

Alpha AXP architecture is listed in Guinness Alpha AXP architecture is listed in Guinness Book Of World Records as the world’s Book Of World Records as the world’s fastest single-chip fastest single-chip Microprocessor.Microprocessor.

Longevity :Longevity :

The longevity of Alpha AXP is increased by 1000 The longevity of Alpha AXP is increased by 1000 times by the following three considerationstimes by the following three considerations..

1.1. Fast Cycle Time Implementations.(10 times)Fast Cycle Time Implementations.(10 times)

2.2. Multiple Instruction Issue (MII).(10 times)Multiple Instruction Issue (MII).(10 times)

3.3. Multiple Processor Implementation.(10 times) Multiple Processor Implementation.(10 times)

Key Design IssuesKey Design Issues

1.RISC.

2.Full 64-bit design.

3.Register File.

4.Multiple Instruction Issue (MII).

5.Shared Memory Multiprocessing.

Multiple Instruction Issue Multiple Instruction Issue (MII)(MII)

MII : Starting more than one instruction at MII : Starting more than one instruction at Once.Once.

1.1. No Branch Delayed Slots.No Branch Delayed Slots.2.2. No Suppressed Instructions.No Suppressed Instructions.3.3. No Byte Load/Store Instructions and No Byte Load/Store Instructions and

Implicit Unaligned accesses and no Partial Implicit Unaligned accesses and no Partial Register Writes.Register Writes.

4.4. No Arithmetic Exceptions.No Arithmetic Exceptions.• Cray-1 Model of Arithmetic Exceptions are Cray-1 Model of Arithmetic Exceptions are

adopted in first AXP architecture (Exceptions adopted in first AXP architecture (Exceptions are reported at the end of the event).are reported at the end of the event).

• Explicit TRAPB ( TRAP Barrier) Instruction.Explicit TRAPB ( TRAP Barrier) Instruction.

Branch Delayed SlotsBranch Delayed Slots

Address Normal Jump Delayed Jump

Optimized Del. Jump

100

101

102

103

104

105

106

LOAD X , A

ADD 1 , A

JUMP 105

ADD A , B

SUB C , B

STORE A , Z

LOAD X , A

ADD 1 , A

JUMP 105

NOP

ADD A , B

SUB C , B

STORE A , Z

LOAD X , A

JUMP 105

ADD 1 , A

ADD A , B

SUB C , B

STORE A , Z

Example for Aligned AccessExample for Aligned Access

1155

3434 7878 1144

1133

4444 1818 1122

1111

DEDE FEFE 1100

99 BCBC ACAC 88

77 4545 EEEE 66

55 FEFE 5656 44

33 4545 1212 22

11 ABAB FFFF 00

15 8 7 0 16 Bit Data

Bus

Memory Address

Data

1. Accessing Data from 0th word

2. Data(15:8) = AB

3. Data(7:0) = FF

4. Aligned Access

Example for Unaligned Example for Unaligned AccessAccess

1515 3434 7878 1414

1313 4444 1818 1212

1111 DEDE FEFE 1010

99 BCBC ACAC 88

77 4545 EEEE 66

55 FEFE 5656 44

33 4545 1212 22

11 ABAB FFFF 00

15 8 7 0

Memory Address

Data Bus

Data

1. Accessing Data from 1 word

2. Data(15:8) = AB

3. Data(7:0) = 12

4. Un aligned Access

Shared Memory Multi Shared Memory Multi ProcessingProcessing

1.1. Load LockedLoad Locked

2.2. In-Register ModifyIn-Register Modify

3.3. Store-Conditional Store-Conditional

4.4. Test Test

Data RepresentationData Representation Data Characteristics :Data Characteristics :

All Operations are done between 64-bit All Operations are done between 64-bit Registers.Registers.

Memory is accessed via 64-bit Virtual Memory is accessed via 64-bit Virtual Addresses, using the little-endian or, Addresses, using the little-endian or, optionally the big-endian byte numbering optionally the big-endian byte numbering convention.convention.

There are 32 integer registers(R31=0) and There are 32 integer registers(R31=0) and 32 floating-point registers (F31=0).32 floating-point registers (F31=0).

Longword(32-bit) and Quadword (64-bit) Longword(32-bit) and Quadword (64-bit) integers are supported.integers are supported.

Data TypesData Types

1. 1. Four Integer data types are supported :Four Integer data types are supported :• ByteByte• WordWord• LongwordLongword• QuadwordQuadword

2. 2. Five floating point data types are supportedFive floating point data types are supported : :• VAX Floating Point FormatsVAX Floating Point Formats

VAX F_floating (32-bit)VAX F_floating (32-bit) VAX G_floating(64-bit)VAX G_floating(64-bit)

• IEEE Floating Point FormatsIEEE Floating Point Formats IEEE single (32-bit)IEEE single (32-bit) IEEE double (64-bit)IEEE double (64-bit) IEEE extended (128-bit)IEEE extended (128-bit)

Integer Data Representation Integer Data Representation

7 0 : A

1. Byte Format

8-bit Data item.

It is supported by the extract, insert , zap instructions.

2. Word Format

15 0 : A

16-bit Data item.

It is supported by the extract, mask, insert instructions.

3. Longword

31 0

32-bit Data item.

Bit 31 is the Sign bit.

It is supported by sign-extended load/store instructions and longword arithmetic instructions.4. Quadword

: A

63 0 64-bit Data item.

Bit 63 is Sign bit (Signed Integer).

It may be a Signed Integer / Un signed Integer

: A

VAX Floating Point FormatsVAX Floating Point Formats 1. F_floating Format1. F_floating Format

Memory FormatMemory Format

31 16 15 14 7 6 0

Frac. HiExp.SFracton. Lo

Register Format

63 62 52 51 29 28 0

S Exp. Fraction 0

1. If Exp=0 and S=0 Then Value = 0.

2. If Exp=0 and S=1 Then it is a Reserved Operand.

3. Range 0.29*10**-38 Through 1.7*10**38.

4. Precision is 7 decimal digits.

IEEE Floating-Point FormatsIEEE Floating-Point Formats IEE Floating-Point FormatsIEE Floating-Point Formats

Basic Extended

Single Double Single DoubleThe values representable within a format are specified by using three integer parameters.

P --- Number of fraction bits.

Emax --- The Maximum exponent.

Emin --- The Minimum exponent.

Within each format following entities are permitted.

Numbers of the from (-1)**S x 2**E x b(0).b(1).b(2)……b(P-1)

a. S=0 or 1

b. E = any integer between Emin and Emax, inclusive

c. b(n) = 0 or 1

d. Two infinities-positive and negative

e. At least one Signaling NaN

f. At least one Quiet NaN

BASICBASIC

Basic Floating Data type FormatsBasic Floating Data type Formats : :1.1. SingleSingle

: AExp.S Fraction.

31 30 23 22

0

S Exp. Fraction 0

63 62 52 51 29 28 0

Memory

: A Register

2.2. Double (T_floatong ) Double (T_floatong )

MemoryMemory

Register Register

S Exponent Fraction Hi

Fraction Lo

31 30 20 19 0 : A

: A+4

S Exp. Fraction 0

63 62 52 51 32 31 0

Instruction FormatsInstruction Formats1.1. Four Fundamental Instruction formats are Four Fundamental Instruction formats are

there in Alpha AXP.there in Alpha AXP. Operate Instructions.Operate Instructions. Memory Instructions.Memory Instructions. Branch Instructions.Branch Instructions. CALL_PAL Instructions.CALL_PAL Instructions.

1.1. All Instructions are 32-bit wide.All Instructions are 32-bit wide.

2.2. They reside aligned long word addresses.They reside aligned long word addresses.

3.3. Each Instruction contains 6-bit Opcode. And zero Each Instruction contains 6-bit Opcode. And zero to three 5-bit Register-number fields, RA,RB,RC.to three 5-bit Register-number fields, RA,RB,RC.

4.4. The remaining bits contains function (opcode The remaining bits contains function (opcode extension), Literal, or Displacement fields. RB is extension), Literal, or Displacement fields. RB is never Written and RC is never Read.never Written and RC is never Read.

Operate InstructionsOperate Instructions Instruction Format :Instruction Format :

OP RA Literal 1

0

Func

Func. RC

Func.

RB

RB

///

6 5 5 11 5

Integer, Litteral

Integer,Register

Floating Point There are five groups of register-to-register operate instructions : Integer, Arithmetic, logical, byte manipulation and miscellaneous instructions.

All Operate Instructions are three-operand register- to-register instructions and operate on 64-bit Quadwords unless otherwise specified.

The Instruction is in the form of RC=RA Operate RB.

In Integer operates , the opcode and a 7-bit function field specify the exact operation.

Integer operates may have an 8-bit zero-extended literal instead of RB.

In floating-point operates, the opcode and an 11-bit function specify the exact operation.

There are no floating point literals.

Example for Opearte InstructionExample for Opearte Instruction

Longword Add :Longword Add : Format : Format :

ADDL Ra.rl,Rb.rl,Rc.wq !Operate ADDL Ra.rl,Rb.rl,Rc.wq !Operate FormatFormat

ADDL Ra.rl,#b.rl,Rc.wq !Operate ADDL Ra.rl,#b.rl,Rc.wq !Operate FormatFormat

Operation :Operation : SEXT((Rav+Rbv)<31:0>)

Rc

Exceptions :

Integer Overflow

Instruction Mnemonics :

ADDL Add Longword

Qualifiers :

Integer Overflow Enable (/V)

Memory InstructionMemory Instruction

Instruction Format :

OP RA RB Displacement

6 5 5 16

31 26 21 16 0

Memory Format Instructions are used for loads, stores, and a few miscellaneous operations.

Loads /Store are two operand Instructions, Specifying Register RA and a base-displacement virtual byte address.

The effective address calculation sign extends the 16-bit displacement to 64 bits and adds the 64-bit RB register.

The resultant virtual byte address is mappe d to the physical address.

The miscellaneous instructions makes the other uses of RA,RB registers.

Example For Memory InstructionExample For Memory Instruction

Load G_floating :Load G_floating : Format : Format : LDG Pa.wg,disp.ab(Rb.abLDG Pa.wg,disp.ab(Rb.ab)) !Memory Format !Memory Format

Operation :Operation : Va (Rbv+SEXT(disp))Va (Rbv+SEXT(disp))

Fa (Va)<15:0>||(Va)<31:16>||Fa (Va)<15:0>||(Va)<31:16>|| (Va)<47:32>||(Va)<63:48(Va)<47:32>||(Va)<63:48>>

Exception : Exception : Access ViolationAccess Violation

Fault on ReadFault on Read AlignmentAlignment

Translation Not ValidTranslation Not Valid

Instruction Mnemonic :Instruction Mnemonic : LDG Load G_floating (Load D-floating)LDG Load G_floating (Load D-floating) Qualifiers :Qualifiers : None.None.

Branch Instruction FormatBranch Instruction Format

Instruction Format :Instruction Format :

OP RA Displacement

6 5 21

31 26 21 0

Branch Instructions specify a single register RA and a signed PC-Relative longword displacement.

The branch target calculation shifts the 21-bit displacement left by 2 bits to make it long word displacement then sign extends it and adds to the updated PC.

Conditional branch instructions test register RA, and unconditional branches write the updated PC to RA for subroutine linkage.

Calculated jump instructions write the updated PC to RA and then jumps to the target address in RB.

Instruction Format : Instruction Format :

CALL_PAL Instruction

OP Function

31 26 0

6 26

The CALL_PAL Instructions has only a 6-bit opcode and a 26-bit function field.

The function field is a small integer specifying one of a few dozen privileged architecture library routines.