All Digital Fm Receiver

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All Digital FM Receiver (Version 1.0)All Digital FM Receiver (Version 1.0)All Digital FM Receiver (Version 1.0)All Digital FM Receiver (Version 1.0)

Tom Wada, Prof of the University of the Ryukyus, Information Engineering Dept.

[0] Introduction[0] Introduction[0] Introduction[0] Introduction

This year's design target is the All Digital FM Receiver circuit. The FM (Frequency Modulation) isone of very famous wireless communication method and you can find many text book relating tothe FM. Carrier frequency is modulated according to the strength of analog signal such as Voice.In this design project, we are going to design the all digital FM receiver circuit assuming theFrequency Modulated signal is converted to series of numerical values (digital signal) via Analogto Digital Conversion (ADC) circuit.

Since this contest is mainly for University students, we try to realize the target design as simpleas possible. The core of the target design will be digital phase locked loop circuit, which

generates sinusoidal wave synchronizing to the input FM wave. The requirements of the design isto write HDL (VHDL or Verilog HDL) and to synthesize digital circuits using Synopsys designanalyzer or any other EDA tools. Making FPGA is also optional but our judges love to see yourFPGA designs.

Figure1 System DiagramFigure1 System DiagramFigure1 System DiagramFigure1 System Diagram

Figure 1 shows the Frequency modulation and demodulation system. Signal generator (SigGen)generates the transmitting signal. In the figure 1, although only 1 or -1 are assumed for SigGenoutput, other value such as 0.5 is also acceptable. VCO represents Voltage Controlled Oscillator,which generates sinusoidal wave frequency-modulated by the SigGen output. ADC is Analog toDigital Converter, which converts the analog FM signal to descrete digitaized signals. When the

output of SigGen is -1, the VCO output frequency is relatively low, and when the SigGen outputis 1, the VCO output frequency is relatively high. In our design target, we assume the ADC

output bit width is 8 bit. Then 28=256 different values can be expressed at the output of ADC.

码，1/15All Digital FM Receiver

2006-7-12http://www.ie.u-ryukyu.ac.jp/~wada/design05/spec_e.html



The FM Receiver gets the 8 bit signal every clock cycle and outputs the demodulated output.

[1] Phase Locked Loop (PLL)[1] Phase Locked Loop (PLL)[1] Phase Locked Loop (PLL)[1] Phase Locked Loop (PLL)

The figure 2 shows the serially connnected PLL cirucit and Low Pass Filter circuit. This simplecircuit configuration realizes the our target FM Receiver circuit.

Figure 2. PLL and LPFFigure 2. PLL and LPFFigure 2. PLL and LPFFigure 2. PLL and LPF

In this section, PLL operation basic will be explained using some mathematical equations.

Since the input signal is Frequency Modulated, the input signal in(t) can be expressed as follows,

NCO is similar oscillator as VCO. although VCO is analog circuit, NCO is digital circuit. Theoutput sinusoidal frequency is controlled by digital input value. The the oscillator is called asNumerical Controlled Oscillator (NCO). As shown in figure 1, since the PLL includes thefeedback loop, NCO outputs the same frequency sinusoidal with in(t). Then NCO output ref(t) isexpressed as follows,

By multiplying in(t) and ref(t) gives the c(t) as follows,





The first term of the above equation corresponds to the phase difference between in(t) and ref (t). The second term corresponds to high frequency component. By removing the second termthru loop filtering, the phase difference can be obtained. This is the job of the PhaseComparator.

As shown in the figure 2, the loop filter circuit is composed of small loop circuit. It does additionof c(t) and coefficient alpha=15/16=0.9375 multiplied D flipflop output. Then loop filter outputexpressed as follows.

This is a kind of averaging with the smaller weight for the older values. Then it has low passfiltering characteristics.

NCO will be explained in the next section.

[2] Numerical Controlled Oscillator (NCO)[2] Numerical Controlled Oscillator (NCO)[2] Numerical Controlled Oscillator (NCO)[2] Numerical Controlled Oscillator (NCO)

Figure 3 explains NCO.





Figure 3. Numerical Controlled Oscillator (NCO)Figure 3. Numerical Controlled Oscillator (NCO)Figure 3. Numerical Controlled Oscillator (NCO)Figure 3. Numerical Controlled Oscillator (NCO)

In our target system, let's assume that system clock frequency is 16MHz = 16,000,000MHz andcenter NCO operating frequency is 1MHz = 1,000,000MHz. Then as shown in the figure 3, thereare 16 sampling points in 1 cycle of 1MHz sinusoidal wave.

The NCO generates exactly 1 cycle of sinusoidal wave when input value = 0. Then the offsetvalue is 1/16. Every clock cycle, the D flipflop accumulates the offset value. Then, in 16 cycles,accumulated value will increase by 1.0. The accumulator output is multiplied by 2pai, then cosinevalue is extracted from the cos ROM.

When the input value is more than 0, the accumulation speed gets higher. Then in less than 16cycles, the accumulator increases by 1.0. This corresponds to higher frequency than 1.0MHz isgenerated. Vice versa, when the input value is less than 0, lower frequency than 1.0MHz isgenerated. Consequently, the NCO operating frequency will be controlled by the input value withcenter frequency of 1.0MHz.

[3] Low Pass Filter (LPF)[3] Low Pass Filter (LPF)[3] Low Pass Filter (LPF)[3] Low Pass Filter (LPF)

One of the most famous digital filter is Finite Impulse Response (FIR) Filters. Figure 4(a) showsthe 16 TAP FIR filter circuit diagram.

Figure 4. Finite Impulse Response FiltersFigure 4. Finite Impulse Response FiltersFigure 4. Finite Impulse Response FiltersFigure 4. Finite Impulse Response Filters

Then, the 16TAP filter output is as follows,





If the coefficients a0, a1, ..., a15 are appropriately determined, optimized Low Pass Filter can be

configured. However, the optimized configuration needs 16 multipliers, that is, larger circuit area.Then, in this design task, let's assume the all coefficients a

i= 1/16=0.0625. Figure 4(b) shows

this configuration. 1/16 multiplier is moved to the latter stage and shared. In reality, 1/16multiply can be implemented by just 4 bit right shift operation. Then, no multiplier is required.

[4] Fixed Point Format[4] Fixed Point Format[4] Fixed Point Format[4] Fixed Point Format

In this design task, we need to treat fraction number such as 1/16 = 0.0625 in digital circuitdesign. The meaning of the 4 bit value "0111" does change according to the position of thefraction point. For example, "01.11" in binary means +1.75 in decimal, and "0111." in binarymeans +7 in decimal. In addition, the meaning of the 4 bit binary value will change whether it isunsigned format or two's complement format. For example, "11.10" in unsigned binary means +3.50 in decimal, and "11.10" in two's complement binary means -0.50 in decimal.

Then we need to clarify the attributes of both "the position of fraction point" and "unsigned ortwo's complement" when we use binary number.

In this section, the attributes notation , which is used in Signal Processing Workbench, isexplained.

If the signal attribute is <8,2,t>, then the signal is as follows,

8: signal width is 8 bit2: integer part is 2 bitst: two's complement number, then the MSB bit of the signal is sign bit.

For example, "01101111" with attribute <8,2,t> is as follows.

Then fraction is 5 bits and it is +3.46875 in decimal.

If the signal attribute is <8,2,u>, then the signal is as follows,

8: signal width is 8 bit2: integer part is 2 bitsu: unsigned format, then the value is always positive or zero and no sign bit.

0 1 1 0 1 1 1 1

sign bitsign bitsign bitsign bit integerintegerintegerinteger fractionfractionfractionfraction





[5] Circuit Example of All Digital FM Receiver[5] Circuit Example of All Digital FM Receiver[5] Circuit Example of All Digital FM Receiver[5] Circuit Example of All Digital FM Receiver

Figure 5 shows a example circuit diagram of the FM receiver with all bit attributes. fmin is 8bitFM input signal and dmout is 12 bits demodulated output signal.

Figure 5.Figure 5.Figure 5.Figure 5. A example of All Digital FM ReceiverA example of All Digital FM ReceiverA example of All Digital FM ReceiverA example of All Digital FM Receiver

Figure 6 shows the simulated waveform of the example circuit. Here, the system clock frequencyand the sampling frequency are 16MHz = 16,000,000Hz. FM modulation is +- 10KHz at center of 1MHz=1,000,000Hz. The modulation is just +-10% of the 1MHz carrier frequency, then it is

difficult to identify the FM modulation in the figure 5 simulation waveform. In the simulation, wehave assumed the sampling frequency = 16MHz. However, you can scale the sampling frequencyas you wish. Be sure not to forget to scale the carrier frequency.

<4,0,t> S.XXXS.XXXS.XXXS.XXX -1.00 to +0.875 0.125 (1/8)

othersothersothersothers

<4,2,u> XX.XXXX.XXXX.XXXX.XX 0.0 to 3.75 0.25 (1/4)

<4,2,t> SXX.XSXX.XSXX.XSXX.X -4.0 to + 3.5 0.5 (1/2)

<4,5,u> XXXX0.XXXX0.XXXX0.XXXX0. 0 to 30 2

<4,5,t> SXXX00.SXXX00.SXXX00.SXXX00. -32 to 28 4

<4,-1,u> .0XXXX.0XXXX.0XXXX.0XXXX 0.0 to 0.46875 0.03125 (1/32)

<4,-1,t> S.SXXXS.SXXXS.SXXXS.SXXX -0.5 to +0.4375 0.0625 (1/16)





The first row shows the sending data is repeating 1 and -1. The second row show the FMmodulated waveform according to the sending data. The third row is NCO output and the fourthrow is Phase comparator, that is, multiplier output. The fifth row and the sixth row are theaccumulator output and the demodulated output. In this view, all sampled signal, which arediscrete, are connected in line. At the initial simulation phase, the demodulated outputovershoots since the phase synchronization is in convergence phase.





Figure 6.Figure 6.Figure 6.Figure 6. Simulated Waveform (1)Simulated Waveform (1)Simulated Waveform (1)Simulated Waveform (1)

A part of the figure 6 is expanded and shown in figure 7. In this view, all sampled signal is shownin bar graph style.





Figure 7.Figure 7.Figure 7.Figure 7. Simulated Waveform (2)Simulated Waveform (2)Simulated Waveform (2)Simulated Waveform (2)

[6] LEVEL 1 Task for beginners[6] LEVEL 1 Task for beginners[6] LEVEL 1 Task for beginners[6] LEVEL 1 Task for beginners

In LEVEL 1 Task, the minimum design requirement is to design FM demodulation circuit which iscapable to demodulate the 1 and -1 repeating sending data as shown in figure 6. Table 3 showsthe example of the pin list of the FM Receiver. You can modify the pin list if needed.

Table 3. Pin list for LEVEL1Table 3. Pin list for LEVEL1Table 3. Pin list for LEVEL1Table 3. Pin list for LEVEL1

FM input (FMIN) data is linked as follows, corresponding to the second row waveform in figure 6.The attribute is <8,0,t> and 1000 points.

FM input： fm.txt

NCO's cos ROM data is also linkd as follows. It just one cycle of cosine then it it will be easilygenerated. Totally 1024 <8,0,t> data.

x=0 to 1023 by 1, cosine value = cos(2*pi*x/1024)

cosine ROM contents： cos.txt

[7] LEVEL2 Task for experienced designners[7] LEVEL2 Task for experienced designners[7] LEVEL2 Task for experienced designners[7] LEVEL2 Task for experienced designners

In LEVEL 2 Task, the minimum design requirement is to design FM demodulation circuit which iscapable to demodulate the triangular wave between -1 to 1 as shown in figure 8. According tothe sixth row of figure 8, you can see that the triangular sending data is successfullydemodulated. Input data vector is linked as follows.

FM input wave for triangular sending data with attribute <8,0,t>： fmTri.txt

FM Receiver

Signal name in or output bit width explanation

CLK IN 1 system clock input

RESET IN 1 assertion '1' means reset

FMIN IN 1 input data with attribute<8,0,t>

DMOUT IN 12 demodulated output with attribute<12,4,t>





Figure 8.Figure 8.Figure 8.Figure 8. Simulated waveform for Triangular shape sending dataSimulated waveform for Triangular shape sending dataSimulated waveform for Triangular shape sending dataSimulated waveform for Triangular shape sending data

[[[[8] Speed and Area UNIT8] Speed and Area UNIT8] Speed and Area UNIT8] Speed and Area UNIT

Since it is impossible to use the same synthesis library for various participants,

use 1 exor gate delay as a 1 UNIT_DELAYUNIT_DELAYUNIT_DELAYUNIT_DELAY for speed comparison and, use 1 exor gate area as a 1 UNIT_AREAUNIT_AREAUNIT_AREAUNIT_AREA for area comparison.

How to measure 1 exor gate delayHow to measure 1 exor gate delayHow to measure 1 exor gate delayHow to measure 1 exor gate delay

1. Synthesize the 50 inputs exor gate2. Measure the total delay time

3. UNIT_DELAYUNIT_DELAYUNIT_DELAYUNIT_DELAY is obtained by total delay divided by the number of stages4. UNIT_AREA is obtained by the total area divided by number of EXOR gates

VHDL code for 50 inputs exor : parity.vhd example of synthesized circuit : PDF, PS example of critical path delay measurement : report_timing example of circuit area measurement : report_area

In the previous example, total delay = 7.17 ns and 6 circuit stages, then the 7.17/6= 1.195 ns1.195 ns1.195 ns1.195 ns isthe UNIT_DELAYUNIT_DELAYUNIT_DELAYUNIT_DELAY of the speed. Please normalize your circuit speed by this UNIT_DELAYUNIT_DELAYUNIT_DELAYUNIT_DELAY.

In the example, total cell area = 147.0 and 49 EXOR gates. Then 147.0/49=3.0 is the UNIT_AREAUNIT_AREAUNIT_AREAUNIT_AREA.Please normalize your circuit area by this UNIT_AREAUNIT_AREAUNIT_AREAUNIT_AREA.

[9] Report[9] Report[9] Report[9] Report

The report has to include the following contents. Be concise!The report has to include the following contents. Be concise!The report has to include the following contents. Be concise!The report has to include the following contents. Be concise!

Title page

1 Team name, Members Name, School, Grade

2 Address, Phone, Email-address3 TTTT----shirt size for all members in the teamshirt size for all members in the teamshirt size for all members in the teamshirt size for all members in the team

4 Which level of task is designed.

Contents

1 Circuit block or architecture description

2 Designed circuit functional explanation, etc.

3 Appealing point and originality

4 Critical path speed, and circuit area

5 HDL codes (VHDL or Verilog HDL)

6 Simulation waveform indicating the design is operating!

7 Anything you want to claim





Report has to be emailed to the following address. Please use PDF file format.

If you want to send the report data other than PDF, please consult me.

[email protected]

THE DEAD LINE IS 2005/JANUARY/31TH!THE DEAD LINE IS 2005/JANUARY/31TH!THE DEAD LINE IS 2005/JANUARY/31TH!THE DEAD LINE IS 2005/JANUARY/31TH!

[10] Suggestion from judges[10] Suggestion from judges[10] Suggestion from judges[10] Suggestion from judges

We try to evaluate not only the speed and the area, but also your idea ,originality,uniqueness. But be sure to remember that we are not perfect, please make a goodpresentation to appeal us.

We definitely take your school grade into account. We like fun ideas. Please do something different from others.

[11] Acknowledgement[11] Acknowledgement[11] Acknowledgement[11] Acknowledgement

Thank you Mr. Akihisa Yokoyama @ TOYOTA INFOThank you Mr. Akihisa Yokoyama @ TOYOTA INFOThank you Mr. Akihisa Yokoyama @ TOYOTA INFOThank you Mr. Akihisa Yokoyama @ TOYOTA INFO----TECHNOLOGY CENTER for providing initialTECHNOLOGY CENTER for providing initialTECHNOLOGY CENTER for providing initialTECHNOLOGY CENTER for providing initialcircuit idea of FM receiver.circuit idea of FM receiver.circuit idea of FM receiver.circuit idea of FM receiver.

This program isThis program isThis program isThis program isoperated by Univ. of Ryukyus, IE dept.,operated by Univ. of Ryukyus, IE dept.,operated by Univ. of Ryukyus, IE dept.,operated by Univ. of Ryukyus, IE dept.,cocococo----operated by Okinawa Industry Support Center,operated by Okinawa Industry Support Center,operated by Okinawa Industry Support Center,operated by Okinawa Industry Support Center,

anananand cod cod cod co----sponsponsponsponsored by SONY LSI Design Inc and Kyusyu Bureau of Economy, Trade and Industry.sored by SONY LSI Design Inc and Kyusyu Bureau of Economy, Trade and Industry.sored by SONY LSI Design Inc and Kyusyu Bureau of Economy, Trade and Industry.sored by SONY LSI Design Inc and Kyusyu Bureau of Economy, Trade and Industry.

ENJOY HDL! We want to see you at OKINAWA!ENJOY HDL! We want to see you at OKINAWA!ENJOY HDL! We want to see you at OKINAWA!ENJOY HDL! We want to see you at OKINAWA!

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