SHAIK.JOHAR ALIEmail: ali08cn18@gmail.com .Mobile:7416132405

Career Objective: To obtain a professional position in challenging and creative environment which will help me to explore my abilities and contribute to the organization’s growth.

Core Competency:

A dedicated professional with 1 1/2 years of experience as custom layout design engineer

Experience as layout design engineer in 3 Tape-ins at intel in 14nm (finifets) Experience of cadence tools in executing custom layout projects. Proficient in writing TCL,SKILL scripts which improves productivity and efficiency. Analyzing technology files, layers, rule files, device formation technology. Knowledge on device matching, noise coupling, antenna effect, latch up effects. Inter-digitization and Centroid based Layout Design of Resistor, Capacitor Array and

Amplifier Design. Understanding signal flow to acquire an optimum floor plan and power plan. Writing a SPICE level net list of a given circuit. Debugging DRC and LVS violations. Knowledge of operating systems UNIX, WINDOWS. Programming Languages: C, C++

Education Qualification:

Special Diploma in Electronics from Govt. Institute of Electronics (2008-2013), Secunderabad with Specialization in Communication Engineering with an aggregate of 65%.

SSC passed in year 2007-08 with an aggregate of 88 %.

Job experience:

Worked as Layout design engineer (ICE) at Intel since feb-2014 to jan-2015 in 14 nm technology.

Undergone intensive training in CUSTOM LAYOUT from First Pass Semiconductors Pvt Ltd., Hyderabad, since May to November 2011.

Tool expertise:

Virtuoso (Cadence) IC compiler (synopsys) ICWB (synosys) Parade (intel)

Genesys (intel) Assura (Verification) IC validator (verification) SISS (verification)

Projects Executed:

Project 1: NEXT GENERATION SERVER (intel)Targeted technology: 14nm (finfets)

Worked as MD for fub-level DRC, DFM ,LVS cleanup, net improvement to achieve timing targets, implementing engineering change orders, upsizing and downsizing of the cells ,buffer insertions, rerouting the nets, verification and cleanup of complete tape in flow runsets.

Worked as Section Layout Owner (SLO) at section level which involves DRC/LVS/Density/NAC(IPall) clean up, Noise fix, Section and full chip cleanup, Fub integration, loevr generation, verifying ISS flow (golden run for section).

Tools Used: IC compiler (synopsys), ICWB (synopsys) ,Parade (intel), Genesys (intel),CPDS (iss runs).

Project 2: STANDARD CELLS LAYOUT DESIGNING

Targeted technology: TSMC 130Cells designed: INVERTER, NAND, NOR, AND, OR, LATCH, MUX, D-flip flop.Role: Come up with stick diagram from spice net list, layout design, DRC and LVS verification.Tools Used: Virtuoso Layout Editor, Assura Verification

Project 3: ANALOG LAYOUT DESIGNING

Level shifter - This Project is carried out in TSMC 130nm TechnologyUsing Cadence Virutuoso layout editor tools. Verification like DRC, LVS done using Assura verification.

Responsibilities: Floorplan, Power plan, Placement, Routing, DRC, LVS,DFM of layout.

Op-amp- This Project is carried out in TSMC 130nm Technology and consists of different types of blocks and constraints like diff pairs, current mirrors, Layouts of individual blocks, top level integration of all these blocks done. Verification like DRC, LVS done using Assura.

Responsibilities: Floorplan, Power plan, Placement, Routing, DRC, LVS,DFM of layout.

DAC - This Project is carried out in TSMC 130nm,consists of capacitor array, amplifiers, comparator and half VDD power supply block and digital blocks. layout and physical verification like DRC and LVS was done.

Responsibilities: Floorplan, Power plan, Placement, Routing, DRC, LVS,DFM of layout

Band gap - This Project is carried out in TSMC 130nm Technology and Layouts of individual blocks, top level integration of all these blocks done. Verification like DRC, LVS ,DFM done by using Assura.

Responsibilities: Floorplan, Power plan, Placement, Routing, DRC, LVS,DFM of layout.

PLL - This Pll Project is carried out in TSMC 130nm Technology and consists of different types of blocks like VCO amp, Charge pump, Loop filter, Divider and Phase detector. Layouts of individual blocks, top level integration of all these blocks done. Verification like DRC, LVS done using Assura.

Responsibilities: Floorplan, Power plan, Placement, Routing, DRC, LVS,DFM of layout

Achievements:

Recognized in the team at Intel with 2 awards for diligently managing multiple timing ECO’s and related layout cleanup of fubs with high routing congestion.

Pratibha award from state govt. of AP for securing CEEP rank 160. Secured district first in a talent test conducted by oxford educational institutions. Secured district 1st & mandal 2nd ranks in two different chess competitions. Got seat in GIOE , SDECN branch.

Personal Assets:

Leadership qualities. Analytical skills & giving effective seminars. Hard working nature.

Personal Details:

DOB : 5th August 1993.Gender : MaleNationality : IndianFather name : Shaik Mustafa Address : Masjid centre, Dachepalli, guntur district, AP – 522414.Languages Known : English, Telugu, Hindi