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ALGORITHM FOR ASYMMETRIC SOURCECONFIGURATION IN A NEWLY CONSTRUCTED

MULTISTRING MULTILEVEL INVERTER TOPOLOGY

Kr ishna Kumar Gupta* , Shail endra Jain

* Maulana Azad National Institute of Technology Bhopal, India,* kk_mact@rediffmail.com, sjain68@gmail.com

Keywords: Multilevel inverters, cascaded H-bridge topology,reduced device count, symmetric and asymmetric sourceconfigurations .

Abstract

This paper proposes an algorithm to configure asymmetricsources for a recently proposed topology for multilevelinverters. Since the topology proposed by Yi-Hung Liao et. al[8] is incapable of synthesising all additive and subtractivecombinations of input DC levels (as happens in cascaded H-

bridge inverter), various popular asymmetric configurationscannot be employed for it. The proposed algorithm isdescribed in detail and it is shown that it helps to synthesisemultilevel waveform with equal sized steps.

1 Introduction

Multilevel voltage source inverters are considered cost-effective and efficient solution especially for high

power/medium voltage DC to AC conversion. A multilevelinverter (MLI) utilises multiple input DC sources tosynthesise a staircase waveform. As a result of this approach,voltage stresses across the power switches are lower ascompared to the output voltage level. Moreover, the steppedwaveform exhibits a better harmonic profile as compared to atwo level waveform produced by the conventional inverters.Other advantages of using MLIs are higher efficiency,reduced dv/dt stresses on the load and possibility of faulttolerant operation [1, 2].An important limitation of MLIs is requirement of increasednumber of power semiconductor devices (and accompanyinggate driver circuits) for increased number of output levels [3].This makes the overall system expensive and complex.Therefore, practical implementation of MLIs demandsreduction in number of switches and gate driver circuits. As aresult, attempts have been made by researchers to proposenewer topologies with reduction in device count [4-8].Focus of work presented here is a recently proposed MLItopology for distributed energy resources (DERs) [8]. Yi -Hung Liao et. al [8] have proposed a newly-constructed five-level multistring inverter topology for DERs. As shown inFig.1 (a) , the aforesaid topology requires only six activeswitches instead of the eight required in the conventionalcascaded H-bridge (CHB) multilevel inverter ( Fig.1 (b) ). Itwas established in [8] that the newly-constructed inverter

topology offers advantages such as improved outputwaveforms, smaller filter size, lower EMI and lesser totalharmonic distortion (THD). However, in literature [8], thetreatment of the aforesaid topology was limited to a five leveloutput with symmetrical input DC sources.

In this paper, a generalised structure of the topology is presented in Section 2. This section also discusses the conceptof symmetric and asymmetric source co nfigurations in MLIs.In Section 3 an algorithm is proposed for asymmetric sourceconfiguration for the proposed topology. Simulation resultsfor the proposed algorithm are shown in Section 4.Conclusions are presented in Section 5.

2 Generalised Structure of Topology Proposedin [8]

As shown in Fig.1 (a) , the topology in question contains sixactive switches and two isolated DC sources for a five level

output. An alternative structure of this topology is shown inFig.2. It can be noted that the consecutive sources are cross-connected i.e. the higher potential terminal of source V s1 isconnected to the lower potential terminal of the source V s2 through a power switch. Similarly, the higher potentialterminal of source V s2 is connected to the lower potentialterminal of source V s1 through a power switch. A similar scheme of connections can be extended for increased number of input DC sources. For n number of DC sources, thegeneralised structure of the topology is shown in Fig. 3. Itwould need 2 n + 2 power switches. For the same number of DC sources, a CHB topology would require 4 n power switches [9].The DC sources V sk (k = 1 to n) can be configured assymmetric or asymmetric. A brief description of sourceconfiguration is made below.

2.1 Source Configurations in MLIs The concept behind a multilevel waveform synthesis is toutilise multiple input DC sources. Multiple input DC sourcescan be obtained mainly in two ways:(i) using electrically isolated DC sources.(ii) using multiple capacitors in series so as to sub-divide theinput voltage from a single DC source.The first approach leads to requirement of large number of sources. Also, equal load sharing among them is a desirableand challenging task. On the positive side, there are novoltage balancing problems. The second approach does not

mailto:kk_mact@rediffmail.commailto:kk_mact@rediffmail.commailto:kk_mact@rediffmail.com

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need many DC sources but capacitor voltage balancingremains an important issue especially for increased number of levels in the output.

V s1

+

V s2

_

v o

(a)

Vdc

+

Vdc

_

v o

(b)

Fig.1. (a) Five level inverter as proposed in [8](b) CHB topology for five level output

V s1

V s2

S1 S1'

SU SU

SL SL

ACLOAD

N

1

2

+

_

v N

i L

Fig.2. Alternative form for the structure shown in Fig.1 (a)

The topology discussed in this paper uses the first approach,namely, using multiple isolated input DC sources. Based ontheir values, the source configuration are categorised as:

V s1

ACLOAD

+

_

v O

i L

V s2

V sn -1

V s n

Fig.3. Generalised structure for the topology proposed in [8]

(a) Symmetric Source Configuration:

When all the input DC sources have equal values, theconfiguration is designated as a symmetric sourceconfiguration. That is,

V s1 = V s2 = ... = V sk = ... = V DC (1)

Based on the topology, such configuration may offer advantages like modularity and possibility of equal loadsharing amongst the sources. However, for a given number of output levels, such configuration needs more power switchesas compared to an asymmetric configuration.

(b) Asymmetric Source Configuration

When two or more of the input DC sources have unequalvalues, the configuration is designated as an asymmetricsource configuration. Such a configuration enables lesser number of power switches to be used for the same number of output levels as compared to a symmetric configuration.However, it may lead to loss of modularity (if any) in thestructure. Also, it may not always be possible to achieve equalload sharing amongst the sources [10]. Some of popular asymmetric source configurations are [10,11]:

(i) Binary configuration : It consists of DC sources having ageometric progression with a factor of 1/2 i.e.

12

= 23

= = ( 1) = 2 (2)

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Binary configuration does not permit equal load sharingamongst the sources.

(ii) Trinary configuration : It consists of DC sources having ageometric progression with a factor of 1/3 i.e.

1

2= 2

3= = (

1) = 3 (3)

Trinary configuration does not permit equal load sharingamongst the sources.

(iii) As proposed in [10]: In this configuration, one source hasvoltage V DC while all other sources have values 3 V DC , that is,

V s1 = V s2 =... = V sk =...=V sn-1 = 3 V DC ; and V sn = V DC (4)

Such a configuration partially incorporates the advantages of

trinary configuration along with the possibility of equal loadsharing.

(iv) As proposed in [11] : In this configuration, one sourcehas voltage V DC while all other sources have values 2 V DC , thatis,

V s1 = V s2 =... = V sk =...=V sn-1 = 2 V DC ; and V sn = V DC (5)

Such a configuration partially incorporates the advantages of binary configuration along with the possibility of equal loadsharing.

3 Proposed Algorithm for Source Configuration

As mentioned in the previous section, using an asymmetricconfiguration leads to further reduction in number of switchesin a given topology with separate DC sources. However, for the proposed topology, the asymmetric configurationsdiscussed in previous section cannot be implementedsatisfactorily. For example, if the multistring topology issimulated using a trinary source configuration with V s1 = 100V and V s2 = 300V, all expected nine levels (-400V to 400V, insteps of 100V each) are not synthesised. For a nine-levelinverter, carrier and reference signals are shown in Fig 4 . Such a configuration in CHB would synthesise nine levels

shown in Fig 5 . However the multistring topology synthesisesseven levels with unequal step-sizes as shown in thesimulated waveform in Fig. 6.

Fig.4. Reference and carrier waveforms for a 9-level inverter

Fig.5. Output voltage waveform for a two-cell CHB inverter with trinary configuration ( V s1 = 100 V and V s2 = 300 V)

Fig.6. Output voltage waveform for the multistring inverter with trinary configuration ( V s1 = 100 V and V s2 = 300 V)

Similarly, if the multistring topology is implemented usingtrinary configuration with three sources, the source valueswould be: V s1 = 100 V, V s2 = 300V and V s3= 900V. Such aconfigurations offers possibility of twenty-seven levels (-1300V to 1300 V in steps of 100V each) which is achievedwith the CHB topology. However, the multistring topologygenerates only fifteen levels viz. 0, 100, 300, 400, 800,900, 1200 and 1300 V.

The aforesaid discussion indicates that the commonly usedasymmetric configurations cannot be implemented for themultistring topology. The reason is that it does not synthesiseall additive and subtractive combinations of the input DClevels. This can be inferred from Table 1. There are somevoltage levels which are skipped. Therefore, an appropriatealgorithm for asymmetric source configuration is requiredwhich can synthesise maximum number of steps with equalstep size.

In order to obtain a multilevel waveform with equal step-size,the aforesaid topology needs to use a natural number sequence of sources i.e. V DC , 2V DC , 3 V DC , .... , nV DC .Moreover, placing the sources at the correct positions isequally important. It is determined that the position of sourceshas to be as shown in Table 2, shown for up to ten DCsources.0.1 0.105 0.11 0.115 0.12 0.125 0.13 0.135 0.14

-4

-3

-2

-1

0

1

2

3

4

Time [sec]

R e f e r e n c e a n

d C a r r i e r W a v e f o r m s

0.1 0.11 0.12 0.13 0.14 0.15 0.16

-400

-300

-200

-100

0

100

200

300

400

Time [sec]

O u

t p u

t V o l t a g e

[ V ]

0.1 0.11 0.12 0.13 0.14 0.15 0.16

-400

-300

-200

-100

0

100

200

300

400

Time [Sec]

O u p u

t V o

l t a g e

[ V ]

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Number

of Sources

Source

Designation

Possible Voltage

Levels

Presence of

Voltage Level inthe MultistringTopology

Total number of

possiblecombinations

Total number of

possibilities offeredby the MultistringTopology

1 V s1 0 Present 3 3(V s1) Present

2 V s1 , V s2 0 Present 9 7V s1 PresentV s2 Present(V s1 - V s2) Missing(V s1 + V s2) Present

3 V s1 , V s2 , V s3 0 Present 27 15V s1 PresentV s2 PresentV s3 Present(V s1 + V s2) Present(V s1 V s2) Missing(V s1 + V s3) Missing(V s1 V s3) Present(V s2 + V s3) Present(V s2 V s3) Missing(V s1 + V s2 + V s3) Present(V s1 + V s2 V s3) Missing(V s1 V s2 + V s3) Missing(V s1 V s2 V s3) Missing

Table 1. Additive and subtractive combinations of input values and their presence/absence in the multistring topology

Numberof

Sources

Source Designation and their Values

V s1 V s2 V s3 V s4 V s5 V s6 V s7 V s8 V s9 V s10

1 V DC 2 V DC 2V DC 3 V DC 3V DC 2V DC 4 V DC 3V DC 4V DC 2V DC 5 V DC 3V DC 5V DC 4V DC 2V DC 6 V DC 3V DC 5V DC 6V DC 4V DC 2V DC 7 V DC 3V DC 5V DC 7V DC 6V DC 4V DC 2V DC 8 V DC 3V DC 5V DC 7V DC 8V DC 6V DC 4V DC 2V DC 9 V DC 3V DC 5V DC 7V DC 9V DC 8V DC 6V DC 4V DC 2V DC

10 V DC 3V DC 5V DC 7V DC 9V DC 10V DC 8V DC 6V DC 4V DC 2V DC

Table 2 Proposed placement of voltage sources in the proposed topology for up to ten number of input sources

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Accordingly, the proposed algorithm for asymmetric sourceconfiguration in the multistring structure is:

(i) For even number of sources:

V sj = (2 j - 1) V DC , for 1 j ( n/2),

= 2( n +1 j) V DC , for [( n + 2 )/2] j n (6)

(ii) For odd number of sources:

V sj = (2 j - 1) V DC, for 1 j [( n + 1)/2],

= 2( n +1- j) V DC , for [( n + 3)/2] j n (7)

4 Simulation Results and Comparison withSymmetric Configuration

In order to substantiate the algorithm proposed in the previoussection, some simulation studies are carried out usingMATLAB/Simulink.

(i) Simulation Study I Two sources with V s1 = 100V and V s2 = 200V are used for themultistring structure and it is expected that it can synthesiseseven levels in equal steps of 100V. Simulation is carried outwith these values and the results are shown in Fig.7. Theresults indicate that a seven level waveform is obtained with a

peak value of 300V and in equal steps of 100V.

Fig.7. Voltage waveform for Simulation Study I

( ii) Simulation Study II

Another inverter is simulated based on the multistringtopology with the following source values: V s1 = 100V, V s2 =300V, V s3 = 400V and V s4 = 200V as shown in Fig. 8.

The output waveform is expected to consist of twenty-onelevels with an amplitude 1000V and in equal steps of 100V.The simulated voltage waveform is shown in Fig.9. It is seenthat the output waveform achieves amplitude of 1000V in

equal steps of 100V.

V s1 = 100V

i o(t )

v o(t )

ACLoad

+ _

+ _

+ _

+ _

V s2 = 300V

V s3 = 400V

V s4 = 200V

Fig. 8 Multistring topology with four asymmetric sources

Fig.9. Voltage waveform for Simulation Study II

It can also be noted that for a seven level output, the topologywould require eight switches with symmetric sourceconfiguration and six switches with the proposed algorithmfor asymmetric configuration. Also, for a twenty-one leveloutput, the topology would need twenty-two switches withsymmetric source configuration and ten switches withasymmetric source configuration as proposed in the paper.Thus, asymmetric source configuration would further reducethe device count. A general comparison between number of switches and number of voltage levels produced by themultistring topology for the symmetric and the proposedasymmetric configurations are shown in Fig.10.

0.1 0.11 0.12 0.13 0.14 0.15 0.16

-300

-200

-100

0

100

200

300

Time [sec]

O u p u

t v o

l t a g e

[ V ]

0.1 0.11 0.12 0.13 0.14 0.15 0.16

-1000

-500

0

500

1000

Time [sec]

O u p u

t V o

l t a g e

[ V ]

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Fig 10. Number of power switches versus number of levels synthesized in the multistring topology with symmetric sourceconfiguration and with proposed configuration

5 Conclusion

This paper presents a newly formed algorithm for asymmetricsource configuration in a recently proposed multistringtopology by Yi-Hung Liao et. al [8]. A generalized structureof the multistring topology is formulated. It is shown that the

popular asymmetric configurations are not employable for themultistring topology since it does not synthesize all additiveand subtractive combinations of the input DC values. The

proposed algorithm is shown to satisfactorily synthesize allvoltage levels with equal sized steps. It is shown that the

proposed algorithm significantly reduces the number of power switches (and associated gate driver circuits).

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4 6 8 10 12 14 16 18 200

20

40

60

80

100

Number of Power Switches

N u m

b e r o f

L e v e

l s i n

O u t p u

t W a v e f o r m

With proposedasymmetric configuration

With symmetricconfiguration

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