SummaryParametersSpecificationsCalculated resultsSimulated results

Supply Voltage

1.8 V

Power Consumption< 750 W

Lowfrequency Gain A0> 65 dB

UnityGain Frequency f0>150 MHz

Slew Rate SR> 12.5 V/us

Phase Margin PM> 60

CMRR75 dB

PSRR> 75 dB at dc> 55 dB at 1 MHz

DC Output0.9 V +/50 mV

Differential Output Swing> +/0.75 V

Input Offset Voltage< 25 mV

(SingleEnded) Load Capacitor CL0.5 pF

IntroductionThe specifications require us to design high gain, low power, high bandwidth and highly stable fully differential operational amplifier. There are many fully differential operational amplifier topologies available but we selected two stage operational amplifier due to its high gain and high output swing. With one stage of differential amplifier, we could get a maximum 40dB gain so we added one more stage of common source amplifier to increase the gain. Adding one more stage introduced one more pole. This made the negative feedback as positive feedback and hence the circuit was highly unstable and thus we were unable to meet phase margin requirements. Thus we had to introduce miller capacitance between output of the two stages to push the two poles apart and make the second pole less than or equal to Unity gain frequency. This helped us to improve phase margin. The miller capacitance also introduced a zero in the circuit as there are now two paths from input to output. To control this zero we added a nulling resistor.Below is our schematic.

We are using tsmc35mm library. For this library unCox = 182.4uA/V and upCox = 44.4uA/VSteps of designing : 1. Choosing current : The minimum value of current can be chosen by considering slew rate specifications. Hence minimum Iss = SR*Cc = 12.5uv/s*0.5pF=6.25uAMaximum current allowed in circuit = power/vdd=750uw/1.8 = 416uA6.25uA is too low to achieve high input Gm for high bandwidth. Hence we decided to give 120uA, 80uA, 120uA respectively to each branch considering power budget.

2. Determining overdrive voltage of each transistor: Output swing = Vout,max-Vout,min = (VDD-Vov13-Vov10) < 0.75Vov13+Vov10 < Vdd -0.75 => Vov6+Vov7 < 1.05V For maintaining the symmetry of the circuit Vov5=Vov7=Vov9 For M1,M2 the Vov should be minimum as this is an input transistor that will contribute to high gain and high bandwidth. Thus keeping Vov1=Vov2=0.105V

3. Transistor sizing:For bias circuit NMOS, we needed Iref = Iout given by equation

For Iref as 13uA we have set (w/L)4 = 1.6/1, K = 1.12 and Rs = 1.165K

Simulation results1. After