AHB Slave Decoder

User Guide

12/2014

Capital Microelectronics, Inc.

China

User Guide of AHB Slave Decoder

http://www.capital-micro.com 2

Contents

Contents ................................................................................................................................................. 2

1 Introduction ..................................................................................................................................... 3

2 AHB Slave Decoder Overview ............................................................................................................ 4

2.1 Pin Description .......................................................................................................................... 4

2.2 Block Diagram ........................................................................................................................... 5

3 AHB Slave Decoder IP Usage ............................................................................................................. 6

3.1 AHB Slave Decoder operation timing diagram .............................................................................. 6

3.2 AHB Slave Decoder address mapping .......................................................................................... 8

4 Resource usage ................................................................................................................................. 9

5 Generate File Directory Structure .................................................................................................... 10

Revision History..................................................................................................................................... 12

User Guide of AHB Slave Decoder

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1 Introduction

This document mainly describes the usage of the AHB Slave Decoder IP. This IP is used to facilitate user to

connect up to 16 slaves to AHB bus. It works as slave of AHB Bus.

The AHB Slave Decoder IP supports the following features:

Compliance with the AMBA Specification, Revision 2.0 from ARM

Single and burst AHB transfer

Up to 16 AHB slaves, the slave number can be configured

AHB slave address space can be configured

- All slaves must have their address spaces aligned to a 1 K boundary.

- Minimum address space allocated to a configured slave is 1 K.

Device family support:

CME-M7

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2 AHB Slave Decoder Overview

2.1 Pin Description

Table 2-1 AHB Slave Decoder pin description

Interface Name Direction Width Description

system hclk Input 1 AHB interface clock

hresetn Input 1 AHB interface reset, low active

AHB bus

interface

haddr Input 32 AHB address bus

hsel Input 1 AHB slave select signal

htrans Input 2 AHB Transfer type signal

hwrite Input 1 AHB transfer direction:

1-write, 0-read

hsize Input 3 AHB Transfer size

hburst Input 3 AHB Transfer type signal

hresp Output 1 Transfer response signal

hready_out Output 1 Transfer done output

hwdata Input 32 AHB write data bus

hrdata Output 32 AHB read data bus

Slave

interface

hclk_s Output 1 Clock signal to slaves

hresetn_s Output 1 Reset signal to slaves, low active

haddr_s Output 32 Address bus signal to slaves

htrans_s Output 2 Transfer type signal to slaves

hwrite_s Output 1 Transfer direction signal to slaves

hsize_s Output 3 Transfer size signal to slaves

hburst_s Output 3 Transfer type signal to slaves

hwdata_s Output 32 Write data bus signal to slaves

hsel_s0

~

hsel_s15

Output 1 Select signals to slaves

hrdata_s0

~

hrdata_s15

Input 32 Read data bus signals from each

slave

hready_s0

~

Hready_s15

Input 1 Transfer done signals from each slave

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Table 2-2 AHB Slave Decoder parameter description

Name Type Value Description

NUM_SLAVES Integer 1~16 Number of AHB slave

START_PADDR_SN Integer

32’ha000_0000~

32’hbfff_fc00

or

32’hc000_0000~

32’hdfff_fc00

Start address of AHB slave N, 1K boundary

in FP0/FP1 address space

END_PADDR_SN Integer

32’ha000_03ff~

32’hbfff_ffff

or

32’hc000_03ff~

32’hdfff_ffff

End address of AHB slave N, 1K boundary

in FP0/FP1 address space

2.2 Block Diagram

Address Decoder

Read DataMux

AHB Slave Decoder

AHB Slave

Interface

AHB Slave 0

AHB Slave 15

. .

. .

. .

Hready Signal Mux

Figure 2-1 AHB Slave Decoder block diagram

The Address Decoder module will decodes the address input and generates the select signals to each

slave .Then the hrdata and hready signal are selected from Read Data MUX module and Hready Signal Mux

module according to the select signal of each slave.

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3 AHB Slave Decoder IP Usage

3.1 AHB Slave Decoder operation timing diagram

The AHB Slave Decoder IP transforms the signals from ARM Core to AHB control signals and outputs them to

AHB slaves. Meanwhile, the hrdata and hready_out are from each slave.

Figure 3-1 Basic write transfer

Figure 3-2 Basic read transfer

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

2

addr1

data1

0

TimeGen

hclk

hsel

haddr

htrans

hwrite

hready_out

hwdata

hready_s0

hsel_s0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

2 0

addr1

data1 0

data1

TimeGen

hclk

hsel

hwrite

htrans

haddr

hready_out

hrdata

hsel_s0

hrdata_s0

hready_s0

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Figure 3-3 Burst write transfer

Figure 3-4 Burst read transfer

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

2

d1

00 3

d2 d3 d4

a1 a2 a3 a4 a5

TimeGen

hclk

hsel

haddr

htrans

hwrite

hready_out

hwdata

hsel_s0

hready_s0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

2 0

d1 d2 d3 d4

a2 a3 a4 a5

0 3

d1 d2 d3 d4

a1

TimeGen

hclk

hsel

haddr

htrans

hwrite

hready_out

hrdata

hsel_s0

hrdata_s0

hready_s0

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3.2 AHB Slave Decoder address mapping

FP0

bfff_ffff

a000_0000

FP1

dfff_ffff

c000_0000

Figure 3-5 Address mapping

The ARM Core provides two groups of AHB Bus signals,AHB0 and AHB1, so there are two memory space for

user logic which are called as FP0 and FP1.It means that if you instantiate an ARM Core and choose the AHB0 ,

you must access your slaves on the address from a000_0000 to bfff_ffff, but if you connect the AHB Slave

Decoder to AHB1, the slaves can be accessed on the address from c000_0000 to dfff_ffff.

The slave number and each slave’s address space can be configured by user. The address space must be

aligned to a 1K boundary, for example, slave0’s address space is from a000_0000 to a000_03ff.

User Guide of AHB Slave Decoder

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4 Resource usage

Resource usage of the AHB Slave Decoder IP on Primace

Table 4-1 AHB Slave Decoder IP resource usage

Resource LUTs Regs

2 slave 440 16

4 slaves 480 16

8 slaves 480 16

16 slaves 460 16

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5 Generate File Directory Structure

The AHB Slave Decoder IP wizard generated file includes: source files (src), simulation files (sim) and example

design files and related document. The detailed design directory structure is as below.

Project

src outputs ip_core

ip_top.v(define by user)

ahb_slave_decoder.v

simsrc doc example

ahb_slave_decoder_tb_modelsim.f

ahb_slave_decoder_tb.v

CME_AHB_Slave_Decoder_user_guide_

EN01.pdf

slaves_decoder_test.zip

CME_AHB_Slave_Decoder_example_user_guide_EN01.pdf

= directory

= source RTL code

= simulation related files

= documentation

ahb_slave_decoder_v1

m7s_sim.v

M7S_SOC.v

ahb_slave_decoder_tb.do

*.v(other simulation related src files)

src

Figure 5-1 IP wizard generated file directory structure

Table 5-1 Generated File Directory structure

Directory Description

src\ Directory for project source code

ip_core\ The directory specially for all IPs

\ahb_slave_decoder_v1 Directory for AHB Slave Decoder IP

\doc\CME_AHB_Slave_Decoder_user_guide_EN01.doc User guide for AHB Slave Decoder IP

\src IP Design RTL

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\src\ahb _slave_decoder.v The src of AHB Slave Decoder IP

\sim

\ ahb_slave_decoder_tb.v Testbench file

\ ahb_slave_decoder _tb.do Modelsim simulation related files

\ ahb_slave_decoder _tb _modelsim.f

\m7s_sim.v Other files for simulation including IP

wizard generate files and lib files \M7S_SOC.v

\src

\*.v

\example

slaves_decoder_test.zip AHB Slave Decoder IP example

CME_AHB_Slave_Decoder_example_user_guide_EN01.pdf

The guide of AHB Slave Decoder

example

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Revision History

Revision Date Comments

1.0 2014-12-08 Initial release