Aging Gate Delay Model at Logic Circuit under NBTI Effect · Aging Gate Delay Model at Logic...
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Aging Gate Delay Model at Logic Circuit under NBTI Effect
郭海霞
Department of Electrical Engineering, and Shanghai Key
Laboratory of Multidimensional Information Processing,East China Normal University, Shanghai, China
2016-6-28 1
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1 Introduction
2 Aging Gate Delay Model
3 Validation and Discussion
contents
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IntroductionTheNBTIeffectdrivingthedeclineincurrentandtransconductance,subthresholdslopeincreasingandthresholdvoltageshi<,willincreasepropaga>ondelayofcombina>onalcircuits.UnderNBTIeffect,thethresholdvoltageofthePMOStransistorincreasesandcausesthedegrada>onoflogicgatesandeventuallyleadstothe>mingviola>ons.
reac>on-diffusion(R-D)theoryReac>on:Si–HorSi–Obondsatthesubstrate/gateoxideinterfacearebrokenDiffusion:reac>on-generatedspeciesdiffuseawayfromtheinterfacetowardthegatetrapping/detrapping(T/D)theoryTrapping:inelectricfield,chargeintheSiO2interfaceiscapturedbythedefectsintheoxideDetapping:removingelectricfield,thechargetrappingbreakawayfromoxida>onlayer. 3
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NBTI timing analysis framework
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The long-term prediction model
ΔVthforperiodicalinputpaVern
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n:>meexponent(1/6forH2diffusion)C:temperaturedependencefactorEa:ac>va>onenergyofhydrogenspeciesk:BoltzmannconstantEox:ver>calelectricalfieldTo,K1,Eo:temperatureandprocessdependentconstantsTclk:>meperiodofonestress-recoverycycleα:dutycycleisthera>oofthe>mespentinstressto>meperiodβe:thefrac>onparameteroftherecovery
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Obtain experimental data
Alltransistorsuse45-nm PTM model.pmos:180nm/45nmnmos:90nm/45nmVDD:1.1VTA:8nsTB:4nsα:0.5
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NAND
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CL(loadcapacitor):0fF~2fFti(inputslewrate):10ps~110pstp(gatedelay):3ps~53ps
NAND Gate Delay Model without Degradation
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(a)Themodeloftpwithoutdegrada>onandthesimulatedresults(b)theresidualsoftpbetweenmodelandthesimula>ons
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CL(loadcapacitor):0fF~2fFti(inputslewrate):10ps~110pstp(gatedelay):3ps~53ps
(a)Themodeloftowithoutdegrada>onandthesimulatedresults(b)theresidualsoftobetweenmodelandthesimula>ons
NAND Gate Delay Model without Degradation
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NAND Gate Delay Model without Degradation
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tp,fresh(CL,ti)tp,aging(ΔVth,ti)tp,aging(ΔVth,CL)
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NAND Gate Delay Model with Degradation
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Aging Gate Delay Model
to,fresh(CL,ti)to,aging(ΔVth,ti)to,aging(ΔVth,CL)
Detailsoftheprocess
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NANDGateDelayModelwithDegrada>on
tp,fresh(CL,ti)tp,aging(ΔVth,ti)tp,aging(ΔVth,CL)
to,fresh(CL,ti)to,aging(ΔVth,ti)to,aging(ΔVth,CL)
Aging Gate Delay Model
1,keeppingcommonitem2,addingcorrec>onitemforeveryfactor3,runninggenetic algorithm ofRandom7000setsofdatatogetcoefficients
2,Fijng
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tp,aging(CL,ti,ΔVth)
to,aging(CL,ti,ΔVth)
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Thedistribu>onoferrorbetweensimula>onandcalcula>onoftp,aging
Aging Gate Delay Model
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Freshpropaga>ondelay:Agedpropaga>ondelay:
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Pathdelaycalcula>onframework
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Validation and Discussion
circuitnetlistofC17inISCAS85andthepath
The inputpaVerns:Inputslew rate is 20ps.Inputduty-cycleof{I1,I2,I3,I6,I7}are{0.5,0.5,0.5,0.5,0.33}.Periodof{I1,I2,I3,I6,I7}are{8ns,4ns,4ns,8ns,3ns}.Thegatedegrada>onΔVthis0.05V
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Summary
1Analyzed the time delay under the effect of NBTI in combinational logic circuit.
2Using the curve fitting toolbox and the genetic algorithm to explore the propagation delay model with the NBTI considered.
3This method will also be extended to other logic gates.
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Thecalcula>onsofthedelaymodelwithoutandwithdegrada>onforC17benchmarkcircuit.
The histogram represents the path delay .Thelines represent the relative errors between the calculation and simulation.
Validation and Discussion
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Question Time
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Thanks!
2016-6-28
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