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Unit 5: Constraining I/O Paths5-1PrimeTime: Introduction to Static Timing Analysis

5-1

Constraining I/O pathsPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16

Agenda: Day Two

DAY2222 I/O Paths and Exceptions LabUnit

Introduction to Timing Models (QTM)7

8

Specifying Timing Exceptions6

Constraining I/O Interface Paths5

Summary9

Performing STA

Customer Support10


5-2


Unit Objectives

After completing this unit, you should be able to:

� Constrain the input and output (I/O) timing paths for single and multiple non-ideal clocks

� Determine when and how to use a Virtual clock

� Define common base period of synchronous multiple clocks


5-3


The Inputs and Outputs of PrimeTime

Reports

PrimeTime

Technology Libraries

SDFTiming

Models in .db format

Gate-LevelNetlist Constraints Exceptions

SetupFile

Log,Script Files

Our Focus


5-4


Five Step Static Timing Analysis Flow

READREAD

CONSTRAINCONSTRAIN

EXCEPTIONSEXCEPTIONS

CHECKCHECK

ANALYZEANALYZEOur Focus


5-5


Constrain Input and Output Timing Paths

In Unit-4, Path X was constrained bycreate_clock

D QFF4

T

D QFF3

M

B

Clock source

D Q D Q

Clk

Current_Design

FF1 FF2N S

u1u2 u3

u4

A

Network latencySource latency

Clock source

I/O Paths N & S are still unconstrained!


5-6


Input Arrival Time

The_Current_Design

ND Q

Clk

MD Q

TClk-q TM TNTSETUP

Next edge captures data

External Logic

(Input Delay)(TClk-q + TM) (TN + TSETUP)

Clk

A

Launch edge triggers

data

A

Clk

Valid new data

To meet the setup time of our flop:Tclk-q + Tm + Tn + Tsetup < Clock period


5-7


You specifyhow much time

is used byexternal logic.

PT calculateshow much time

is left for theinternal logic.

Launch Edge

1.5

delay ofexternal

logic

time leftfor

internallogic

Capture Edge

Constraining Input Paths

� set_input_delay -max

� Describes the maximum arrival time of external data with respect to a launching clock and an input port

pt_shell> set_input_delay -max 1.5 -clock Clk [get_ports A]


5-8


Exercise: : : : Constraining Input Paths

1.5

0.0 2.0 4.0

Clk

A

Constraint of YOUR input path

If U1 has a 0.37 ns setup time, what is the maximum delay for N?

A

Clk(250 MHz)

CLK-OUTPUT1.5 ns(worst)

EXTERNAL CIRCUIT

Clk

Clk latency: 0.8 nsSkew: 0.25 ns

The_Current_Design

U1

D QN

create_clock _______________________________________

set_clock_latency ___________________________________

set_clock_uncertainty _______________________________

set_input_delay ____________________________________

Points to remember:

1. Set_input_delay is specified w.r.t the launch clock.

2. Set_input_delay amount specified is measured from the launch clock edge.


5-9


Timing Report: : : : Constraining Input Paths

Point Incr Path---------------------------------------------------------------clock Clk (rise edge) 0.00 0.00clock network delay (ideal) 0.80 0.80input external delay 1.50 2.30 fA (in) 0.00 2.30 f…..

data arrival time 4.25

clock Clk (rise edge) 4.00 4.00clock network delay (ideal) 0.80 4.80clock uncertainty -0.25 4.55 rlibrary setup time -0.37 4.18data required time 4.18---------------------------------------------------------------data required time 4.18data arrival time -4.25---------------------------------------------------------------slack (VIOLATED) -0.07

Latency = 0.80

Input delay = 1.50

Period = 4.0

Latency = 0.80

Skew = 0.25

Slack violation

create_clock -period 4.0 [get_ports Clk]

set_clock_latency 0.8 [get_clocks Clk]

set_clock_uncertainty 0.25 [get_clocks Clk]

set_input_delay -max 1.5 –clock Clk [get_ports A]

report_timing –from [all_inputs]


5-10


Input Delay May Include Latency

In the previous timing report, would slack be different if you changed the clock latency?

What if the latency amount is already part of the input delay?Would you see a different slack?

A

Clk(250 MHz)

CLK-OUTPUT1.5 ns(worst)

EXTERNAL CIRCUIT

Clk

Clk latency: 0.8 nsSkew: 0.25 ns

The_Current_Design

U1

D QN

Includes latency


5-11


Timing Report: : : : Constraining Input Paths

Point Incr Path---------------------------------------------------------------clock Clk (rise edge) 0.00 0.00clock network delay (ideal) 0.00 0.00input external delay 1.50 1.50 fA (in) 0.00 1.50 f…..


clock Clk (rise edge) 4.00 4.00clock network delay (ideal) 0.80 4.80clock uncertainty -0.25 4.55 rlibrary setup time -0.37 4.18data required time 4.18---------------------------------------------------------------data required time 4.18data arrival time -3.45---------------------------------------------------------------slack (MET) 0.73

Latency = 0.00

Input delay = 1.50

Period = 4.0

Latency = 0.80

Skew = 0.25

Slack MET

create_clock -p 4 [get_ports Clk]



set_input_delay -network_latency_included -max 1.5 \

–clock Clk [get_ports A]

report_timing –from [all_inputs]


5-12


Specifying Input Driving Cell

� In order to accurately calculate the timing of input boundary cells, PT also needs to know the driving cell

� set_driving_cell allows the user to specify the external driving cell (thus transition time or slew rate) for input ports:

� The default drive on input ports is 0; Transition time is zero.� The driving cell also imposes its design rules (max_transition etc) on

the input port (and slows down the data)� You may also specify max and min driving cells; for setup and hold.

set_driving_cell -lib_cell buf1 [get_ports IN1]

IN1

buf1

You will experiment the effect of applying driving cell in the lab.


5-13


Output Setup Time

Clk

TT + TSETUP

Launch Edge Capture Edge

TClk-q + TS

(Output Delay)

Clk

B

SD Q

Ts

The_Current_Design

D Q

TT TSETUP

T

External Logic

U3 B

TClk-q

U3 Launches

Data

External Flip-Flop captures

data

Valid new data

To meet the external flop’s setup time:Tclk-q + Ts + Tt + Tsetup < clock period


5-14


LaunchEdge

CaptureEdge

1.75

You specifyhow much time

is needed byexternal logic.

PT calculateshow much time

is left forinternal logic.

Constraint for YOUR output path

Constraining Output Paths

� set_output_delay -max� Describes the setup time of an output port with respect to a

capture clock

pt_shell>set_output_delay -max 1.75 -clock Clk [get_ports B]


5-15


Exercise: : : : Constraining Output Paths

0.0 2.0 4.0

1.75

Data launchMust be valid

here

Clk

B

What is the maximum delay for the timing path through S?

Clk

SD Q

The_Current_Design

U3 BEXTERNAL CIRCUIT

SetupRequirement:

1.75 nsClock

(250 MHz)

Source latency: 0.5 nsNetwork latency: 0.3Skew: 0.25 ns

Use Clock period and skew constraints from the previous exercise

set_clock_latency ___________________________________

set_clock_latency -source ___________________________

set_output_delay ___________________________________

Points to remember:1.set_output_delay is specified w.r.t the capture clock.

2.set_output_delay amount specified is measured from the capture clock edge, towards the launch clock, (in the negative time direction).


5-16


Timing Report: : : : Constraining Output Paths

Point Incr Path---------------------------------------------------------------clock Clk (rise edge) 0.00 0.00clock network delay (ideal) 0.80 0.80…..B (out) 0.00 2.60 r


clock Clk (rise edge) 4.00 4.00clock network delay (ideal) 0.80 4.80clock uncertainty -0.25 4.55output external delay -1.75 2.80data required time 2.80---------------------------------------------------------------data required time 2.80data arrival time -2.60---------------------------------------------------------------slack (MET) 0.20

Source Lat : 0.50

Network Lat: 0.30

Period = 4.0

Source Lat : 0.50

Network Lat: 0.30

Skew = 0.25

Output delay: 1.75

Slack MET

create_clock -p 4 [get_ports Clk]


set_clock_latency –source 0.5 [get_clocks Clk]


set_output_delay -max 1.75 –clock Clk [all_outputs]

report_timing –to [all_outputs]


5-17


Output Delay May Include Latency

In the previous timing report, would slack be different if you changed the clock source or network latencies?

What if the latency amount is already part of the input delay?Would you see a different slack?

Clk

SD Q

The_Current_Design

U3 BEXTERNAL CIRCUIT

SetupRequirement:

1.75 nsClock

(250 MHz)

Source latency: 0.5 nsNetwork latency: 0.3Skew: 0.25 ns

Includes source, network latencies


5-18


Point Incr Path---------------------------------------------------------------clock Clk (rise edge) 0.00 0.00clock network delay (ideal) 0.80 0.80…..B (out) 0.00 2.60 r


clock Clk (rise edge) 4.00 4.00clock network delay (ideal) 0.00 4.00clock uncertainty -0.25 3.75output external delay -1.75 2.00data required time 2.00---------------------------------------------------------------data required time 2.00data arrival time -2.60---------------------------------------------------------------slack (VIOLATED) -0.60

Source Lat : 0.50

Network Lat: 0.30

Period = 4.0

source latency (incl)

network latency (inc)

Skew = 0.25

Output delay: 1.75

Slack VIOLATION

Timing Report: : : : Constraining Output Pathscreate_clock -p 4 [get_ports Clk]


set_clock_latency –source 0.5 [get_clocks Clk]


set_output_delay -source_latency \

–network_latency -max 1.75 –clock Clk [all_outputs]

report_timing –to [all_outputs]


5-19


Is this Output Path Fully Constrained?

How many output delay constraints are specified on Port B?What is the effect of connecting another 10 External logic to B?

SD Q

The_Current_Design

U3D Q

T

External Logic

B

D QT

External Logic

D QT

External Logic

Clk

Clk

Clk

Clk buf1


5-20


Specifying Output Capacitance (fixed)

� In order to accurately calculate the timing of boundary cells, PT needs to know the external capacitate loading

� set_load allows the user to specify the external capacitive load on ports:

� By default, the external load on ports is 0� You may also specify different min and max numbers

OUT15 pt_shell>set_load 5 [get_ports OUT1]

Useful at the very top level of the CHIP where the driving cell is an I/O buffer.


5-21


Specifying Output Capacitance (Derived)

A

OUT1

A

A

Use load_of lib/cell/pin to return the pin capacitance of a specific gate from the technology library.

OUT1AN2

A

B

Required BLANK spaces around the *

set_load [load_of ssc_core_slow/AN2/A] [get_ports OUT1]

set LOAD [expr [load_of ssc_core_slow/IVA/A] * 3]

set_load $LOAD [get_ports OUT1]

Suitable for sub blocks within the chip.


5-22


Test for Understanding

CHIP1CHIP1_CORE

BoardCHIP2

BLOCK2A

Clk

J = .1

CHIP2_COREPort Out1

EXTERNALPATH

DELAY = 2

INTERNALPATH DELAY

CLOCK NETWORK DELAY2

tu = 0.35

tsutsl1 = 0.5

tsl2 = 0.7

tn1 = 0.25

tn2 = 0.5

Your task is to constrain the input timing path(s) in CHIP2_CORE in the context shown above. Use the legend for the terms and the command template provided to you in the Notes section. There is a single clock Clk that controls 2 chips on a board. Your focus is on CHIP2_CORE.

Legend:Clk is 200 MHz Clock with a Jitter (J) = 0.1 and a maximum skew within each chip (tu) = 0.35CHIP1_CORE: Source Latency (tsl1) = 0.5, Network latency (tn1) = 0.25CHIP2_CORE: Source latency (tsl2) = 0.7, Network latency (tn2) = 0.5, Cell name driving CHIP2_CORE is is mux007NOTE1: Make reasonable assumptions for parameters not suppliedNOTE2: You do not have to use all the constraints below. You can, however, use additional constraints.create_clock ______________________________________________________________set_clock_latency __________________________________________________________set_clock_latency –source –early _____________________________________________set_clock_latency –source -late ______________________________________________set_clock_uncertainty ______________________________________________________set_input_delay __________________________________________________________set_driving_cell __________________________________________________________


5-23


Verify or Remove I/O Constraints

report_port -verbose:Returns all constraints and environment placed on all the input and output ports (delay, load, driving cell).

remove_capacitance:Removes capacitance load placed by set_load command

remove_driving_cell:Removes driving cell placed by set_driving_cell

remove_input_delay:Removes input delay constraints from specified ports

remove_output_delay:Removes output delay constraints from specified ports

Note that to remove the capacitance placed by the set_load command you should use the remove_capacitance command.


5-24


Synchronous Multiple Clock Designs

What is different?A: Multiple clock sources � All derived from the same clock source � Some clocks do not have a corresponding clock port

on our design� Multiple constraints on a single port

CLKA

CLKCCLKBCLKE

CLKDD Q D Q

The_Current_Design

FF2 FF3N X S

What do you do now?

Clocks are said to be synchronous if they are derived from the SAME clock source.


5-25


Answer: Use Virtual Clocks!

What are virtual clocks?

A: Clocks in the environment of the design that:� Are defined as clock objects � Do not clock any sequential devices within the current_design

� Serve as references for input or output delays


5-26


Creating a Virtual Clock

How do you create a virtual clock?

A: It is the same as defining a clock, but you do not specify a clock pin or port:

� You must name your virtual clock, since there is no clock port for the virtual clock

create_clock -name VCLK -period 5.00

No source pin or port!Must be named


5-27


Method for Synchronous Multiple Clocks

Method is the same as that for single clock designs: 1. Define the clock(s), using virtual clocks if necessary2. Specify I/O delays relative to the clock(s):

• PrimeTime will determine which clock imposes the most restrictive constraint on the design by finding Base Period

CLKA

(33 Mhz)

CLKC(50 Mhz) CLKE

(100 Mhz)

CLKD(75 Mhz)D

The_Current_Design

FF2 FF3

N X S

300 MHz

CLKA

CLKD

÷9

÷4

Q D Q

CLKE÷3

÷6 CLKC

Base Period is the Lowest Common Multiple (LCM) of all the clock periods involved. In the above example there are 2 base periods:

For the Input paths: Base period = LCM (20, 30) = 60 nsFor the output paths: Base period = LCM (20, 1000/75, 10) = 40 ns


5-28


Example: Multiple Clocks on Input Ports

create_clock -period 30 -name CLKA

create_clock -period 20 [get_ports CLKC]

set_input_delay 5.5 -clock CLKA -max [get_ports IN1]

create_clock -period 30 -name CLKA


set_input_delay 5.5 -clock CLKA -max [get_ports IN1]

0.5 nsCLK-Q

5.5 nsThe_Current_Design

IN1

CLKC

300MHz

CLKC

CLKA÷9

÷6

5 ns N

tN


5-29


Example Waveforms

For the example shown, input logic cloud of The_Current_Design must meet:

tN < 10 - 5.5 - tsetup

CLKC

CLKA

0 10 20 30 40 50 60

10 ns

÷6300 MHz

CLKA

CLKC

÷9What is the Base period?


5-30


Example: Multiple Clocks Output Ports

create_clock -period [expr 1000.0/75] -name CLKD

create_clock -period 10 -name CLKE


set_output_delay -max 2.5 -clock CLKD [get_ports OUT1]

set_output_delay -max 4.5 -clock CLKE -add_delay [get_ports OUT1]

2ns

4 ns

CLKD

0.5 nsSETUP

4.5 ns

2.5 ns

0.5 nsSETUP

CLKE

OUT1

The_Current_Design

CLKC

S

tS

NOTE: Do NOT use “13.3” as the clock period for CLKD when you cannot correctly represent it using finite decimals. Use “1000.0/75”. Also, do NOT use “1000/75”, the result will be truncated to integer 13.


5-31


Example Waveforms

For the example shown, output logic cloud of The_Current_Design must meet:

tS < 10 - 4.5

CLKC

CLKD

CLKE

÷4300MHz CLKC

CLKD÷6÷3

CLKE0 10 20 30 40

tS < 6.6 - 2.5AND

6.6

10

26.613.3

What is the Base period?


5-32


Recommendation: Keep the base period smaller than 10 * (the smallest clock period) whenever possible.

� By definition, all clocks used with PT are synchronous:� You can not create asynchronous clocks with create_clock

� PT will determine every possible data launch/data capture time, and perform STA to the most conservative constraint

� This can be very time consuming, when � difference in periods between multiple clocks is large� base period is too large

Hints for Multiple Clock Designs


5-33


Test For Understanding

1. Given 4 synchronous clock periods of: 3, 5, 20, 25 ns:

A) What is the Base period? ______________________________

B) Does this Base period follow our Recommendation, i.e. Tbase < 10 * min (periods)? ___________________________

C) How would this affect the runtime for PT? _______________________________

2. Does it make sense to specify source and network latency for a virtual clock?


5-34


Summary of I/O Path Constraints

set IN_EX_CLK [remove_from_collection \

[all_inputs] [get_ports Clk]]

set LOAD [load_of ssc_core_slow/AN2/A]

set_input_delay -max 1.0 -clock Clk $IN_EX_CLK

set_driving_cell -lib_cell FD2 -pin Q $IN_EX_CLK

set_output_delay -max 2.0 -clock Clk [all_outp]

set_load $LOAD [all_outputs]

redirect io.rpt {report_lib ssc_core_slow}

redirect -append io.rpt {report_port -verbose}


5-35


Lab Overview

� Given a design specification you will constrain all the I/O paths in the design

� You will ensure that all timing paths in the design have been constrained using check_timing

� You will generate timing reports for the longest I/O paths and interpret the effects of your applied I/O constraints

� You will vary the input driving cell, output load and observe their effects on the timing paths

LAB

60 min


5-36


Appendix

Constraining I/O for Hold Time check


5-37


When to Check for Hold Violations

� Small Violations:� Post layout: Check all hold-time violations using best case

operating conditions post-layout because� The clock tree is not in place until after layout� They often disappear when net parasitics are annotated

� Large Violations:� Pre-Layouit: Check only using the worst case operating

conditions for any large hold-time violations pre-layout

My design has met setup requirements.Is it a good time to check for hold?


5-38


Constrain for Hold Time: Input Paths

D Q D Q D Q

QB

D Q

QB

Clk

TO_BE_SYNTHESIZED

FF1 FF2 FF3 FF4M N X S T

set_input_delay -min describes the fastest arrivaltime of the external logic on the input ports.

create_clock -period 10 [get_ports Clk]set_input_delay -min 0.3 -clock Clk $all_in_ex_clk

create_clock -period 10 [get_ports Clk]set_input_delay -min 0.3 -clock Clk $all_in_ex_clk

min 0.3ns

If FF2 has THOLD = 1ns:What is the min delay allowed for N?


5-39


Constrain for Hold Time: Output Paths

D Q D Q D Q

QB

D Q

QB

Clk

TO_BE_SYNTHESIZED

FF1 FF2 FF3 FF4M N X S T

� set_output_delay -min :� Describes the hold time requirement of the external logic on the

output ports

0.3ns 0.5nsHold TimeRequirement

If FF has THOLD = 0.5ns and TT = 0.3ns:What is the min output delay?

If logic cloud T uses 0.3 ns, you need to have a minimum delay for FF3 (Clk->Q) plus logic cloud S of 0.2 ns in order not to violate the hold time requirement on FF4.


5-40


Calculation of Output Hold Time

create_clock -period 5 [get_ports Clk]set_output_delay -min (0.3-0.5) -clock Clk [all_outputs]

D Q D Q

QBClk

FF3 FF4TS

set_output_delay -max (Tmax + FF4setup)set_output_delay -min (Tmin - FF4hold)

setup = 0.8hold = 0.5

Tmin

0.3ns

-0.2

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