Advantages of 5th Generation Silicon Carbide (SiC) diode in...

Advantages of 5th Generation Silicon Advantages of 5th Generation Silicon Carbide (SiC) diode in Switched-Mode P S li D iPower Supplies Design

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for 21ic Power Technologies Conference

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Content

Design Trends and Requirement of SMPS

Why SiC in SMPS?

Current Rating of SiC diodeCurrent Rating of SiC diode

What is the Benefits of Infineon 5th Generation SiC Diode?

Infinoen SiC Diode Product Portfolio

Summary

For internal use only2012-07-30 Copyright © Infineon Technologies 2010. All rights reserved.

Design trends and requirement of SMPS

High efficiency

h 80 l C tifi ti li t ti d such as 80 plus Certification, climate savers computing, and energy star

f iPower factor requirement

such as IEC-61000-3-2 (EU standard), Energy star and 80 plus Certification requested power factor =>0 9)plus Certification requested power factor =>0.9)

High power density

40W 50W/i ³


40W-50W/in³

2012-07-30 Copyright © Infineon Technologies 2010. All rights reserved.

Why SiC in SMPS?

For example: CCM Boost converter

When the power switch turn on the power diode will be When the power switch turn-on, the power diode will be opened. However, due to silicon diode physical limitation, the diode will keep the current pass from cathode to anode (red

t th) t h t i d ticurrent path) at a short period, reverse recovery time.

This event makes:

High voltage spike at power devices

Power losses at power devices


EMI issues and limited switching frequency

2012-07-30 Copyright © Infineon Technologies 2010. All rights reserved.

Advantages of silicon carbide over SiKey Features SiC:

Low switching losses due to nearly no

reverse recovery charge or stored charge

Switching behavior independent on forward

c ent s itching speed and tempe at ecurrent, switching speed and temperature

Key benefits SiC:

Improved EfficiencyImproved Efficiency

Allows use of smaller MOSFET

Cost / Size savings due to reduced cooling i i d irequirements increase power density

Reduced EMI

Increased system reliabilityIncreased system reliability

Strong market adoption driven by clear benefits over Si in target markets (Server, Telecom Solar UPS) IFX SiC 6A

Copyright © Infineon Technologies 2008. All rights reserved. For internal use only

Telecom, Solar, UPS) Si pin double diode 1 (6A)Si pin double diode 2 (6A)

2012-07-30

Continuous forward current: IF

Eg. IDH06SG60C

Diode Forward Voltage, VF = 2.3V (Max @ Tj=25oC)

Diode Forward Voltage, VF = 2.8V (Typ @ Tj=150oC)g , F ( yp j )

¬ VF characteristic make SiC diode easily to parallel

Max. allowable junction temperature, TJMax=175oCMax. allowable junction temperature, TJMax 175 C

RthJC=2.1k/W

All bl di i ti Allowable power dissipation:

Ptot = f(Tcase) = (TJMax-Tcase)/RthJC

IF=f(Tcase)= Ptot (Tcase)/VF(@Tj)

Copyright © Infineon Technologies 2008. All rights reserved. For internal use only2012-07-30

Forward current with duty cycle

SiC diode current test with duty

cycle:

Duty cycle of diode conduct

y

Junction temperature lower or

equal to 175oC (T )equal to 175oC (TJmax)

Testing switching frequency:

=5kHz

Eg. at duty cycle =0.5 100oC

g y y

(switching frequency higher

than 5kHz) and case 11A

)

temperature=100oC (TC),

IDH06SG60C can pass 11 A.

Copyright © Infineon Technologies 2008. All rights reserved. For internal use only

p

From IDH06SG60C datasheet2012-07-30

Definition of non-repetitive peak forward current (IF,max)

Definition of current pulse. (tp=10µs and TC =100oC )

From IDH06SG60C datasheet

Current(A)

10µs

Current(A)

Time (μs)10µs

The value is defined base on destructive current measurement with 30% de-rating.

Copyright © Infineon Technologies 2008. All rights reserved. For internal use only Page 82012-07-30

Selection guidance for SiC diode

Worse case surge

t

Vin, Po, η, Fsw,

Fmain, Vout

Tc @ low

current profile

Vout

Tc @ low line, Full loading

Appropriate ThinQ! Diode

Set date Copyright © Infineon Technologies 2010. All rights reserved.

Estimation of the boost diode rms current

Procedure:

1 Input current base on a prefect PF 1Vin, Po, η,

Fsw 1. Input current base on a prefect PF = 1.

2. Estimate inductor according to desire high frequency ripple current ~ 30% of current

Fsw, Fmain, Vout

frequency ripple current. 30% of current envelope.

3. Generate the maximum and minimum diode current.

4. Evaluate the RMS current of the diode.

5. Selection of ThinQ! diode base on current rating @ 130oC.5. Selection of ThinQ! diode base on current rating @ 130 C.


Estimation of the boost diode rms currentMathCAD calculation:

F_main 50:=

Vin_rms 230:=

f 62 5 10 3

ΔIL_ON t( )V_in t( )

LpDs t( )⋅

1fs

⋅:=

Δ IL OFF t( )Vout V_in t( )−

Dd t( )1

:fs 62.5 10⋅:=

Po 300:=

η 0.9:=

Vout 400:=

Δ IL_OFF t( )Lp

Dd t( )⋅fs

⋅:=

Idiode_max t( ) I_in t( )12

Δ IL_OFF t( )⋅+:=

T_main1

F_main:=

ω 2 π⋅ F_main⋅:=

t_main 01

fs 10⋅, T_main..:=

Idiode_min t( ) I_in t( )12

ΔIL_OFF t( )⋅−⎛⎜⎝

⎞⎟⎠

I_in t( ) ΔIL_OFF t( )>if

0 otherwise

:=

Idiode rms1

T_main

t mainIdiode max t main( )( )2⌠⎮ d

⎡⎢⎢

⎤⎥⎥:=V_in t( ) Vin_rms 2⋅ sin ω t⋅( )⋅:=

Iin_rmsPo

η Vin_rms⋅:=

I_in t_main( ) Iin_rms 2⋅ sin ω t_main⋅( )⋅:=

Idiode_rmsT_main 0

t_mainIdiode_max t_main( )( )⎮⌡

d⎢⎣

⎥⎦

:=

Idiode_avg1

T_main 0

T_maint_mainIdiode_max t_main( )( )

⌠⎮⌡

d:=

Idiode_rms 1.818= Idiode_avg 1.691=

Ds t( ) if 1V_in t( )

Vout−⎛⎜

⎝⎞⎟⎠

0.9> 0.9, 1V_in t( )

Vout−⎛⎜

⎝⎞⎟⎠

, ⎡⎢⎣

⎤⎥⎦

:=

Dd t( ) 1 Ds t( )−:= 2.4

3

Idiode_max t_main( )

Idiode min t main( )

LpVin_rms 2⋅

Vout Vin_rms 2⋅−

Vout

fs

⎛⎜⎜⎝

⎞⎟⎟⎠

⋅

0.3 2 Iin_rms⋅:= 0.6

1.2

1.8Idiode_min t_main( )

I_in t_main( )

Idiode_rms

Idiode_avg


Lp 1.581 10 3−×= 0 5 10 3−× 0.01 0.015 0.020

t_main

Anticipate the worse case surge currentProcedure

Various case can happen but typicallyWorse

case surge

Simply half cycle missing may not be the worse case. It needs to consider of below:

1 D ti ti f b di d ( V *1 4 Vb lk l

current profile

1.Deactivation of bypass diode ( Vrms*1.4 = Vbulk, as lease as close as possible)

2.Deactivation of soft start by PWM (Check the under voltage 2.Deactivation of soft start by PWM (Check the under voltage lock out condition, observable in Vgs in ms time scale)

3.High line at maximum input voltage. ( 90o or 270o of input sinewave)sinewave)

4.Disable the inrush limiter. (Check if the relay is re-turn on)

5 Lower the bulk capacitor voltage as possible5.Lower the bulk capacitor voltage as possible.


Anticipate the worse case surge currentMeasurement

Green: inductor currentYellow: MOSFET duty cycle


Estimation of junction temperature when the SiC diode in surge mode

Simulation base on Tc @ low li F llSIMetrix.

Obtain the surge current in CSV format

line, Full loading

current in CSV format

Program the current in PWL file.

1kR1

IDH04SG60C_L3T0=80 ratio=540m

U1

ANODEC1

I2PWL file.

Estimate the junction temperature with a

ANODE

KATODE TCASETREF

C110p

given case temperature (Tc).

Tc is measured in Full Tc is measured in Full load, low line condition.


Simulation Result as a demonstration

Inspection if

Y2

120

Y1 IDH04SC60C

Inspection if junction temperature below

175oC

115

6

7

< 175oC.

degC

/ D

egC

105

110

5

6

Tem

pera

ture

@ T

c =

80d

100

Dio

de C

urre

nt /

A

4

Junc

tion

T

90

95

2

3

85 1


Time/mSecs 2mSecs/div

-2 0 2 4 6 8 10 12 14 16 18 20 22

Infineon thinQ!™ SiC diode (600-650V):

Enhanced surge current capability by introductionof a Merged-pin-structure

4040

G5 650V technology:

f

Product definition and market positioning

20

25

30

35

(A) surg

e cu

rrent

Schottky diodeforward characteristic

Combined characteristics

20

25

30

35

(A) surg

e cu

rrent



surg

e cu

rrent



all former improvements + new design and wafer thinning technology

price and performance improvements

5

10

15

20I F

Bipolar pn diodeforward characteristic

5

10

15

20I F

Bipolar pn diodeforward characteristicBipolar pn diodeforward characteristicG22005 G5 main product characteristics:

I d Vb t 650V

Pric

e

00.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00

VF (V)

00.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00

VF (V)

Diffusion soldering: ≥ 40% reduction of thermal resistance

G520121. Increased Vbr to 650V

2. Wafer thinning resulting in:

Surge current capability at G2 levelgfor same chip area (IFX patent)

Soft soldering Diffusion soldering

G32009 Improved thermal performance

3. Improved efficiency with respect to

i ti

Performance Si

previous generations

4. Extension of portfolio up to 40A

5. New Packages (TO247, ThinPAK)


(efficiency, density)6. Pricing : below Gen 2

Wafer thickness and surge capability

Wafer thickness reduced to 1/3 (110µm)

Consistent reduction of substrate resistance(main contributor above 20 A/mm2)

G5Lower Vf increase by high current spikes

Higher surge current capability

G2-G3

G5

g g p y(per unit Area)

G)

2G

an

d 3

G

0µ

m (

5G

)

Current

R bulk

35

0µ

m (

2

11

0


Wafer thickness and thermal performance

bond metal

Wire bond

Also thermal resistance is reduced:

• Better heat spread through lead-frame• Lower chip temperatureSiC Substrate

Schottky contactDrift layer R bulk

• Lower chip temperature• Lower losses.

SiC Substrate

Backside metal

Heat flow

Thermal simulation: Equal sized chips in TO-220, Plosses=75W

G5G3G2 Lead-frame G5G3G2Rth=2.0 K/W Rth=1.5 K/W Rth=1.2 K/W

Wafer chip Diffusion Sold. Diffusion Sold.+ Thin-Wafer


Lower Figure of Merit Vf x Qc

Gen2 diodes have been optimized for low forward voltage (Vf)

Gen3 are optimized for lower capacitive charge (Qc), higher Vf

Gen5 shows comparable Qc than Gen3, and Vf at Gen2 level

G2

osse

sQC

G3

Sw

. Lo

1 4 1 5 1 6 1 7 1 8 1 9

G3

G5Cond. Losses


1.4 1.5 1.6 1.7 1.8 1.9

vf2012-07-30 Copyright © Infineon Technologies 2010. All rights reserved.

Lower Figure of Merit Vf x Qc Device performance

0.15

G5

Efficiency comparison among 8A IFX diodes (absolute values left; relative to G5 right)

98.4

0

0.05

0.1

Dif

fere

nce [

%]

G5

G2

G3

CCMode PFC, High line

Pmax=1800 W

fSW=65 kHz97 6

97.8

98

98.2

Dif

fere

nce [

%]

-0.15

-0.1

-0.05

10 20 30 40 50 60 70 80 90 100

Eff

icie

ncy

Theat Sink=60°C

MOSFET:IPW60R075CP (Rg=5 Ohm).

97

97.2

97.4

97.6

10 20 30 40 50 60 70 80 90 100

Eff

icie

ncy

G5

G2

G3

Ouput Power [% Nominal]

Improved performance over all load conditions!

Low load performance at comparable level with G3

Heavy load performance at comparable level with G2


98

98.2

98.4

cy [

%]

G5

G2

G3

0 05

0.1

0.15

0.2

ce [

%]

G5

G2

G3

fSW=100 kHz

97 2

97.4

97.6

97.8

Cir

cu

it E

ffic

ien

0 15

-0.1

-0.05

0

0.05

Eff

icie

ncy D

iffe

ren

SW


97

97.2

10 20 30 40 50 60 70 80 90 100Ouput Power [% Nominal]

-0.2

-0.15

10 20 30 40 50 60 70 80 90 100

E


Planned product portfolio

Vbr = 650V for all G5 products

Maximum current rate increase from 16A (G2) up to 40A

TO220 R2L TO247 D2PAK R2L ThinPAK 8x8

3 new packages: TO247, D2PAK-R2L, ThinPAK

TO220 R2L TO247 D2PAK R2L ThinPAK 8x8

2A IDH02G65C5 IDK02G65C5 IDL02G65C53A IDH03G65C5 IDK03G65C54A IDH04G65C5 IDK04G65C5 IDL04G65C55A IDH05G65C5 IDK05G65C56A IDH06G65C5 IDK06G65C5 IDL06G65C58A IDH08G65C5 IDK08G65C5 IDL08G65C59A IDH09G65C5 IDK09G65C510A IDH10G65C5 IDW10G65C5 IDK10G65C5 IDL10G65C512A IDH12G65C5 IDW12G65C5 IDK12G65C5 IDL12G65C516A IDH16G65C5 IDW16G65C520A IDH20G65C5 IDW20G65C5


30A IDW30G65C540A IDW40G65C5

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