Advances in Verilog-A compact semiconductor device modelling with Qucs/QucsStudio

10 years of Qucs/QucsStudio GPL development in10 years of Qucs/QucsStudio GPL development insupport of circuit simulation and compact device modellingsupport of circuit simulation and compact device modelling

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Background and scope of presentation● Qucs/QucsStudio development roadmaps● Qucs/QucsStudio changes since 2011● Qucs/QucsStudio ADMS compact model construction ● Current state of ADMS development● ADMS 2.30 Verilog-A subset● Qucs/QucsStudio special ADMS features● Known problems with ADMS● New Qucs/QucsStudio Verilog-A models● New system simulation features● Future plans● Summary

M. E. BrinsonCentre for Communications Technology

London Metropolitan UniversityLondon N78DB, UK

mbrin72043@yahoo.co.uk

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Introduction : Qucs development roadmap

Date Release Notes [Highlights]

Dec. 2003 0.0.1 First public version of simulator - very basic.Jun. 2004 0.0.2 First MacOS version.Sep. 2004 0.0.3 Implemented S-parameters and noise analysis. Added microstrip components and

BJT and MOSFET devices.Mar. 2005 0.0.5 Implemented AC analysis and basic transient analysis.May 2005 0.0.6 Mainly bug fixes and extensions to implemented analysis.Jul. 2005 0.0.7 Windows 32 version. Simulator renamed as Qucs. New device library manager.

Added post simulation data processing mathematical functions.Jan. 2006 0.0.8 Support for pure digital simulation using FreeHDL. Added many new component

models. Improved post simulation data plotting features. Added a filter synthesis tool.May 2006 0.0.9 New functions in equation solver. Harmonic Balance simulation introduced. Many

new components added.Sept. 2006 0.0.10 Qucs converter tool improved. Support for nine-valued VHDL logic. Circuit optimization

introduced using ASCO. Added attenuator design tool.Mar. 2007 0.0.11 Added device parameters to equations and parameters to subcircuits. New models plus

improvements to existing models. Using ADMS to translate Verilog-A device models foruse in Qucs.

Jun. 2007 0.0.12 Lots of new components, bug fixes and small improvements. Added support for Verilog using Icarus Verilog. Support for symbolically equation-defined devices (EDD). Explicit equations allowed.

Nov. 2007 0.0.13 General improvements plus implementation of immediate vectors and matrices in equations.Apr. 2008 0.0.14 Implemented multi-port equation-defined RF device (RFEDD) S, Y and Z parameters

available. Two-port equation-defined device also supported.Apr. 2009 0.0.15 Mainly bug fixes, small improvements and the addition of new models.Mar. 2011 0.0.16 Implemented interactive post simulation data processing using Octave. Again many bug

fixes, small improvements and the addition of new models.Feb. 2013 0.0.17 New experimental Qt4 version of Qucs release 0.0.16. Added microstrip Lange coupler.

New Octave post-simulation data processing functions. Added HICUML2V2p31 model.

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Introduction : QucsStudio development roadmap

Date Release Notes [Highlights]

Feb. 2011 1.0.0 First public version of simulator- features include more than 100 different circuit components, DC analysis, AC analysis (including noise analysis and noise distribution analysis), S-parameter analysis (including noise simulation), transient analysis, Harmonic Balanceanalysis (including noise simulation), system simulation, parameter sweep and optimizationof analogue circuits, digital simulation with ICARUS Verilog,PCB layout using KiCAD, numerical data processing using Octave, RF transmission line calculation (coaxial, microstrip,coupled microstrip, coplanar line, stripline, twisted pair rectangular wavequide etc., filter synthesis (LC ladder, stepped-impedance, microstrip, active filters etc., attenuator synthesis, and GPIB control.

Mar. 2011 1.1.0 Added VHDL digital simulation with GHDL plus numerous bug fixes.

Jun. 2011 1.2.0 Many small improvements plus bug fixes.

Nov. 2011 1.3.0 Added compiled C++ and Verilog-A device and circuit models using MinGW and ADMS, more bug fixes and small improvements. Released QucsStudio-light: QucsStudio without Octave and model Compiler.

Feb. 2012 1.3.1 Verilog-A: new syntax for highlighting, $given() function, preprocessor flag 'insideQucsStudio',better parameter extraction in Verilog-A files, port names in Verilog-A symbols. Linear branchesin Verilog-A. Added stoh() function. Windowing for time2freq() function. HB now allows Frequency sweeps. Many small improvements plus bug fixes.

April 2012 1.3.2 Added functions length(), arcsin() and arccos() in equations. Added export filter for Xfig3.2 format. Added system simulation icon to simulation group. Added German translation for texteditor. Many small improvements plus bug fixes.

July 2012 - 1.4.0 - Many small improvements plus bug fixes. New components like photodiode. QucsStudio nowFeb. 2013 1.4.4 creates Octave MEX files from its GUI. New difference marker. SPICE models to a schematic

per drag-n-drop. Conversion of SPICE models to QucsStudio library. QucsConv now supportsSPICE POLY in dependent sources and ENDS at end of .MODEL statements. Power output

option (including transient simulation). Lots of bug fixes.

Qucs/QucsStudio: Developments since 2011

2003-2011 Qucs0.001-0.016 (Qt3)

QucsStudio (Qt3) Feb. 2012

NewModels

Qucs 0.0.17 (Qt4/Qt3) Dec. 2012

New analogue simulatorSystem simulation PCB layoutGPIB device controlSingle and multi-tone input HB simulation

Print duration of simulation in ms Bug fixes

Add templatesCompiled model using ADMS and MinGW Functions stoy() and stoz() Bug fixes

Frequency sweeps for HBToolbar icon for DC simulation Linear branches in Verilog-A Windowing for time2freq() Function stoh() Bug fixes

Add functions length(),arcsin() and arccos() Bug fixes

Generation of Octave mex files from GUI Function stoa()Noise sources for transient analysis Bug fixes

New Octave post-simulation data prossing functions

Sourceforge.net qucs-qt4 branch snapshot: Windows and Ubuntu 12.04/12.10 Linuxhttp://sourceforge.net/projects/qucs/files/qucs-binary/0.01

QucsStudio Homepage Windows version 1.4.3 LATEST VERSION 1.4.4http://www.mydarc.de/dd6um/QucsStudio/qucsstudio.html

Microstrip Lange coupler

MESFET models Curtice Statz TOM1 TOM2 TOM3EPFL EKV 2.6

Long channel

PhotodiodePotentiometer

HICUM L0, L2_full BSIM 3.24 BSIM 4.30

Pin diode Reverserecovery diode

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Latest HICUM L2 model added Qucs 0.0.17 (Qt4/Qt3) Dec. 2012

Qucs 0.0.17 (Qt4) 2013

HICUM L0, L2_full

HICUML2V2p31

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Generating Qucs Verilog-A compact device models: Introduction

● The following diagram illustrates the initial stage in the construction of a Qucs Verilog-A compact device model.

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Model symbolpin names

Equation-defined devicemodel

Verilog-Acode

fragments

1. Compile Verilog-A template code with ADMS-2.302. Add new model to Qucs by patching C++ code (see next slide)3. Add new model symbol to Qucs C++ code (see next slide)4. Compile and link Qucs static C++ code to generate a new version of Qucs

//Verilog-A model template//`include “disciplines.vams”`include “constants.vams”module name (P1, P2, P3, ....... Pn);inout P1, P2, P3, ....Pn;electrical P1, P2, P3, ..... Pn;// Definition of local internal nodes// Parameter values and descriptions// Definition of internal variablesanalog begin// Initialisation code// Model quantity equations// Current contributions// Noise contributionsendendmodule

Generating Qucs Verilog-A compact device models: Template code

Generating Qucs Verilog-A compact device models: C++ code patches;new model REGISTRATION process

1. Qucs-core1.1 Directory ../src/components/verilog Modify file Makefile.am ADD to libverilog_SOURCES = ... XXX.analogfunction.cpp XXX.core.cpp ADD to noinst_HEADERS = …. XXX.analogfunction.h XXX.defs.h XXX.core.h ADD to VERILOG_FILES = …. XXX.va ADD to “if MAINTAINER_MODE” An entry for XXX (use existing code as a (template)1.2 Directory ../src/components Modify file components.h ADD #include “verilog/XXX.core.h”1.3 Directory ../src Modify file module.cpp ADD REGISTER_CIRCUIT(XXX);

Compiling XXX.va with ADMS-2.30 results in files XXX.core.cpp, XXX.core.hXXX.defs.hXXX.gui.cpp, XXX.gui.hXXX.analogfunction.cpp

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5. Qucs5.1 Directory ../qucs/qucs/components Modify file Makefile.am ADD to libcomponents_a_SOURCES = ... XXX.cpp ADD to noinst_HEADERS = …. XXX.h5.2 Directory ../qucs/qucs/components Modify file components.h ADD #include “XXX.h”5.3 Directory ../qucs/qucs Modify file module.cpp ADD REGISTER_VERILOGA_1(XXX);

2. model symbolAfter entering the Verilog-acode for a new model, pressingkey F9 will automatically generatea Qucs schematic symbol for thenew model. This may be editedusing the Qucs drawing tools.On saving the symbol Qucs writes the C++ drawing code for the symbol to file XXX.dat in the working project directory.

3. Qucs model graphicsCopy files XXX.gui.cpp and XXX.gui.h to directory ../qucs/qucs/components as filesXXX.cpp and XXX.h respectively.3.1 File XXX.cpp(a) Change the XXX.cpp statement #include XXX.gui.h to #include XXX.h(b) Change code line Name =”T”; to a more appropriate name, like Name = “BJT”; (c) Replace the symbol drawing statement, at the bottom of the file, with the C++ code held in file XXX.dat.

4. Model bitmap4.1. Generate a 30x30 pixel bitmap (png format) using Gimp.4.2 Save XXX.png in Qucs directory ../qucs/qucs/bitmaps.4.3 Modify file Makefile.am in directory ../qucs/qucs/bitmaps to include Model name XXX.png in “XPMS= ...”REGISTER NEW MODEL

Qucs uses static C++ libraries

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CompactSemiconductorDevice or circuit

macromodels

CompactSemiconductorDevice or circuit

macromodels

CompactSemiconductordevice or circuit

physicalequations

Equation-defineddevice model

or circuit macromodel

Verilog-Afragments

Verilog-Amodelcode

[Templatestructure]

C++ Compiled model

C++

Pin1

::

Pinn

Pout1

Poutn

Symbol

Pin1

::

Pinn

Pout1

Poutn

Subcircuitsymbol

Generate Verilog-A codewith the QucsStudio

colour highlighted text editor

File XXX.va

File XXX.va.cpp

File XXX.dll

“Turn-Key” Verilog-A compact model development system WHERE the Verilog-Acode is automatically recompiled ONLY if it has been changed prior to the start of a simulation

Other QucsStudio components may be included in asubcircuit with one or more compiled C++ models

Subcircuit body API functions for C++

component creation

ADMSMinGW tools

QucsStudio: Compact semiconductor device and circuit macromodel construction using ADMS and MinGW dynamically linked models

Mike E. Brinson, and Michael Margraf, Verilog-A compact semiconductor device modelling and circuit macromodelling with theQucsStudio-ADMS “Turn-Key” Modelling System, International journal of Microelectronics and Computer Science, Vol. 3, No1,2012, pp. 32-40, ISSN 2080-8755.

QucsStudio/MinGWuses dynamic linked C++ libraries

QucsStudio: Compact semiconductor device and circuit macromodelcompiled Verilog-A binary model libraries

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EDD model

C++ code

RNL.va.cpp template file

Subcircuit Symbol

Attach

QucsStudio: Compact semiconductor device and circuit macromodelcompiled Verilog-A binary model libraries

Display symbol

Edit: click on Copy C++ symbol

// ----------------- evaluate verilog analog equations -------------------- R_VPin_Pout=(R0*((A)+(((B)*sys->getV(Pin, Pout))+(B*sys->getV(Pin, Pout))))); R=(R0*((1+(A*sys->getV(Pin, Pout)))+((B*sys->getV(Pin, Pout))*sys->getV(Pin, Pout))));

sys->setIQ(Pin,Pout,(sys->getV(Pin, Pout)/R),0); sys->setGC(Pin,Pout,Pin,Pout,((R-(sys->getV(Pin, Pout)*R_VPin_Pout))/R/R),0);}char icon[236] = { 0x89,0x50,0x4E,0x47,0x0D,0x0A,0x1A,0x0A,0x00,0x00,0x00,0x0D,0x49,0x48,0x44,0x52, 0x00,0x00,0x00,0x22,0x00,0x00,0x00,0x16,0x08,0x02,0x00,0x00,0x00,0x2A,0xCE,0xD9, 0x2E,0x00,0x00,0x00,0x09,0x70,0x48,0x59,0x73,0x00,0x00,0x0B,0x13,0x00,0x00,0x0B, 0x13,0x01,0x00,0x9A,0x9C,0x18,0x00,0x00,0x00,0x07,0x74,0x49,0x4D,0x45,0x07,0xDD, 0x03,0x0E,0x0E,0x27,0x24,0x29,0x53,0xD3,0x0C,0x00,0x00,0x00,0x8B,0x49,0x44,0x41, 0x54,0x48,0xC7,0xED,0x55,0x41,0x0A,0xC0,0x20,0x0C,0x4B,0xA4,0xFF,0xFF,0x72,0x76, 0x28,0x88,0xE8,0xB6,0x6E,0x4E,0x07,0x63,0xF6,0x22,0x48,0x9B,0x96,0x90,0xA6,0x94, 0x84,0x22,0x48,0x62,0x44,0x54,0xB0,0x16,0x66,0x74,0x44,0x3B,0x6B,0xC2,0x2B,0xB1, 0xDA,0xFC,0xBE,0x8D,0x5D,0x51,0xA4,0x4B,0xBC,0x95,0x69,0xFE,0x0F,0x77,0xC0,0xC2, 0xFD,0x2A,0xD1,0x4B,0xB8,0x5B,0x8B,0x9C,0xBC,0x62,0x22,0x5F,0x24,0x00,0x03,0x09, 0xA9,0x9D,0xED,0xA1,0xEB,0x78,0xB9,0x00,0x07,0x37,0x7F,0x32,0x1D,0x47,0x14,0xF5, 0x7B,0x1A,0x09,0x29,0xF9,0xDF,0x6E,0xDE,0x18,0x1B,0x95,0x02,0x41,0x0F,0xEB,0x74, 0xA2,0xB4,0xB2,0x53,0xC8,0x5E,0x48,0x35,0xDB,0x7B,0x33,0xE4,0x10,0x54,0x20,0xCB, 0xD3,0x3E,0x65,0x9D,0x9C,0xE0,0x3D,0x1B,0xDB,0xDF,0x46,0x35,0xBF,0x76,0x6A,0x2A, 0x00,0x00,0x00,0x00,0x49,0x45,0x4E,0x44,0xAE,0x42,0x60,0x82};// list of schematic symbolschar *symbolList[] = { "<Line -100 0 20 0 #000080 2 1>\n" "<Line 80 0 20 0 #000080 2 1>\n" "<Line 80 -20 0 40 #000080 2 1>\n" "<Line -80 -20 160 0 #000080 2 1>\n" "<Line -80 20 160 0 #000080 2 1>\n" "<Line -80 -20 0 40 #000080 2 1>\n" "<Text -70 -10 8 #000000 0 \"R=R0*(1+A*Vr+B*Vr*Vr)\">\n" "<.PortSym -100 0 1 0>\n" "<.PortSym 100 0 2 180>\n" "<.ID -50 24 RNL >\n"};// component definitionEXPORT tComponentInfo compInfo = { isNonLinear, // component type ('isNonLinear' or 'isLinear') "ResNL", // model identifier "VerilogAMS model of ResNL", // component description 2, // number of external nodes 0, // number of internal nodes 0, // number of inputs (system simulations only) 3, // number of parameters params, // pointer to list of parameters 0, // size of global variable buffer in bytes icon, // pointer to component icon (0 = unused) sizof(icon), // size of component icon -1, // index of parameter determining schematic symbol (-1 = unused) symbollist, // pointer to list of schematic symbols (tEvaluate)fillMatrix, // function calculating analog model (0 = no model exists) 0, // function calculating noise model (0 = noise free) 0, // function calculating system model (0 = no model exists) 0, // string with digital Verilog model (0 = no model exists) 0 // string with digital VHDL model (0 = no model exists)};

Insert: click onInsert file as C++ array

Copy and pastesymbolList

Modify

Project: Create Binary Library

Modify

Model bitmap

RNL.va.cpp template file

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MOT-ADMS: Current Position

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● ADMS was developed by Laurent Limaitre while he was at Motorola/Freescale.

● The package was registered in 26/06/2003 at, and the code published by, Sourceforge.net, under the GNU Library or Lesser General Public License version 2.0 (LGPLV2).However, under the terms of the LGPL license the copyright remains with Motorola/Freescale.The same applies to any extensions to ADMS which are derivatives of the original ADMS code. Motorola/Freescale by releasing ADMS for use under LGPL intended to encourage the adoption of Verilog-A and Verilog-ADMS, by the modelling community, for compact model development.

● All versions of the package up to, and including, ADMS 2.30 have been maintained by

Laurent Lemaitre. Laurent Lemaitre no longer maintains ADMS.

● The current copyright position has been checked by the Freescale legal department: ADMS remains open source under LPGL (confirmed by Steven Hamm and Colin McAndrew ofFreescale) with copyright held by Motorola/Freescale.

● In the future ADMS will be maintained by Ryan Fox (ngspice team?) via Upverter/ADMS[1] GitHub.

● Maintenance of the ADMS back end code generation xml scripts is the responsibility of each circuit simulator development team.

[1] Upverter/ADMS can be found at https:github.com/upverter/ADMS/com.

MOT-ADMS: Examples of current circuit simulators using the package for compact and behavioural model development

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Circuit Simulator License ADMS Available Notes Version From

1. Qucs* GPL 2.30 http://qucs.sourceforge.net/ DC, AC, TRAN, S-parameters, noise and HB.

2. QucsStudio* GPL 2.30 http://www.mydarc.de/dd6um/QucsStudio/qucsstudio.html DC, AC, TRAN, S-parameters,

noise and HB.

3. ngspice GPL[2] 2.20 http://ngspice.sourceforge.net/ DC, AC and TRAN only.

4. GNUCAP GPL 2.30? https://github.com/gserdyuk/models-mot-adms DC, AC and TRAN only.

5. SymicaDE* Commercial[3] 2.29 http://www.symica.com/products/symica-free-edition DC, AC, TRAN, noise, S-parameters and mixed mode AMS extensions .

[2] Upverter/ADMS is a development project for ngspice – includes bug fixes and additional Verilog-AMS features. [3] Symica Free addition: This package is intended for personal non-commercial use in education and scientific research: features SymSpice, circuits with up to 300 elements, single thread simulation, and Verilog-A interface (extended for Verilog- AMS mixed mode simulation).

* ADMS is embedded in these circuit simulators.

MOT-ADMS: Introduction to the basic Verilog-A subset available with ADMS

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The MOT-ADMS software is supplied with little documentation!The MOT-ADMS software is supplied with little documentation!These brief notes provide a basic introduction to the MOT-ADMS Verilog-A subsetThese brief notes provide a basic introduction to the MOT-ADMS Verilog-A subset

● Verilog-A is a case sensitive language● Comments: single line comments start with //,

block comments begin with /* and end with */● Identifiers are sequences of letters, digits, dollar signs '$' and the underscore '_';

the first letter of an identifier must not be a digit● MOT-ADMS version 2.30 keywords: parameter, aliasparameter, aliasparam,

module, endmodule, function, endfunction, discipline, potential, flow, domain,ground, enddiscipline, nature, endnature, input, output, inout, branch, analog,begin, end, if, while, case, endcase, default, for, else, integer,real, string, from,exclude, inf, INF

● Compiler directives: `define,`undef, `ifdef, `else, `endif, `include● Data types: integers, reals and strings● Predefined constants in “constants.vams”: `M_PI, `M_TWO_PI, `M_PI_2, `M_PI_4,

`M_1_PI, `M_2_PI, `M_2_SQRTPI, `M_E, `M_LOG2E, `M_LOG10E, `M_LN2, `M_LN10, `M_SQRT2, `M_SQRT1_2, `P_Q, `P_C, `P_K, `P_H,`P_EPS0, `P_U0,`P_CELSIUS0

● Variables are named objects that contain a value of a particular type. They are initialised to zero or unknown. They retain their value until changed by an assignmentstatement.

MOT-ADMS: Introduction to the basic Verilog-A subset available with ADMS; continued

● Parameters are declared using statements of the form: parameter integer size=16; parameter real period = 1.0 from (0:inf);parameter integer dir = 1 from [-1:1] exclude 0;

● Verilog-A natures and disciplines ae listed in file “disciplines.vams”● Port, net and node examples in Verilog-A:

module amp(out1, in1); input in1; output out1; electrical out1, in1;

● Branches declared with statement branch (n1,n2) b1;● Signal access function examples: V(n2), I(n), V(b1), I(b1), V(n,m), I(n,m)● Current contribution examples:

I(diode) <+ Is*(limexp(V(diode)/$vt)-1); I(diode) <+ ddt(-2*cj0*phi*sqrt(1-V(diode)/phi));

● MOT-ADMS allows an extensive range of Verilog-AMS operators andmathematical functions

● Environmental Functions: $temperature, $vt, $strobe, $finish, $given,$parameter_given

● Analogue operators: @(initial_step), @(final_step), @(initial_model),@(initial_instance)

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MOT-ADMS: Introduction to the basic Verilog-A subset available with ADMS; continued

15

● Analogue behavioural statements:1. Analog process/procedural block; analog begin I(diode) <+ Is*(limexp(V(diode)/$vt)-1);

qd = tf*I(diode) -2*cj0*phi*sqrt(1-V(diode)/phi); I(diode) <+ ddt(qd); end 2. Assignment statements consist of a variable followed by = and an expression 3. Conditional operator cond ? Val1 : Val2, for example State = (V(d) > 0.0) ? 1 : -1; 4. if-else statement: If (V(ps,ns) > thresh) I(p,n) <+ 1; else I(p,n) <+ 0; 5. Case statement: case (select) 0 : out = I(in0); 1 : out = I(in1); 2 : out = I(in2); default : out = 0; endcase

TRUE = non-zero value

6. While statement: test = 4; While( test) begin A = A+1; B = B-1; test = test-1; end

7. For loops: for (i=0; I <10; i=i+1) begin .. .. end

8. User defined functions and function calls.

MOT-ADMS: Example QucsStudio Verilog-A model code template

16

// A QucsStudio Verilog-A simple BJT mode;`include "disciplines.vams"`include "constants.vams"// Module name becomes name of the model file names.module Transistor (externalBase, Collector, Emitter); inout externalBase, Collector, Emitter; electrical externalBase, Collector, Emitter; electrical Base;`define attr(txt) (*txt*)`define GMIN 1e-10parameter real Bf=100 from [1:inf] `attr(info="forward current gain" unit="1");parameter real Rbase=1 from [0:inf] `attr(info="base resistance" unit="ohms");parameter real Is=1e-16 from [0:inf] `attr(info="saturation current" unit="A");parameter real Vearly=100 from [0:inf] `attr(info="early voltage" unit="V");parameter real Cj0=0 from [0:inf] `attr(info="zero-bias depletion capacitance" unit="F");parameter real Vj0=0.75 from [0:inf] `attr(info="junction built-in potential" unit="V");parameter real Fc=0.5 from [0:inf] `attr(info="depletion capacitance coefficient" unit="1");parameter real Mj=0.33 from [0:inf] `attr(info="junction exponential factor" unit="1");parameter real Temp=26.85 from [-273.15:inf] `attr(info="simulation temperature" unit="Celsius");parameter real Kf=1e-9 from [0:inf] `attr(info="flicker noise coefficient" unit="1");parameter real Af=0 from [0:inf] `attr(info="flicker noise current exponent" unit="1");parameter real Ffe=1.0 from [0:inf] `attr(info="flicker noise frequency exponent" unit="1");parameter string Type="npn" `attr(info="transistor type [npn, pnp]");real Tj, Vtemp, Vbe, Vbc, Vce, Ibe, Ibc, Ice, Qbe;// Model branchesbranch (Base, Emitter) be; branch (Base, Collector) bc; branch (Collector, Emitter) ce;branch (Base, externalBase) rb;analog begin// equations that are constant during simulation@(initial_step)begin Tj = Temp + `P_CELSIUS0; Vtemp = `P_K * Tj / `P_Q;// If the parameter "Temp" exists the following expressions can be used.// Otherwise they refer to 300K.// Tj = $temperature; // temperature in Kelvin// Vtemp = $vt; // temperature voltage if(Is > 0.1) $warning("Saturation current unusually high: %g", Is); if(Vearly < 0.0001) begin $error("Early voltage is negative: %g", Vearly); $finish; endend;

// voltagesVbe = V(be); Vbc = V(bc); Vce = V(Collector, Emitter);if(Type == "pnp") // pnp transistor?begin Vbe = -Vbe; Vbc = -Vbc; Vce = -Vce;end// current and charge equationsIbe = Is * (limexp(Vbe/Vtemp) - 1.0) + `GMIN*Vbe;Ibc = Is * (limexp(Vbc/Vtemp) - 1.0) + `GMIN*Vbc;Ice = Bf * (Ibe-Ibc) * (1.0 + Vce/Vearly);if(Vbe < (Fc*Vj0)) Qbe = Cj0 * pow(1 - Vbe/Vj0, 1-Mj);else Qbe = Cj0 / pow(1 - Fc, Mj) * (1 + Mj*(Vbe - Fc*Vj0) / Vj0 / (1-Fc));if(Type != "npn") // not npn transistor?begin Ibe = -Ibe; Ibc = -Ibc; Ice = -Ice;end// linear resistance`ifdef insideQucsStudioR(rb) <+ Rbase;`elseI(rb) <+ V(rb) / Rbase;`endif// current and charge contributionsI(be) <+ Ibe; I(bc) <+ Ibc;I(ce) <+ Ice; I(be) <+ ddt(Qbe);// noise contributionsI(be) <+ white_noise(2.0*`P_Q*Ibe, "shot");I(ce) <+ flicker_noise(Kf*pow(Ice, Af), Ffe, "flicker");// noise of linear conductanceG(rb) <+ white_noise(4.0*`P_K*Tj/Rbase, "thermal");endendmodule

MOT-ADMS: Special features and problems

● Although Verilog-A is standardised, published versions of MOT-ADMS implement differentsubsets of verilog-A: more divergence will result from any new additions to ADMS 2.30 unlessthey are adopted universally.

● Simulator interface facilities may vary: for example $strobe is replaced/added to by $error and$warning in QucsStudio.

● The inclusion mechanism for Verilog-A predefined constants, natures and discipines files can change from simulator to simulator: for example use of `include constants.h and `include disciplines.h by SymicaDE.

● Parameter statement descriptive elements vary significantly amoung circuit simulatorimplementations: for example Qucs and QucsStudio use `attr(info = “description”), or`attr(desc=”description”) and unit=”value” other simulators use`P(........).

● Verilog-A compact modelling extensions: special features tailored to compact device modellinghave been added to the MOT-ADMS 2.30 software, including desc, unit, $parameter_given, $given, aliasparameter and string type in parameters. In addition the function ddx is nowadopted in the language standard, where ddx takes a variable and a node potential ( for example gm = ddx(Ids,V(g));) and returns the symbolic partial derivative of the variable withrespect to the node potential, holding all other potentials constant. Qucs and QucsStudioimplement these extensions but other circuit simulators may not.

● Each circuit simulator uses one or more back end xml files for C++ code generation and modelinterfacing to the main body of C++ code: as these xml scripts are specific to each simulator API there are likely to be differences in the C++ model generated. One example being electricalnoise: Verilog-A statements white_noise(pwr, <name>), flicker_noise(pwr, <exp>,<name>) are implemented in Qucs and QucsStudio but not, for example, in ngspice. Hence, do model results vary and how are they to be checked with certainty? Also to meet the needs ofindividual simulator APIs, additions to the natures and disciplines implemented by Verilog-Amay be needed: see for example the implimentation of a linear resistance in QucsStudio (slide 14).

● In addition to the above how are the results from new types of circuit simulation, like Harmonic Balance, and compact device models to be checked?

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Qucs/QucsStudio: Recent compact model developments Pin diode model

// Verilog-A RF PIN diode block called PINDiodeB1.va// This is free software; you can redistribute it and/or modify// it under the terms of the GNU General Public License as published by// the Free Software Foundation; either version 2, or (at your option)// any later version.// // Copyright (C), Mike Brinson, mbrin72043@yahoo.co.uk // QucsStudio version July 2012.//`include "disciplines.vams"`include "constants.vams" `define attr(txt) (*txt*)module PINDiodeB1(AI, CI); inout AI, CI ;electrical AI, CI, n1,n2;//parameter real Rmin = 0.716 from [1e-20 : inf) `attr(info="Minimum n region resistance" unit = "Ohm" );parameter real Rmax = 1212 from [1e-20 : inf) `attr(info="Maximum n region resistance" unit = "Ohm" );parameter real A = 0.01257 from [1e-20 : inf) `attr(info="Non-linear resistance A coeficient");parameter real K = 0.9947 from [1e-20 : inf) `attr(info="Non-linear resistance K coeficient");// Model branchesbranch (AI, n1) bAIn1;branch (n1, CI) bn1CI;branch (AI, CI) bAICI;analog begin // Current contribution etc`ifdef insideQucsStudio R(bAIn1) <+ Rmin; R(bn1CI) <+ Rmax; R(n2) <+ 1; C(n2) <+ 1; `else I(bAIn1) <+ V(bAIn1)/Rmin; I(bn1CI) <+ V(bn1CI)/Rmax; I(n2) <+ ddt(V(n2)); I(n2) <+ V(n2); `endif I(n2) <+ -V(bAIn1)/Rmin; if (V(n2) >= 0.0) begin I(bn1CI) <+ V(bn1CI)*pow(V(n2), K)/A; end else begin I(bn1CI) <+ V(bn1CI)/1e7; endendendmodule

Harmonic Balance Diode model

Qucs/QucsStudio: Recent compact model developments Pin diode model continued

// Diode model for Harmonic Balance simulation -- DiodeHB.va.`include "disciplines.vams"`include "constants.vams"module DiodeHB (Anode, Cathode);inout Anode, Cathode;electrical Anode, Cathode, AI;`define attr(txt) (*txt*)`define GMIN 1e-12parameter real N = 1.0 from [0:inf);parameter real Is = 1e-14 from [1e-30 : inf);parameter real Rs = 0.1 from [1e-3 : inf);parameter real Tnom = 26.85 from [-100 : inf);parameter real Temp = 26.85 from [-100 : inf);parameter real Vj = 1.0 from [0.0 : inf);parameter real M = 0.5 from [1e-2 : inf);parameter real Fc = 0.5 from [1e-2 : inf);parameter real Cj0 = 1e-12 from [1e-20 : inf);parameter real Tt = 1e-10 from [1e-20 : inf);//branch (Anode, AI) BAnodeAI;branch (AI, Cathode) BAICathode; //real T1, T2, VTH, Del, ID1, ID2, ID3;real F1,F2,F3,F4, Qdep1, Qdep2, Id, Qdiff, M1, M2, Fc1, Vn1;analog begin@(initial_model)begin M1 = 1-M; M2 = 1+M; Fc1 = ln(1-Fc); T1 = Tnom + 273.15; T2 = Temp + 273.15; VTH = 18; Del = `P_Q/(N*`P_K*T2); F1 = (Vj/M1)*(1.0-exp(M1*Fc1)); //(1.0-pow(1-Fc,1-M)); F2 = exp(M2*Fc1);// pow(1-Fc,1.0+M); F3 = 1-Fc*M2; F4 = Fc*Vj*(Fc*(1+0.5*M)-1.0);end// Current contributionsVn1 = V(BAICathode);if (Vn1 > VTH) begin Id = Is*exp(Del*VTH)*(1+Del*(Vn1-VTH)+Del*(Vn1-VTH)*(Vn1-VTH)/2); I(BAICathode) <+ Id;endif ( ( Vn1 <= VTH) && (Vn1 > -35/Del) ) begin Id = Is*(exp(Del*Vn1)-1.0); I(BAICathode) <+ Id;endif ( Vn1 <= -35/Del ) begin I(BAICathode) <+ -Is; end if (Vn1 < Fc*Vj) begin Qdep1 =-(Cj0*Vj/M1)*exp(M1*ln(1-Vn1/Vj)); I(BAICathode) <+ ddt(Qdep1);endif ( Vn1 >= Fc*Vj)begin Qdep2 = Cj0*F1+Cj0*(F3*Vn1+0.5*M*Vn1*Vn1/Vj+ F4)/F2; I(BAICathode) <+ ddt(Qdep2); I(BAICathode) <+ ddt(Tt*Id);endR(BAnodeAI) <+ Rs;endendmodule

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Qucs/QucsStudio: RF components – Inductance

// Verilog-A RF Inductance block Rp||Cp called RpPARACp.va// This is free software; you can redistribute it and/or modify// it under the terms of the GNU General Public License as published by// the Free Software Foundation; either version 2, or (at your option)// any later version.// // Copyright (C), Mike Brinson, mbrin72043@yahoo.co.uk // QucsStudio version July 2012.//`include "disciplines.vams"`include "constants.vams" `define attr(txt) (*txt*)module RpPARACp(A, B); inout A, B ;electrical A,B;//parameter real L0 = 1e-3 from [1e-20 : inf) `attr(info="Low frequency inductance value" unit = "H" );parameter real F0 = 800e3 from [1e-7 : inf) `attr(info="Self resonant frequency" unit = "Hz");parameter real Q = 50 from [1 : inf) `attr(info="Quality factor");// Variablesreal PIx2xF0, Cp, Rp;// Model branchesbranch (A, B) bAB; analog begin@(initial_step)begin PIx2xF0 =`M_TWO_PI*F0; Cp = 1/(PIx2xF0*PIx2xF0*L0); Rp = Q*PIx2xF0*L0; if (Rp >= 1e9) begin Rp = 1e9; end end// Current contribution etc`ifdef insideQucsStudio R(bAB) <+ Rp; C(bAB) <+ Cp; `else I(bAB) <+ 1.0/Rp; I(bAB) <+ ddt(Cp*V(bAB)); `endifendendmodule

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Qucs/QucsStudio: RF components – Inductance

21

Qucs/QucsStudio: MOS models – BSIM 3.24

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QucsStudio: Communication system simulation

23

QucsStudio example by Michael Margraf

24

Qucs/QucsStudio: Sampled data system simulation

A switched capacitor inverting integrator example

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QucsStudio: System manufacturing printed circuit boards

QucsStudio example by Michael Margraf

PCB layout by KiCAD

Simulation

Qucs/QucsStudio: Future Developments

Current Work1. Development of QucsStudio: Michael Margraf (Germany) + Mike Brinson (UK).2. Port of Qucs from Qt3 to Qt4: Frans Schreuder (Holland), Richard Crozier (UK) + others.3. Model development for QucsStudio/Qucs: Mike Brinson (UK) + others.4. Extend Qucs Verilog-A capabilities : Mike Brinson (UK).5. Development of low cost measurement system linked to QucsStudio/Qucs: Mike Brinson (UK).6. Bug patches from Qucs users.

Future WorkFuture Work1. Qucs/QucsStudio Semiconductor device parameter extraction system: Mike Brinson (UK), Wladek Grabinski(Switzerland) and Daniel Tomaszewski (Poland).2. Continuous system simulation → Modelica like block diagrams: Mike Brinson (UK).3. Non-linear differential equation blocks for electrical machine simulation: Richard Crozier (UK).4. Analogue/Digital mixed mode simulation (cosimulation): Chuck ? (USA)

Long Term Tasks1. Improve post-simulation data analysis facilities.2. Improve Qucs Harmonic Balance Simulation.3. Remove bugs from Qt4 version of Qucs.4. Add more sampled data features.5. Add pcb link to Qucs.6. Improve RF transient simulation models.

+ Many more possibilities – depending on time. 26

Summary

1. Qucs and QucsStudio are freely available circuit simulators distributed as open source software under the GNU General Public Licence (GPL).

2. This presentation has attempted to outline the history and the fundamental features of the packages, the available equation-defined components, built in modelling aids, analysis types and post-simulation data analysis and visualisation capabilities.

3. A series of slides reviewed the current position of the ADMS Verilog-A model synthesiser, describing its implementation in the current QucsStudio/Qucs releases. The talk also introduced how ADMS can be used to develop equation-defined component models of established and emerging technology devices.

5. An outline of a number of proposed future developments was presented at the end of these slides.

Qucs and QucsStudio are freely available under the open source General Public Licence.Download from: Qucs version 0.0.16 (Qt3)/0.0.17 (Qt4) http://qucs.sourceforge.net QucsStudio version 1.4.4 http://mydarc.de/DD6UM/QucsStudio/qucsstudio.html

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