ADVANCED WIDE VOLTAGE - Kazenice.kaze.com/av/MC13028.pdfDevice Operating Temperature Range Package...

DeviceOperating

Temperature Range Package

ORDERING INFORMATION

MC13028ADTA = –25° to +70°C

SO–16

��

SEMICONDUCTORTECHNICAL DATA

C–QUAM AM STEREOADVANCED WIDE VOLTAGE

IF and DECODER for E.T.R. RADIOS

Order this document by MC13028A/D

D SUFFIXPLASTIC PACKAGE

CASE 751B(SO–16)

116

P SUFFIXPLASTIC PACKAGE

CASE 648

16

15

14

13

12

11

10

1

2

3

4

5

6

7

8 9

StereoThreshold Adjust

AGC BypassFilter

IF FeedbackBypass

IF Signal Input

Gnd

StereoIndicator Drive

1.0 V Reference

Blend

Right ChannelOutputLeft ChannelOutput

Loop Filter

VCO Output

VCC

Pilot SignalInputPilot Q DetectorOutputPilot I DetectorOutput

1

16

PIN CONNECTIONS

MC13028AP DIP–16

1MOTOROLA ANALOG IC DEVICE DATA

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The MC13028A is a third generation C–QUAM stereo decoder targetedfor use in low voltage, low cost AM/FM E.T.R. radio applications. Advancedfeatures include a signal quality detector that analyzes signal strength,signal to noise ratio, and stereo pilot tone before switching to the stereomode. A “blend function” much like FM stereo has been added to improvethe transition from mono to stereo. The audio output level is adjustable toallow easy interface with a variety of AM/FM tuner chips. The externalcomponents have been minimized to keep the total system cost low.

• Adjustable Audio Output Level• Stereo Blend Function• Stereo Threshold Adjustment• Operation from 2.2 V to 12 V Supply• Precision Pilot Tone Detector• Forced Mono Function• Single Pinout VCO• IF Amplifier with IF AGC Circuit• VCO Shutdown Mode at Weak Signal Condition

The purchase of the Motorola C–QUAM AM Stereo Decoder does not carry with such pur-chase any license by implication, estoppel or otherwise, under any patent rights of Motorolaor others covering any combination of this decoder with other elements including use in aradio receiver. Upon application by an interested party, licenses are available from Motorolaon its patents applicable to AM Stereo radio receivers.

Representative Block Diagram

This device contains 679 active transistors.

87654321

910111213141516

Reg

AGC Signal QualityDetector

Pilot ToneDetector

� 8VCO

AM StereoDecoder

IFAmp

Motorola, Inc. 1996 Rev 2

MC13028A

2 MOTOROLA ANALOG IC DEVICE DATA

MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)

Rating Symbol Value Unit

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Power Supply Input Voltage ÁÁÁÁÁÁÁÁ

VCCÁÁÁÁÁÁÁÁ

14 ÁÁÁÁÁÁ

Vdc

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Operating Junction Temperature ÁÁÁÁÁÁÁÁ

TJÁÁÁÁÁÁÁÁ

150 ÁÁÁÁÁÁ

°CÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Operating Ambient Temperature ÁÁÁÁÁÁÁÁ

TAÁÁÁÁÁÁÁÁ

–25 to +70ÁÁÁÁÁÁ


Storage Temperature Range ÁÁÁÁÁÁÁÁ

TstgÁÁÁÁÁÁÁÁ

–55 to +150ÁÁÁÁÁÁ


LED Indicator Current ÁÁÁÁÁÁÁÁ

ILEDÁÁÁÁÁÁÁÁ

10 ÁÁÁÁÁÁ

mA

ELECTRICAL CHARACTERISTICS (VCC = 8.0 Vdc, TA = 25°C, Input Signal Level = 74 dBµV, Modulation = 1.0 kHz@ 50% Modulation, unless otherwise noted.)

Characteristic Symbol Min Typ Max Unit

Supply Current Drain ICC mAVCC = 2.2 V

CC– 9.0 11

VCC = 8.0 V – 11 –

Audio Output Level, L+R, Mono Modulation Vout mVrmsRO = 1.8 k, VCC = 2.2 V, Input 55 dBµV 22 33 44RO = 10 k, VCC = 8.0 V, Input 50 dBµV 150 200 250RO = 10 k, VCC = 8.0 V, Input 40 dBµV 80 130 180RO = 10 k, VCC = 8.0 V, Input 31 dBµV – 50 –

Audio Output Level, L or R Only, Stereo Modulation Vout mVrmsRO = 1.8 k, VCC = 2.2 V, 55 dBµV Input 35 80 106RO = 10 k, VCC = 8.0 V 340 460 580

Output THD %50% Stereo, L or R Only THD1 – 0.6 1.850% Mono, L+R THD2 – 0.3 0.690% Mono, L+R, Input 86 dBµV THD3 – – 1.5

Channel Separation L or R 23 35 – dB50% L or R Only

Decoder Input Sensitivity Vin – 33 – dBµVVout = –10 dB

Force to Mono Mode, (Pin 10) – 0.25 0.3 – Vdc

Stereo Threshold Adjust (Pin 1) STA dBµVPin 1 Open

TA– 50 55

µ

R1 = 15 k (Gnd) – 55 –R1 = 680 k (VCC) – 48 –

Signal to Noise Ratio, RO = 10 k S/N dB50% Stereo, L or R Only 40 62 –50% Mono, L+R 40 59 –

Input Impedance Rin – 10 – kΩ(Reference Specification) Cin – 8.0 – pF

Maximum Input Signal Level for THD ≤ 1.5% – – – 86 dBµV

Blend Voltage BI VdcMono Mode 0.7 – 0.9Stereo Mode 1.20 1.30 1.35Out of Lock – 0.12 0.2

VCO Lock Range OSCtun – ±2.5 – kHz

AGC Range AGCrng – 44 – dB

Channel Balance C–B –1.0 – 1.0 dB

Pilot Sensitivity – – 2.5 4.0 %

MC13028A


Standard Test Circuit

IFAmp

Pilot Tone Detector

Reg

Signal Quality Detector

AM StereoDecoder

AGC

Left

Right

LAudio Output

R10 k

2.2 k

Loop3.6 MHz

VCC

2.2 k

9

10

11

12

13

14

15

16

4

3

2

1

+10 µF

Blend

LED

Pilot Ind

Gnd

0.01 µF

IFin

0.47 µF

10 µF

R1VCC

10 µF 10 µF

0.47 µF

0.22 µF

47 µF

2.2 k

10 k

47 µF47

43 pF

VCO

�8

+8

7

6

5

+

+

+

+

+

RORO

++

PIN FUNCTION DESCRIPTION

ÁÁÁÁÁÁÁÁ

Pin ÁÁÁÁÁÁÁÁÁÁ

Symbol ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Internal Equivalent Circuit ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Description/External Circuit Requirements

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

STA ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

VCC

12.4 k

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Stereo Threshold Adjustment PinThe function of this circuit is to provide the freedomto achieve a desired value of incoming IF signal levelwhich will cause full stereo operation of the decoder.The level can be determined by the value of R1, aresistor from Pin 1 that can be connected to eitherVCC or to ground. This resistor may also be omittedin some designs (Pin 1 left open). The approximatedc level with the pin left open is 0.6 Vdc.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

2 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

AGCcap ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

2ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

AGC Filter Bypass CapacitorAn electrolytic capacitor is used as a bypass filterand it sets the time constant for the AGC circuitaction. The recommended capacitor value is 10 µFfrom Pin 2 to ground. The dc level at this pin variesas shown in the curve in Figure 13, AGC Voltageversus Input Level.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

3ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

IFFBcap

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

VCC

3

2.0 k

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

IF Amplifier Feedback CapacitorA capacitor which is specified to have a low ESRat 450 kHz is normally used at Pin 3. The valuerecommended for this capacitor is 0.47 µF fromPin 3 to ground. This component forms a low passfilter which has a corner frequency around 30 kHz.

MC13028A


PIN FUNCTION DESCRIPTION

ÁÁÁÁÁÁÁÁ

Pin ÁÁÁÁÁÁÁÁÁÁ

Symbol ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Internal Equivalent Circuit ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Description/External Circuit Requirements



IFin ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

10 k

4

Vref

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

IF Amplifier InputPin 4 is the IF input pin. The typical input impedanceat this pin is 10 k. The input should be ac coupledthrough a 0.01 µF capacitor.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

5 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Gnd ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Gnd5

Substrate

Circuit

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Supply GroundIn the PCB layout, the ground pin should beconnected to the chassis ground directly. This pinis the internal circuit ground and the siliconsubstrate ground.


6 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

SIND ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

VCC

30 k

6


Stereo Indicator DriverThis driver circuit is intended to light an LED orother indicator when the decoder receives theproper input signals and switches into the stereomode. The maximum amount of current that thecircuit can sink is 10 mA.

A current limiting resistor is applied externally tocontrol LED brightness versus total power supplycurrent.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

7 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

VRef ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

7Reference

Voltage1.0 V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Regulated Voltage, 1.0 VAn electrolytic capacitor used as a bypass filter isrecommended from Pin 7 to ground. The capacitorvalue should be 10 µF.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

8ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CAPBlendÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

8

Blend CapCharging

Circuit

Pilot IndicatorDriver Circuit

BlendAlgorithm

Circuit

VCC

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Blend CapacitorThe value of the capacitor on this pin will effect thetime constant of the decoder blend function. Therecommended value is 10 µF from Pin 8 to ground.The dc level at Pin 8 is internally generated inresponse to input signal level and signal quality. Thispin is a key indicator of the operational state of the IC(see text Functional Description). It is recommendedto discharge the blend capacitor externally whenchanging stations.



IPilot ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Vreg

9

43 k

VCCÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Pilot I Detector OutputThe Pilot I Detector output requires a 10 µFelectrolytic capacitor to ground. The value of thiscapacitor sets the pilot acquisition time. The dclevel at Pin 9 is approximately 1.0 Vdc, unlocked,and 1.1 to 2.4 Vdc in the locked condition.

MC13028A


PIN FUNCTION DESCRIPTIONÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Description/External Circuit RequirementsÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Internal Equivalent CircuitÁÁÁÁÁÁÁÁÁÁ

SymbolÁÁÁÁÁÁÁÁ

PinÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

10ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

QPilotÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

10

5.0 k

VCC


Pilot Q Detector OutputThis pin is connected to the Pilot Q detector andrequires a 0.47 µF capacitor to ground to filter theerror line voltage at the PLL pilot tone detector. If thevalue of this capacitor is made too large, thedecoder may be prevented from coming back intostereo after a signal drop out has been experiencedin the field. The force to mono function is alsoaccomplished at this pin by pulling the dc voltagelevel at the pin below 1.0 V.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

11ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

PILOTfilÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

VCC

2.0 k

11

VCC

30 k

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Pilot Signal InputA capacitor to ground forms a filter for the pilot inputsignal. The recommended value of the capacitor is0.22 µF. The dc level at Pin 11 is approximately1.0 Vdc.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

12 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

VCC ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

12

VCC

VCC

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Supply Voltage (V CC)The operating supply voltage range is from 1.8 Vdcto 12 Vdc.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

13 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

OSCin ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Vreg

15 k

3.0 k

13Vreg

3.1 k

6.3 pF

2.2 k

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Oscillator InputThe oscillator pin requires a ceramic resonator andparallel capacitor connected to ground. Therecommended source for the ceramic resonator isMurata, part number CSA 3.60MGF108.A 43 pF NPO capacitor is in parallel with theresonator. The dc level at Pin 13 is approximately1.1 Vdc.

MC13028A


PIN FUNCTION DESCRIPTIONÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Description/External Circuit RequirementsÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Internal Equivalent CircuitÁÁÁÁÁÁÁÁÁÁ

SymbolÁÁÁÁÁÁÁÁ

PinÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

14ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

LOOPFilterÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

10 k

VCC

390

FastLockLow

VCC

14

VCC

FastLockHighIdrive

Idrive

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Loop FilterA capacitor which forms the loop filter is connectedfrom Pin 14 to ground. The recommended value is47 µF in series with 47 Ω. This capacitor should be ofgood construction quality so it will have a very lowspecification for leakage current in order to preventstereo distortion. The 47 Ω resistor in series with thecapacitor controls the PLL corner frequencyresponse, keeping the response shape criticallydamped and not peaked up. The dc level at Pin 14 isapproximately 0.6 Vdc in the locked condition.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

15 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

LEFTout ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

VCC

15

VCC

1.0 k

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Left Channel Audio OutputThis is the left channel audio output pin from whichthe IC can provide 1.3 µApp drive current for eachpercent of mono modulation. A resistor to groundsets the level of the audio output.

For example, 100% (mono mod) x 1.3 µApp (ICdrive per % mod) = 130 µApp flowing through theload resistor. (For a 2.2 k load, 286 mVpp is thenthe output signal voltage.) When dealing withstereo signals, multiply the mod level by 2; i.e. 50%(left only mod) x 2 (stereo factor) x 1.3 µApp (ICdrive per % mod) = 130 µApp flowing through theload resistor.


16ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RIGHToutÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

VCC

16

VCC

1.0 k


Right Channel Audio OutputThis is the right channel audio output pin. A resistorto ground sets the level of the audio output. See theexplanation under the Left Channel Audio Outputdescription above.

MC13028A


IFInput

Figure 1. Typical Circuit for E.T.R. Applications

NOTES: 1. The 47 µF capacitor is recommended to be a low leakage type capacitor. Leakage current due to this capacitor causes increase in stereo distortion and decreased separation performance.

2. The recommended source for this part is Murata Products. CSA3.60MGF108. The location of this part should be carefully considered during the layout of the decoder circuit. This part should not be near the audio signal paths, the 25 Hz pilot filter lines, or the VCC high current lines, and the ceramic element ground line should be direct to the chassis ground lead in order to avoid any oscillator inter–modulation.

3. The 43 pF capacitor is recommended to be a NPO type ceramic part. Changing the value of this capacitor alters the lock range of the decoder PLL.

4. The tolerance on the value of the 0.22 µF capacitor should be within ± 20% for the full design temperature range of operation. Any reduction in the value of this capacitor due to temperature excursions will reduce the pilot tone circuit sensitivity.

5. The 0.47 µF capacitor is recommended to be a low ESR type capacitor, (less than 1.5 Ω) in order to avoid increased audio output distortions under weak input signal conditions with higher modulation levels.

6. The scan/mute function is located on the Blend pin at Pin 8. To provide this function, Pin 8 should be pulled down below 0.3 V until the decoder and the synthesizer have both locked to a new station.

RF AGC’d IF Signal from Mixer (450 kHz from

Tuner IC Section)

10 µF 0.01 µFR1

StereoThreshold Adjust

AGCBypass

IFBypass

Gnd Stereo Indicator

(Note 6)

Blend

ScanMute

Reg

Signal Quality Detector

AGC

IF Amp

AM Stereo Decoder

VCO �8

Pilot Tone Detector

Optional Force to Mono

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

Pilot IInput

Pilot QInput

PilotInput

10 µF0.47 µF

(Note 4)

0.22 µF

VCC

43 pF(Note 3)

(Note 2)

4747 µF

(Note 1)

RO

Left Output

Right Output

NRSC Roll–Off Filter

RO

0.47 µF(Note 5)

10 µF

Ref

10 µF

+ + + +

+ ++

47 µF+

MC13028A


FUNCTIONAL DESCRIPTION

IntroductionThe MC13028A is designed as a low voltage, low cost

decoder for the C–QUAM AM Stereo technology and iscompletely compatible with existing monaural AMtransmissions. The IC requires relatively few, inexpensiveexternal parts to produce a full featured C–QUAM AM Stereoimplementation. The layout is straightforward and shouldproduce excellent stereo performance. This device performsthe function of IF amplification, AGC, modulation detection,pilot tone detection, signal quality inspection, and left andright audio output matrix operation. The IC is targeted for usein portable and home AM Stereo radio applications.

A simple overview follows which traces the path of theinput signal information to the MC13028A all the way to theaudio output pins of the decoder IC.

From the appropriate pin of an AM IC, the IF amplifiercircuit of the MC13028A receives its input at Pin 4 as a450 kHz, typically modulated C–QUAM signal. The inputsignal level for stereo operation can vary from 47 dBµV toabout 90 dBµV. A specific threshold level between theselimits can be designed into a receiver by the choice of theresistor value for R1 connected to Pin 1. This IC designincorporates feedback in the IF circuit section which providesexcellent dc balance in the IF amplifier. This balancedcondit ion also guarantees excel lent monophonicperformance from the decoder. An IF feedback filter at Pin 3is formed by a 0.47 µF low leakage capacitor. It is used tofilter out the unwanted audio which is present on the IFamplifier feedback line at higher modulation levels underweak input RF signal conditions. Elimination of the unwantedsignal helps to decrease the amount of distortion in the audiooutput of the stereo decoder under these particular inputconditions. An AGC circuit controls the level of IF signalwhich is subsequently fed to the detector circuits. An AGCbypass capacitor is connected to Pin 2 and forms a singlepole low pass filter. The value of this part also sets the timeconstant for the AGC circuit action.

The amplified C–QUAM IF signal is fed simultaneously tothe envelope detector circuit, and to a C–QUAM convertercircuit. The envelope detector provides the L+R (mono)signal output which is fed to the stereo matrix. In theconverter circuit, the C–QUAM signal is restored to a Quamsignal. This is accomplished by dividing the C–QUAM IFsignal by the demodulated cos φ term. The cos φ term isderived from the phase modulated IF signal in an activefeedback loop. Cosine φ is detected by comparing theenvelope detector and the in–phase detector outputs in thehigh speed comparator/feedback loop. Cosine φ is extractedfrom the I detector output and is actively transferred throughfeedback to the output of the comparator. The output of thecomparator is in turn fed to the control input of the divider,thus closing the feedback loop of the converter circuit. In thisprocess, the cos φ term is removed from the divider IF output,thus allowing direct detection of the L–R by the quadraturedetector. The audio outputs from both the envelope and theL–R detectors are first filtered to minimize the secondharmonic of the IF signal. Then they are fed into a matrix

circuit where the Left channel and the Right channel outputscan be extracted at Pins 15 and 16. (The outputs from the Iand Q detectors are also filtered similarly.) At this time, astereo indicator driver circuit, which can sink up to 10 mA, isalso enabled. The stereo output will occur if the input IFsignal is: larger than the stereo threshold level, not too noisy,and if a proper pilot tone is present. If these three conditionsare not met, the blend circuit will begin to force monauraloperation at that time.

A blend circuit is included in this design becauseconditions occur during field use that can cause input signalstrength fluctuation, strong unwanted co–channel or powerline interference, and/or multi–path or re–radiation. Whenthese aberrant conditions occur, rapid switching betweenstereo and mono might occur, or the stereo quality might bedegraded enough to sound displeasing. Since theseconditions could be annoying to the normal listener, thestereo information is blended towards a monaural output.This circuit action creates a condition for listening wherethese aberrant effects are better tolerated by the consumer.

Intentional mono operation is a feature sometimesrequired in receiver designs. There are several ways in whichto accomplish this feat. First, a resistor from Pin 10 to groundcan be switched into the circuit. A value of 1.0 k is adequateas is shown in the schematic in Figure 18. A second methodto force the decoder into mono is simply to shunt Pin 10 toground through an NPN transistor (collector to Pin 10, emitterto ground), where the base lead is held electrically “high” toinitiate the action.

A third method to force a mono condition upon thedecoder is to shunt Pin 8 of the decoder to ground throughan NPN transistor as described above. Effectively, thisoperation discharges the blend capacitor (10 µF), and theblend function takes over internally forcing the decoder intomono. This third method does not necessarily require extraspecific parts for the forced mono function as the first twoexamples do. The reason for this is that most electronicallytuned receiver designs require an audio muting functionduring turn on/turn off, tuning/scanning, or band switching(FM to AM). When the muting function is designed into anAM Stereo receiver, it also should include a blend capacitorreset (discharge) function which is accomplished in this caseby the use of an NPN transistor shunting Pin 8 to ground,(thus making the addition of a forced mono function almost“free”). The purpose of the blend reset during muting is tore–initialize the decoder back into the “fast lock” mode fromwhich stereo operation can be attained much quicker afterany of the interruptive activities mentioned earlier, (i.e. turnon, tuning, etc.).

The VCO in this IC is a phase shift oscillator type designthat operates with a ceramic resonator at eight times the IFfrequency, or 3.60 MHz. With IF input levels below thestereo threshold level, the oscillator is not operational. Thisfeature helps to eliminate audio tweets under low level,noisy input conditions.

MC13028A


The phase locked loop (PLL) in the MC13028A is locked tothe L–R signal. This insures good stereo distortionperformance at the higher levels of left only or right onlymodulations. Under normal operating conditions, the PLLremains locked because of the current flow capability of theloop driver circuit. This high gain, high impedance circuitperforms optimally when the current flow is balanced. Thebalanced condition is enhanced by the loop driver filter circuitconnected between Pin 14 and ground. The filter circuitconsists of a 47 Ω resistor in series with a 47 µF capacitor. The47 Ω resistor is to set the Fast Lock rate. It is recommendedthat the capacitor be a very low leakage type electrolytic, or atantalum composition part because any significant amount ofleakage current flowing through the capacitor will unbalancethe loop driver circuit and result in less than optimum stereoperformance, see Figures 10 and 11.

The pilot tone detector circuit is fed internally from the Qdetector output signal. The circuit input employs a low passfilter at Pin 11 that is designed to prevent the pilot tonedetector input from being overloaded by higher levels of L–Rmodulation. The filter is formed by a 0.22 µF capacitor andthe input impedance of the first amplifier. A pilot I detector

circuit employs a capacitor to ground at Pin 9 to operate inconjunction with an internal resistor to create an RCintegration time. The value of the capacitor determines theamount of time required to produce a stereo indication. Thisamount must include the time it takes to check for thepresence of detector falsing due to noise or interference,station retuning by the customer, and pilot dropout in thepresence of heavy interference. The pilot Q detector utilizesa filter on its pilot tone PLL error line at Pin 10. This capacitorto ground (usually 0.47 µF) is present to filter any lowfrequency L–R information that may be present on the errorline. If the value of this capacitor is allowed to be too small,L–R modulation ripple on the error line may get large enoughto cause stereo dropout. If the capacitor value is made toolarge, the pilot tone may be prevented from being reacquiredif it is somehow lost due to fluctuating field conditions.

A 1.0 V reference level is created internally from the VCCsource to the IC. This regulated line is used extensively bycircuits throughout the MC13028A design. An electrolyticcapacitor from Pin 7 to ground is used as a filter for thereference voltage.

DISCUSSION OF GRAPHS AND FIGURES

If the general recommendations put forth in this applicationguide are followed, excellent stereo performance shouldresult.

The curves in Figures 2 through 7 depict the separationand the distortion performance in stereo for 30%, 50%, and65% single channel modulations respectively. The data forthese figures were collected under the conditions ofVCC = 8.0 V and RO = 10 k in both the left and the rightchannels as applied to the application circuit of Figure 1. Avery precise laboratory generator was used to produce theAM Stereo test signal of 450 kHz at 70 dBµV fed to Pin 4. AnNRSC post detection filter was not present at the time ofthese measurements. The audio separation shows anaverage performance at 30% and 50% modulations of–45 dB in the frequency range of 2.0 kHz to 5.0 kHz. Thecorresponding audio distortions under these conditions areabout 0.28% at 30% modulation, and about 0.41% at 50%modulation.

Figure 6 shows that the typical separation at 65%modulation in the 2.0 kHz to 5.0 kHz region is about –37 dB,and the corresponding audio distortion shown in Figure 7 isabout 1.0%. The performance level of these sinusoidalsignals is somewhat less than those discussed in the

previous paragraph due to the internal operation of theclamping circuits. In the field, the transmitters at AM Stereoradio stations are not usually permitted to modulate singlechannel levels past 70%. Therefore these conditions do notoccur very often during normal broadcast material.

The roll–off at both the low and high frequencies of the30% single channel driven responses is due to the fact that apost detection bandpass filter of 60 Hz to 10 kHz was used inthe measurement of the data, while a post detection filter of2.0 Hz to 20 kHz was used for the collection of data in the50% and 65% modulation examples. The tighter bandwidthwas used while collecting the performance data at 30%modulation levels in order to assure that the distortionmeasurement was indicative of the true distortion productsmeasured near the noise floor and thus not encumbered byresidual noise and hum levels which would erroneously addto the magnitude of the harmonic distortion data. Note inFigure 8 the traces of noise response for the four differentbandwidths of post detection filtering. It can be seen that thenoise floors improve steadily with increasing levels ofincoming 450 kHz as the value of the lower corner frequencyof the filter is increased. Data for the stereo noise floors wascollected with the decoder in the forced stereo mode.

MC13028A


Figure 2. Single Channel Separation at 30% Modulation

100

10

100

0

f, FREQUENCY (Hz)

SEPA

RAT

ION

(dB)

f, FREQUENCY (Hz)

Figure 3. Single Channel Distortion at 30% Modulation

DIS

TORT

ION

(%)

1.0 k 10 k 1.0 k 10 k

–10

– 20

– 30

– 40

1.0

0.1– 50

Undesired Channel

See Text

Desired Channel

DIS

TORT

ION

(%)

SEPA

RAT

ION

(dB)

f, FREQUENCY (Hz) f, FREQUENCY (Hz)


100

10

100

10

100

0

100

0

f, FREQUENCY (Hz)

SEPA

RAT

ION

(dB)

f, FREQUENCY (Hz)




DIS

TORT

ION

(%)

1.0 k 10 k 1.0 k 10 k

1.0 k 10 k1.0 k 10 k

–10

– 20

– 30

– 40

0.1

0.1

1.0

–10

– 20

– 30

– 40

– 50

Desired Channel

Undesired Channel

– 50

1.0

Desired Channel

Undesired Channel

MC13028A


Figure 8. Stereo Noise and Stereo CompositeDistortion when Mono Transmitted

46

1000

40

10

STEREO THRESHOLD (dBµV)

RES

PON

SE F

OR

30%

, MO

NO

MO

DU

LATI

ON

(dB)

SIGNAL STRENGTH (dBµV)

Figure 9. R1 versus Stereo Threshold Point

R1

(k

)

50 60 70 80 48 50 60

0

–10

– 20

– 40

100

10– 60

Ω

– 30

– 50

7.0

4.0

5.0

3.0

1.0

2.0

0

6.0

DIS

TORT

ION

FO

R 8

0% M

ON

O M

OD

ULA

TIO

N (%

)

52 54 56 58

R1 to Gnd

R1 to VCCStereo Audio Level

50 Hz to 3.0 kHz

Noise5.0 Hz to 3.0 kHz

100 Hz to 3.0 kHz

400 Hz to 3.0 kHz

Stereo Composite Distortion

Figure 10. Decoder Separation versus FilterCapacitor (Pin 14) Leakage Current

2.0

– 600

50

LEAKAGE CURRENT (10–9)

SEPA

RAT

ION

(dB)

LEAKAGE CURRENT (10–9)

Figure 11. Decoder Distortion versus FilterCapacitor (Pin 14) Leakage Current

DIS

TORT

ION

, 50%

SIN

GLE

CH

ANN

EL M

OD

– 200 0 200 400 600 – 200 0 200 400 600

45

40

35

30 1.0

20

25

– 600 – 400 – 400

Figure 12. Low Frequency Corner of PLL Response

40

500

10

4.0

INPUT SIGNAL STRENGTH (dBµV)

PLL

LOO

P R

ESPO

NSE

(dB)

MODULATION FREQUENCY (Hz)

Figure 13. AGC Voltage versus Input Signal Level

AGC

VO

LTAG

E LE

VEL

(mV)

100 50 60 70 80

0

– 4.0

– 8.0

300

400

200

100

0–12

Loop Filter 47 µF

Loop Filter 15 µF

Loop Filter 4.7 µF

90

MC13028A


Figure 9 presents more detailed information with respectto the value of resistor R1 at Pin 1 versus the desiredincoming signal level for stereo threshold.

Figures 10 and 11, discussed briefly in the Pin FunctionDescription Section, show the importance of using a qualitycomponent at Pin 14 to ground. It can be seen that anelectrolytic capacitor leakage current of 600 nA canunbalance the PLL to the point where stereo performancemay degrade to only 25 dB of separation with acorresponding 2.0% distortion at 50% modulation levels.

The value of the capacitor connected to Pin 14 (47 µF) isalso a factor in the determination of the low frequency cornerof the PLL circuit response. Three traces of PLL responseappear in Figure 12 where they have been plotted for threedifferent values of loop filter capacitor. The recommendedvalue of 47 µF provides the best response shape in thisparticular circuit set–up where a Murata ProductsCSA3.60MGF108 part is used.

Figure 13 presents the response of the AGC voltageversus decoder input signal level. This is a typical responsewhen the IC is used as shown in the application schematic ofFigure 1. The trace begins approximately at the point ofdecoder sensitivity, and rises rapidly until reaching the areaof stereo sensitivity, approximately 50 dBµV. Thereafter, thecircuit responds in a linear fashion for the next 30 dB of inputsignal increase.

Figures 14 through 17 inclusively depict the VCC ripplerejection performance for the MC13028A under mono andstereo conditions for nominal and for low values of VCC. Itshould be noted that this data was collected without any VCCfiltering. As one might expect, the ripple rejection is better inmono than in stereo. When the decoder operates in stereo,the VCO is functional, thus the decoder becomes moresusceptible to audio ripple on the VCC line. Under normaloperating conditions, with the recommended value of 47 µFat Pin 12 and 10 µF at Pin 7, a VCC ripple reading will bevirtually the same as measuring the noise floor of the IC.

AM STEREO TUNER / FM STEREO IF

Description of ApplicationThis application combines a Sanyo LA1832M with the

Motorola MC13028A AM Stereo decoder IC. The LA1832provides an FM IF, FM multiplex detection, AM tuning, andthe AM IF functions. The MC13028A provides the AM Stereodetection as well as Left and Right audio outputs. AnMC145151 synthesizer provides the frequency control of thelocal oscillator contained within the LA1832. Frequencyselection is by means of a switch array attached to thesynthesizer. The application circuit is shown in Figure 18.

Circuit Board DescriptionThe copper side layout and the component locations are

shown in Figure 19. The view is from the plating side of theboard, with the components shown in hidden view. Severaljumper wires are placed on the component side of the boardto complete the circuit. Posts are provided for electricalconnections to the circuit. The circuit board has been scaledto fit the page, however, the dimensions provide the true size.

Circuit DescriptionThe Sanyo data sheet for the LA1832 should be

consulted for an understanding of the FM detection andmultiplex decoding.

Special PartsThe following information provides circuit function, part

number, and the manufacturer’s name for special partsidentified by their schematic symbol. Where the part is notlimited to a single source, a description sufficient to select apart is given.

U1 IC – AM Stereo DecoderMC13028AD by Motorola

U2 IC – AM/FM IF and Multiplex TunerLA1832M by Sanyo

U3 IC – Frequency SynthesizerMC145151DW2 by Motorola

T1 AM IF CoilA7NRES–11148N by TOKO

F1 AM IF Ceramic FilterSFG450F by Murata

F2 FM IF Detector ResonatorCDA10.7MG46A by Murata

F3 FM Multiplex Decoder ResonatorCSB456F15 by Murata

F4 AM Tuner BlockBL–70 by Korin Giken

X1 10.24 MHz Crystal, Fundamental Mode,AT Cut, 18 pF Load Cap, 35 Ω maximum series R. HC–18/U Holder

X2 3.6 MHz AM Stereo Decoder ResonatorCSA3.60MGF108 by Murata

S5 8 SPST DIP Switch

MC13028A


100

– 20– 20Figure 14. Mono V CC Ripple Rejection

Figure 15. Mono Low Voltage VCC Ripple Rejection

RES

IDU

AL (d

B)

1.0 k100 1.0 k

– 30

– 50

– 60

– 40

– 30

– 40

– 50

RIPPLE FREQUENCY (Hz)RIPPLE FREQUENCY (Hz)

100

0

100

– 20

RIPPLE FREQUENCY (Hz)RIPPLE FREQUENCY (Hz)

Figure 16. Stereo V CC Ripple RejectionFigure 17. Stereo Low Voltage

VCC Ripple Rejection

1.0 k1.0 k

–10

– 30

– 50

– 60

– 40

– 20– 30

– 40

– 50

– 60

– 60

RES

IDU

AL (d

B)

RES

IDU

AL (d

B)R

ESID

UAL

(dB)

VCC = 4.0 V

VCC = 6.0 VVCC = 8.0 V

VCC = 10 V

VCC = 12 V

VCC

100 mVpp 5010 k 10 k

L

R

300 µFDecoder

VCC = 3.0 V

VCC = 4.0 V

VCC = 2.0 V

VCC = 2.1 V

VCC = 2.5 V

VCC

100 mVpp 5010 k 10 k

LR

300 µFDecoder

VCC = 12 V

VCC = 8.0 V

VCC = 10 V

VCC = 4.0 V

VCC = 6.0 V

VCC = 2.0 V

VCC = 2.5 V

VCC = 4.0 V

VCC = 3.0 V

MC13028A


10µ

F

Figure 18. MC13028A Decoder IC Application

V CC

8.0

V

Gnd

C34

2.2

µF

AM A

nt.

Inpu

t

F4 612

3 4

6

12

3 45

C15

0.01

C50

0.02

2C

510.

68R

23 127

R35 681

Q2

2N39

04

R22 332

R27

2.21

k

Q1

2N39

04

D8

1N41

48D

91N

4148

Q4

2N39

06

Q3 2N

3904

R24

3.65

k

R30

332

R28

2.74

k

R26

392

R21

51.1

C27 0.04

7

C52

0.01

R34

10 k

C26

0.04

7R

2530

1FM

IFIn

put

L.O

.

V CC

C53

100

µF

C28

10µ

F

C29

0.01

R39 3.32 k

F3C

401.

0µ

F

Rig

ht

Left

FM A

udio

Rig

ht

Left

AM A

udio

C41

10µ

F

C44

0.01

C43

0.01

FM S

3 Mon

o

Ster

eo

C42

10µ

F

FM AMS

2

R29 127

D7

1N41

48

BL-7

0 An

t. Tu

ning

Blo

ckKo

rin G

iken

C380

.001

2 C37

C35

C36

0.00

470.

047

22µ

F

1.0

µF

C25

C34

2.2

µF

R15

3.01

k

C39

1.0

µF R

1743

kC

30

12

R19

1.0 k

D2

D3

Ster

eoTu

ning

R18 392 F2

1.0 kR20

C12

0.01

MC1

3028

A

LA18

32M

MC1

4515

1DW

AM F

requ

ency

Set

Sw

itch

Loca

l Osc

. Fre

quen

cy

10

kHz

(Bin

ary

Cod

ed, 8

Bits

)

SFG

450F

Mur

ata

F1

T1

612

43

450

kHz

IF

TOKO

A7N

RES

–111

48N

C22

C23

10µ

FC

110

µF

C2

0.47

S4 S

tere

o

AMM

onoC

30.

22X2 3

.6 M

Hz

C9 43

C4

47µ

F

R40

47.5

R2

6.81

kC

13 0.00

1

R3

6.81

kC

14 0.00

1

C20

10µ

F

C19

10µ

F

C6

47µ

F

C5

0.1

R14

10.2

k

C10

10µ

F

C11

0.47

µF

C7

100

µF

C8

0.1

C57

10

C49

68

C48

10 C47

30 V

AR

X110

.24

MH

z

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

1 2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

13 14 15 16 17 18 19 20 21 22 23 24

12 11 10 9 8 7 6 5 4 3 2 1

U2

U3

U1

12

34

56

78

S5

R36

1.0

k

Fig

ure

18. M

C13

028A

Dec

oder

IC A

pplic

atio

n

CD

A10.

7M

G46

AM

urat

a

÷

MC13028A


C47

C57 C49X1

C48 C7

C8D9

R27R28

R24

Q1

Q2

Q4 Q3

R21 R25

U31

S5

18

C15

R39

C29

D3

D2

F2

C52

C53

T1F1

C12

R20

R19

R18

C30

C22 C23

U2

1

C26

C28

C27

BL70F4

C50

C51

C34

C36 C35

C37

C38C40

F3

C42

C44

C41

C43

C39

S2S3

C14

C20

C10C11

X2 C9 R3

C19

C4

R40

C3C2S4

R36

C1C6 C5

C24

C25

1U1

+

+

+

+

+

+ +++

+

++

+

++

+

+

+

++

D8

R23

R22

D7

R30

R29

R26

R35

R15

R17

R14

R2

Figure 19. MC13028A Decoder IC Application Circuit Board

0.50 cm 8.0 cm

9.0 cm

0.50 cm

12.50cm

11.50cm

MC13028A

R34

C13

MC13028A


The LA1832 tuner IC (U2) is set for AM operation byswitch S2 connecting Pin 12 to ground. An AM Stereo signalsource is applied to Pin 2 of the RF coil contained within theBL–70 tuning block. That coil applies the signal to Pin 21 ofU2. The L.O. coil is connected from Pin 23 to VCC. Thesecondary is tuned by a varactor which is controlled by a dcvoltage output from the synthesizer circuit. The reactance ofthis oscillator tank is coupled back to Pin 23. It is through thisreactance that the frequency of the L.O. is determined. Abuffered output from the L.O. emerges at Pin 24. This signalis routed to Pin 1 of the synthesizer (U3), thus completing thefrequency control loop.

The mixer output at Pin 2 is applied to the IF coil T1. CoilT1 provides the correct impedance to drive the ceramicbandpass filter F1. The IF signal returns to U2 throughPin 4, and also to the input, Pin 4 of the AM Stereo decoder(U1). The ceramic filter F1 is designed to operate into aload resistance of 2.0 kΩ. This load is provided at Pin 4 ofU2.

The stereo outputs exit from Pins 15 and 16 of U1. Thedesign amplitudes of the audio outputs will vary according tothe values used for the resistors to ground at Pins 15 and 16of the decoder, (labeled RO in the Electrical CharacteristicsTable and the Test Circuit on page 2 and 3, and in Figure 1,and called R2 and R3 in Figure 18). While the values chosenfor RO are left to the discretion of the designer, the numberschosen in this data sheet are reflective of those required toset the general industry standard levels of audio outputs inreceiver designs.

Pins 15 and 16 are also good locations for the insertion ofsimple RC filters that are used to comply with the UnitedStates NRSC requirement for the shape of the overallreceiver audio response. The following curve, Figure 20,shows the response of this U.S. standard.

100

0

ATTE

NU

ATIO

N (d

B)

f, FREQUENCY (Hz)

Figure 20. NRSC De–Emphasis Curve for the United States

200 500 1.0 k 2.0 k 10 k

– 2.0

– 4.0

– 6.0

–10

– 8.0

5.0 k

There are many design factors that affect the shape of thereceiver response, and they must all be considered whentrying to approximate the NRSC de–emphasis response. Themixer output transformer (IF coil, T1), and ceramic filterprobably have the greatest contribution to the frequencyresponse. The ceramic filter can be tailored from its ratedresponse by the choice of transformer impedance andbandwidth. When designing an overall audio responseshape, the response of the speakers or earphones shouldalso be considered.

Component Values.The Pin Function Description table gives specific

information on the choice of components to be used ateach pin of U1. A similar section in the Sanyo LA1832 datasheet should be consulted as to the components to be usedwith U2.Tuning

The frequency to which the test circuit will tune is set bythe eight binary switches contained in the S5 assembly,numbered from 1 to 8. Number 1 connects to Pin 11 of U3and number 8 connects to Pin 18. The other switchesconnect to the pins in between and in order. Each individualswitch is a SPST type.

To tune to a specific RF frequency, a computation must bemade in order to ascertain the divide ratio to input to thesynthesizer via the switch array. The divide ratio is simply theeight digit binary equivalent number for the local oscillatorfrequency divided by 10 kHz. The local oscillator frequency isthe desired RF frequency plus 450 kHz, the IF frequency. Anylocal oscillator value within the AM band can be representedby a binary number. Each binary bit represents a switchsetting where a “1” is an open switch and a “0” is a closedswitch. The most significant bit represents switch 8 which isconnected to Pin 18.

To illustrate, consider the setting for an input frequency of1070 kHz. (This frequency was used to test the circuit boardas described further on.) The local oscillator frequency is1070 kHz plus 450 kHz which equals 1520 kHz. Dividing by10 kHz yields the number 152. The binary number for 152 is10011000. Thus the switches are set to:

Switch Position Number

8 Open 1

7 Closed 0

6 Closed 0

5 Open 1

4 Open 1

3 Closed 0

2 Closed 0

1 Closed 0

Circuit AdjustmentsThe FM circuit requires no adjustment. The AM L.O. must

be able to tune from 980 to 2150 kHz to cover the broadcastrange. Adjust the core of the L.O. coil if needed in order to beable to cover this range. The AM RF coil and trimmer can beadjusted for best signal after connection to the loop antenna.The coil is adjusted near the low end of the band, and thetrimmer is adjusted at the top of the band. The IF coil, T1, isfirst adjusted for maximum signal out of the filter, F1. This isa “coarse” adjustment. The final “fine tune” adjustmentoccurs after the following conditions are met. From an AMStereo generator with the pilot tone off, feed the decoder aninput signal of approximately 70 dBµV that is modulated withan 80% L–R audio signal at 3.0 kHz. While monitoring eitherthe left or the right output from the decoder on anoscilloscope, precisely fine tune the IF coil for a minimumresidual signal, see the following diagram. If there is nosideband tilt in the system, this adjustment should hold forboth channels. Otherwise, the best compromise adjustmentfor both channels should be used.

MC13028A


Figure 21. Decoder Signal Output for Mistuned and Tuned Condition with Input Signal of 80%

L–R at 3.0 kHz

Mistuned

Tuned

AM Circuit TestThe connections for test are as shown in Figure 22. A 50 Ω

resistor is placed on the AM antenna input. The AM Stereogenerator is connected to the AM antenna input.Measurements of audio level in mono mode are made withan audio voltmeter connected through a FET probe (pilotsignal “off”). Measurements of audio level and distortion instereo mode (pilot signal “on”) are made using a pilotrejection filter ahead of the distortion analyzer or the audiometer. The pilot rejection filter has a rejection ratio that shouldexceed 20 to 25 dB. Typical data is shown in Figures 23–26.Figures 23 and 24 were read on the left channel in monomode. Figures 25–26 were in stereo mode.

Figure 22. MC13028A/LA1832 Application Circuit Board Test Setup

MC13028A/LA1832 ApplicationCircuit Board Test

Am StereoGenerator1070 kHz

50 Ω Output

50 Ω

AM Ant. Input

Ant. Tuning Block

1

U1

MC13028A

AM Stereo Audio Output

�

�

Left

Right

For Stereo Measurements, Pilot On

DistortionAnalyzer

andAudio Voltmeter

Pilot Filterand

Buffer Amp

FET Probe

Audio Voltmeter

MC13028A


dB O

UT

0

7.0

0

0

PEAK (dBµV)INPUT (dBµV)

Figure 23. Left AM Output at 30% Modulation Figure 24. Left AM Output at 80% Modulation

40 60 80 100 12040 60 80 120

6.0

4.0

2.0

0

1.0

3.0

5.0–10

– 20

– 30

– 50

100

10

100

10

dB O

UT

TONE (Hz)TONE (Hz)

Figure 25. AM Output Right Channel OnlyModulated at 50%

Figure 26. AM Output Left Channel OnlyModulated at 50%

dB O

UT

1.0 k 10 k1.0 k 10 k

0

–10

– 30

– 40

0

–10

– 20

– 30

% D

ISTO

RTIO

N%

DIS

TORT

ION

% D

ISTO

RTIO

N

7.0

6.0

4.0

2.0

0

1.0

3.0

5.0

4.0

2.0

0

1.0

3.0

5.0

– 40

– 60

– 40

10

% D

ISTO

RTIO

N

2.0

0

3.0

5.0

2020 100

– 20

1.0

4.0

Out

Noise

0 dB = 90 mVrms

Distortion

Out

0 dB = 150 mVrms

Channel Separation

Out

0 dB = 150 mVrms

Channel Separation

Distortion Distortion

1000 kHz 1000 kHz

MC13028A


OUTLINE DIMENSIONS

D SUFFIXPLASTIC PACKAGE

CASE 751B–05(SO–16)ISSUE J

0.25 (0.010) T B AM S S

MIN MINMAX MAXMILLIMETERS INCHES

DIMABCDFGJKMPR

9.803.801.350.350.40

0.190.10

0°5.800.25

10.004.001.750.491.25

0.250.25

7° 6.200.50

0.3860.1500.0540.0140.016

0.0080.004

0° 0.2290.010

0.3930.1570.0680.0190.049

0.0090.009

7° 0.2440.019

1.27 BSC 0.050 BSC

NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.

1 8

916

–A–

–B–

D 16 PL

K

C

G

–T–SEATING

PLANE

R X 45°

M J

F

P 8 PL0.25 (0.010) BM M

P SUFFIXPLASTIC PACKAGE

CASE 648–08ISSUE R

MIN MINMAX MAXINCHES MILLIMETERS

DIMABCDFGHJKLMS

18.806.353.690.391.02

0.212.807.50

0°0.51

19.556.854.440.531.77

0.383.307.7410°1.01

0.7400.2500.1450.0150.040

0.0080.1100.295

0°0.020

0.7700.2700.1750.0210.070

0.0150.1300.305

10°0.040

NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.5. ROUNDED CORNERS OPTIONAL.

2.54 BSC1.27 BSC

0.100 BSC0.050 BSC

–A–

B1 8

916

F

HG

D 16 PL

S

C

–T–

SEATINGPLANE

K JM

L

T A0.25 (0.010) M M

MC13028A


Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, andspecifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motoroladata sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights ofothers. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or otherapplications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injuryor death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorolaand its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney feesarising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges thatMotorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an EqualOpportunity/Affirmative Action Employer.

How to reach us:USA/EUROPE/Locations Not Listed : Motorola Literature Distribution; JAPAN : Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315

MFAX: [email protected] – TOUCHTONE 602–244–6609 ASIA/PACIFIC : Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

MC13028A/D

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