ADVANCED VLSI CHAP8-4
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Transcript of ADVANCED VLSI CHAP8-4
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Topics
High-level synthesis.
Architectures for low power.
GALS design.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
High-level synthesis
Sequential operation is not the most
abstract description of behavior.
We can describe behavior without
assigning operations to particular clock
cycles.
High-level synthesis (behavioral synthesis)transforms an unscheduled behavior into a
register-transfer behavior.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Tasks in high-level synthesis
Scheduling: determines clock cycle on
which each operation will occur.
Binding (allocation): chooses which
function units will execute which
operations.
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Functional modeling code in
VHDL
o1
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Data dependencies
Data dependencies describe relationships
between operations:
x
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Data flow graph
Data flow graph (DFG) models data
dependencies.
Does not require that operations be
performed in a particular order.
Models operations in a basic block of a
functional modelno conditionals.
Requires single-assignment form.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Data flow graph construction
original code:
x
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Data flow graph construction,
contd
Data flow forms directed acyclic graph
(DAG):
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Goals of scheduling and
allocation
Preserve behaviorat end of execution,
should have received all outputs, be in
proper state (ignoring exact times ofevents).
Utilize hardware efficiently.
Obtain acceptable performance.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Data flow to data path-controller
One feasible schedule for last DFG:
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Binding values to registers
registers fall on
clock cycle
boundaries
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Choosing function units
muxes allow
function units
to be sharedfor several
operations
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Building the sequencer
sequencer requires three states,
even with no conditionals
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Choices during high-level
synthesis
Scheduling determines number of clock
cycles required; binding determines area,
cycle time. Area tradeoffs must consider shared
function units vs. multiplexers, control.
Delay tradeoffs must consider cycle timevs. number of cycles.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Finding schedules
Two simple schedules:
As-soon-as-possible (ASAP) schedule puts
every operation as early in time as possible.As-late-as-possible (ALAP) schedule puts
every operation as late in schedule as possible.
Many schedules exist between ALAP andASAP extremes.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
ASAP and ALAP schedules
ASAP
ALAP
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Critical path of schedule
Longest path through data flow determines
minimum schedule length:
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Operator chaining
May execute several
operations in sequence in one
cycleoperator chaining. Delay through function units
may not be additive, such as
through several adders.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Control implementation
Clock cycles are also known as control
steps.
Longer schedule means more states incontroller.
Cost of controller may be hard to judge
from casual inspection of state transitiongraph.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Controllers and scheduling
functional
model:
x
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Distributed control
one centralized controller
two distributed controllers
S h i d i i
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Synchronized communication
between FSMs
To pass values between two machines, must schedule output
of one machine to coincide with input expected by the other:
H d i d i d d
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Hardwired vs. microcoded
control
Hardwired control has a state register and
random logic.
A microcoded machine has a state registerwhich points into a microcode memory.
Styles are equivalent; choice depends on
implementation considerations.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Data path-controller delay
Watch out for long delay paths created by
combination of data path and controller:
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Architectures for low power
Power controller
examines system
state, controlssubsystems.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Power-down modes
CMOS doesnt consume power when not
transitioning. Many systems can
incorporate power-down modes:condition the clock on power-down mode;
add state to control for power-down mode;
modify the control logic to ensure that power-down/power-up dont corrupt control state.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Gate power control
Some gate types have low power modes.
Sleep transistor.
Can also change substrate voltage in aregion.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Data latching
Store data in registers to avoid glitching in
combinational logic.
Use conditional clocks on existing latchesto hold data when not in use.
Avoid improper use of dynamic storage.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Clock gating
Clock gating can cause clocked logic to
freeze state.
Must make sure that logic operatesproperly when frozen, when turned back
on.
Must carefully design clock network withgating to avoid skew, etc.
A hit t d i lt
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Architecture-driven voltage
scaling
Add extra logic to increase parallelism so
that system can run at lower rate.
Power improvement for n parallel unitsover Vref:
Pn(n) = [1 + Ci(n)/nCref+ Cx(n)/Cref](V/Vref)
A hit t d i lt
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Architecture-driven voltage
scaling
before
after
D i lt d f
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Dynamic voltage and frequency
scaling
Technique for microprocessors:
Control power supply voltage and clock.
Clock frequency must be in legal range forpower supply voltage setting.
Relies on dynamic workload---
microprocessor may not need to run at fullspeed.
DVFS controller sets power supply, clock.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
GALS design
Globally asynchronous, locally
synchronous design uses different clock
domains for different parts of the chips. Styles:
Pausable clocks.
Asynchronous interfaces.Loosely synchronous interfaces.
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M d VLSI D i 4 Ch t 8 C i ht 2008 W W lf
GALS structure