Advanced VHDL for Design - Leading EdgeAdvanced VHDL for Design. A 3 day course introducing VHDL...

Advanced VHDL for Design A 3 day course introducing VHDL language features which are not commonly known or used. The 3-day Advanced VHDL for Design class is aimed at experienced VHDL users who wish to take advantage of the lesser known aspects of the VHDL language to create reliable, re-usable design units in a standardised manner. A pre-requisite for this course is the Introducon to VHDL course or equivalent experience. Topics Covered • Introducon • Recap of design units • Latest VHDL Standards • The RTL Synthesis Subset • Books and Other Resources • The ASIC Design Flow • VHDL in the Design Flow • Effects of Coding on Synthesis Results • Coding Styles and Synthesis Runme • Type Guidelines • Types and Subtypes • Recommended Types for Synthesis • Preparing for Reuse • Advantages of Reuse • Designing Reusable IP • Managing VHDL Libraries • Limitaons of Standard Approaches • Recommended Library Structure • Exploing Enes and Architectures • Types of Design Unit • Advantages of Mulple Architectures • Synthesis Consideraons • Using Sub-programs Efficiently • Sub-program recap • Reasons for Using Sub-programs • Synthesis Limitaons • VHDL Configuraons • The Power of Configuraons • What Works With Synthesis • Opmising for Power • Power Reducon Techniques • RTL Tips to Reduce Power

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Transcript of Advanced VHDL for Design - Leading EdgeAdvanced VHDL for Design. A 3 day course introducing VHDL...

Advanced VHDL for Design

A 3 day course introducing VHDL language features which are not commonly known or used.

The 3-day Advanced VHDL for Design class is aimed at experienced VHDL users who wish to take

advantage of the lesser known aspects of the VHDL language to create reliable, re-usable design

units in a standardised manner.

A pre-requisite for this course is the Introduction to VHDL course or equivalent experience.

Topics Covered

• Introduction• Recap of design units• Latest VHDL Standards• The RTL Synthesis Subset• Books and Other Resources

• The ASIC Design Flow• VHDL in the Design Flow• Effects of Coding on Synthesis Results• Coding Styles and Synthesis Runtime

• Type Guidelines• Types and Subtypes• Recommended Types for Synthesis

• Preparing for Reuse• Advantages of Reuse• Designing Reusable IP

• Managing VHDL Libraries• Limitations of Standard Approaches• Recommended Library Structure

• Exploiting Entities and Architectures• Types of Design Unit• Advantages of Multiple Architectures• Synthesis Considerations

• Using Sub-programs Efficiently• Sub-program recap• Reasons for Using Sub-programs• Synthesis Limitations

• VHDL Configurations• The Power of Configurations• What Works With Synthesis

• Optimising for Power• Power Reduction Techniques• RTL Tips to Reduce Power

Page 2: Advanced VHDL for Design - Leading EdgeAdvanced VHDL for Design. A 3 day course introducing VHDL language features which are not commonly known or used. The 3-day Advanced VHDL for

• Optimising for Speed• Techniques to Improve Design Performance• RTL Tips to Improve Performance

• Optimising for Area• Techniques to Reduce Area• RTL Tips to Reduce Area

The course is a consistent mix of lecture and lab-exercises. Targeted quizzes and labs are designed

to reinforce the course material.

Who Should Attend

Experienced VHDL design and verification engineers wishing to expand their knowledge of VHDL to

include the latest techniques.

Prerequisites

Introduction to VHDL class and experience writing VHDL testbenches.

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Advanced VHDL for Design - Leading EdgeAdvanced VHDL for Design. A 3 day course introducing VHDL...

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Transcript of Advanced VHDL for Design - Leading EdgeAdvanced VHDL for Design. A 3 day course introducing VHDL...