Advanced Tools for Simulation and Design of...

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ASP-DAC 2007. Copyright © 2001-2006, J Roychowdhury and ASVG, Univ of Minnesota Slide 1 Advanced Tools for Simulation and Design of Oscillators/PLLs Xiaolue Lai and Jaijeet Roychowdhury University of Minnesota, Minneapolis, USA

Transcript of Advanced Tools for Simulation and Design of...

Page 1: Advanced Tools for Simulation and Design of Oscillators/PLLspotol.eecs.berkeley.edu/~jr/research/PDFs/2007-ASPDAC-Lai-Roychowdhury-OscPLL-invited.pdfinefficient for even 1-transistor

ASP-DAC 2007. Copyright © 2001-2006, J Roychowdhury and ASVG, Univ of Minnesota Slide 1

Advanced Tools for Simulation and Design of Oscillators/PLLs

Xiaolue Lai and Jaijeet Roychowdhury

University of Minnesota, Minneapolis, USA

Page 2: Advanced Tools for Simulation and Design of Oscillators/PLLspotol.eecs.berkeley.edu/~jr/research/PDFs/2007-ASPDAC-Lai-Roychowdhury-OscPLL-invited.pdfinefficient for even 1-transistor

ASP-DAC 2007. Copyright © 2001-2006, J Roychowdhury and ASVG, Univ of Minnesota Slide 2

Oscillators: A Special Simulation Challenge

● Computation/size/accuracy: much greater than for amps/mixers

● inefficient for even 1-transistor oscillators● long startups: many cycles● tiny timesteps needed per cycle

● integrated RF: 100s to 1000s of transistors● errors dependent on size of timesteps, integration method,

size of perturbations● fundamental cause: marginal phase stability of all

oscillators● numerical errors integrate over time

 SPICE­based perturbation analysis of oscillators is not a good idea

Page 3: Advanced Tools for Simulation and Design of Oscillators/PLLspotol.eecs.berkeley.edu/~jr/research/PDFs/2007-ASPDAC-Lai-Roychowdhury-OscPLL-invited.pdfinefficient for even 1-transistor

ASP-DAC 2007. Copyright © 2001-2006, J Roychowdhury and ASVG, Univ of Minnesota Slide 3

Alternatives to SPICE-level simulation

● Use simplified phase macromodels● Obtain effects of external perturbations on phase

directly without simulating the full circuit● (Linear Time-Invariant (LTI) models)

Ken Kundert, Cadence

Linear VCO macromodel

Page 4: Advanced Tools for Simulation and Design of Oscillators/PLLspotol.eecs.berkeley.edu/~jr/research/PDFs/2007-ASPDAC-Lai-Roychowdhury-OscPLL-invited.pdfinefficient for even 1-transistor

ASP-DAC 2007. Copyright © 2001-2006, J Roychowdhury and ASVG, Univ of Minnesota Slide 4

● Linear models are not generally applicable for all effects

● LTI model: narrow applicability● LPTV models, including: 

● Kaertner's LPTV IRF● Hajimiri's closed­form ISF● better, but validity depends on circuit/dynamical 

effects ● Eg, cannot capture nonlinear phenomena

● injection locking, jitter, cycle slips, power grid noise effects, ...

Limitations of Linear Phase Macromodels

Page 5: Advanced Tools for Simulation and Design of Oscillators/PLLspotol.eecs.berkeley.edu/~jr/research/PDFs/2007-ASPDAC-Lai-Roychowdhury-OscPLL-invited.pdfinefficient for even 1-transistor

ASP-DAC 2007. Copyright © 2001-2006, J Roychowdhury and ASVG, Univ of Minnesota Slide 5

Automatically-extracted Oscillator Macromodelworks for ALL effects, ALL oscillators

Coupled oscs

PLL Lock/Capture

Phase noise,timing jitter

ONESmall,

Nonlinear phase/amplitude

macromodel(fast to simulate)

Nano/Bioapplications

Fast envelopemethods

PLL cycle slipping

ANY oscillator (Ring, LC, biological, ...) (SPICE-level circuit, ordifferential equations)

Automated ExtractionAlgorithms

Fast SimulationAlgorithms

Injection locking

Power/groundinterference jitter

Early design tools/formulae

PLL design methodology

Oscillator AC

Page 6: Advanced Tools for Simulation and Design of Oscillators/PLLspotol.eecs.berkeley.edu/~jr/research/PDFs/2007-ASPDAC-Lai-Roychowdhury-OscPLL-invited.pdfinefficient for even 1-transistor

ASP-DAC 2007. Copyright © 2001-2006, J Roychowdhury and ASVG, Univ of Minnesota Slide 6

Phase error/ jitter

Noise “Input”

Perturbation Projection Vector (PPV/NISF)

Phase macromodel is nonlinear and scalar(nonlinear = captures complex dynamics)

(scalar = small, fast to evaluate)

Drop-in replacement for linear phase models

Automatically Extracted Nonlinear Oscillator Macromodel

Page 7: Advanced Tools for Simulation and Design of Oscillators/PLLspotol.eecs.berkeley.edu/~jr/research/PDFs/2007-ASPDAC-Lai-Roychowdhury-OscPLL-invited.pdfinefficient for even 1-transistor

ASP-DAC 2007. Copyright © 2001-2006, J Roychowdhury and ASVG, Univ of Minnesota Slide 7

LTI LPTV Our approach

Jitter from white noise Flicker/coloured jitter Supply interference jitter VCO frequency control Injection locking PLL lock/capture Cycle slipping Amplitude effects NA NA

Model generation speed Poor ExcellentModel gen. robustness Poor MediocreModel simulation speed Excellent Excellent Excellent

i

ii i

i ii

Poor iGood i

Feature Comparison with Existing Methods

Page 8: Advanced Tools for Simulation and Design of Oscillators/PLLspotol.eecs.berkeley.edu/~jr/research/PDFs/2007-ASPDAC-Lai-Roychowdhury-OscPLL-invited.pdfinefficient for even 1-transistor

ASP-DAC 2007. Copyright © 2001-2006, J Roychowdhury and ASVG, Univ of Minnesota Slide 8

PLL Capture and Lock Transients

Page 9: Advanced Tools for Simulation and Design of Oscillators/PLLspotol.eecs.berkeley.edu/~jr/research/PDFs/2007-ASPDAC-Lai-Roychowdhury-OscPLL-invited.pdfinefficient for even 1-transistor

ASP-DAC 2007. Copyright © 2001-2006, J Roychowdhury and ASVG, Univ of Minnesota Slide 9

PLL Capture/Lock: fref=1.07f0

Nonlinear

Reference(full simulation)

LTI

>1000x speedup over full simulation

Page 10: Advanced Tools for Simulation and Design of Oscillators/PLLspotol.eecs.berkeley.edu/~jr/research/PDFs/2007-ASPDAC-Lai-Roychowdhury-OscPLL-invited.pdfinefficient for even 1-transistor

ASP-DAC 2007. Copyright © 2001-2006, J Roychowdhury and ASVG, Univ of Minnesota Slide 10

PLL Capture/Lock: fref = 1.074 f0

Nonlinear Reference(full simulation)

LTI

>1000x speedup over full simulation

Page 11: Advanced Tools for Simulation and Design of Oscillators/PLLspotol.eecs.berkeley.edu/~jr/research/PDFs/2007-ASPDAC-Lai-Roychowdhury-OscPLL-invited.pdfinefficient for even 1-transistor

ASP-DAC 2007. Copyright © 2001-2006, J Roychowdhury and ASVG, Univ of Minnesota Slide 11

PLL Capture/Lock: fref = 1.083 f0

NonlinearReference

(full simulation)LTI

>1000x speedup over full simulation

Page 12: Advanced Tools for Simulation and Design of Oscillators/PLLspotol.eecs.berkeley.edu/~jr/research/PDFs/2007-ASPDAC-Lai-Roychowdhury-OscPLL-invited.pdfinefficient for even 1-transistor

ASP-DAC 2007. Copyright © 2001-2006, J Roychowdhury and ASVG, Univ of Minnesota Slide 12

Oscillator and PLL jitter due to Supply Interference

Page 13: Advanced Tools for Simulation and Design of Oscillators/PLLspotol.eecs.berkeley.edu/~jr/research/PDFs/2007-ASPDAC-Lai-Roychowdhury-OscPLL-invited.pdfinefficient for even 1-transistor

ASP-DAC 2007. Copyright © 2001-2006, J Roychowdhury and ASVG, Univ of Minnesota Slide 13

Ring Oscillator: Per-cycle jitter as a function of sinusoidal supply

interference frequency

Nonlinear

Reference(full simulation)

Closed-form (LPTV) ISF

~100x speedup over full simulation

PPV, used in LPTV equation

Page 14: Advanced Tools for Simulation and Design of Oscillators/PLLspotol.eecs.berkeley.edu/~jr/research/PDFs/2007-ASPDAC-Lai-Roychowdhury-OscPLL-invited.pdfinefficient for even 1-transistor

ASP-DAC 2007. Copyright © 2001-2006, J Roychowdhury and ASVG, Univ of Minnesota Slide 14

PLL: Max jitter as function of supply interference frequency

Nonlinear

Reference(full simulation)

Closed-form (LPTV) ISF

>1000x speedup over full simulation

Page 15: Advanced Tools for Simulation and Design of Oscillators/PLLspotol.eecs.berkeley.edu/~jr/research/PDFs/2007-ASPDAC-Lai-Roychowdhury-OscPLL-invited.pdfinefficient for even 1-transistor

ASP-DAC 2007. Copyright © 2001-2006, J Roychowdhury and ASVG, Univ of Minnesota Slide 15

PLL Cycle Slipping

Page 16: Advanced Tools for Simulation and Design of Oscillators/PLLspotol.eecs.berkeley.edu/~jr/research/PDFs/2007-ASPDAC-Lai-Roychowdhury-OscPLL-invited.pdfinefficient for even 1-transistor

ASP-DAC 2007. Copyright © 2001-2006, J Roychowdhury and ASVG, Univ of Minnesota Slide 16

PLL: cycle slipping (5mA, 10T shock)

Nonlinear

Reference(full simulation)

LTI

>1000x speedup over full simulation

Page 17: Advanced Tools for Simulation and Design of Oscillators/PLLspotol.eecs.berkeley.edu/~jr/research/PDFs/2007-ASPDAC-Lai-Roychowdhury-OscPLL-invited.pdfinefficient for even 1-transistor

ASP-DAC 2007. Copyright © 2001-2006, J Roychowdhury and ASVG, Univ of Minnesota Slide 17

PLL: cycle slipping (3mA, 10T shock)

NonlinearReference(full simulation)

LTI

>1000x speedup over full simulation

Page 18: Advanced Tools for Simulation and Design of Oscillators/PLLspotol.eecs.berkeley.edu/~jr/research/PDFs/2007-ASPDAC-Lai-Roychowdhury-OscPLL-invited.pdfinefficient for even 1-transistor

ASP-DAC 2007. Copyright © 2001-2006, J Roychowdhury and ASVG, Univ of Minnesota Slide 18

Impact of Nonlinear Macromodelson PLL Design Process

Page 19: Advanced Tools for Simulation and Design of Oscillators/PLLspotol.eecs.berkeley.edu/~jr/research/PDFs/2007-ASPDAC-Lai-Roychowdhury-OscPLL-invited.pdfinefficient for even 1-transistor

ASP-DAC 2007. Copyright © 2001-2006, J Roychowdhury and ASVG, Univ of Minnesota Slide 19

Injection-aided PLL structure

PFD

HPF

LPFReferencefrequency

1N

VCOLPF

switch

● Lock acquisition time reduction is important● High-pass path: induces injection locking

● speeds lock acquisition● Once locked, HPF path is switched out of the loop

● to lower phase noise in lock

Page 20: Advanced Tools for Simulation and Design of Oscillators/PLLspotol.eecs.berkeley.edu/~jr/research/PDFs/2007-ASPDAC-Lai-Roychowdhury-OscPLL-invited.pdfinefficient for even 1-transistor

ASP-DAC 2007. Copyright © 2001-2006, J Roychowdhury and ASVG, Univ of Minnesota Slide 20

PLL Capture (freq shift vs time)

● ~3x faster lock acquisition due to injection aiding

With HPF pathWithout HPF path

Page 21: Advanced Tools for Simulation and Design of Oscillators/PLLspotol.eecs.berkeley.edu/~jr/research/PDFs/2007-ASPDAC-Lai-Roychowdhury-OscPLL-invited.pdfinefficient for even 1-transistor

ASP-DAC 2007. Copyright © 2001-2006, J Roychowdhury and ASVG, Univ of Minnesota Slide 21

● Linear macromodels: wrong results (though fast)● can mislead, waste design time

● Nonlinear macromodels: can be trusted during design● sanity checking via SPICE-level simulation: still indispensable

● ~80 simulations in all● ~5 full SPICE-level simulations● macromodel offers 100-1000x speedup over full

● few minutes/simulation (including macromodel generation)

● Enables much more thorough exploration of design space● many combinations of parameters, injection paths, ...● Impractical using full simulation alone

● Design exploration completed in ~1 week● Estimate: 10x saving in design time vs prior methodologies

● (with much more complete exploration)

Nonlinear PLL Macromodel: Benefits for Design

Page 22: Advanced Tools for Simulation and Design of Oscillators/PLLspotol.eecs.berkeley.edu/~jr/research/PDFs/2007-ASPDAC-Lai-Roychowdhury-OscPLL-invited.pdfinefficient for even 1-transistor

ASP-DAC 2007. Copyright © 2001-2006, J Roychowdhury and ASVG, Univ of Minnesota Slide 22

Coupled Oscillator Systems

Page 23: Advanced Tools for Simulation and Design of Oscillators/PLLspotol.eecs.berkeley.edu/~jr/research/PDFs/2007-ASPDAC-Lai-Roychowdhury-OscPLL-invited.pdfinefficient for even 1-transistor

ASP-DAC 2007. Copyright © 2001-2006, J Roychowdhury and ASVG, Univ of Minnesota Slide 23

Brusselator biochemical oscillators

Brusselator biochemical

oscillators

Coupling(diffusion)

terms

“Network model” ofcoupled oscillators

Page 24: Advanced Tools for Simulation and Design of Oscillators/PLLspotol.eecs.berkeley.edu/~jr/research/PDFs/2007-ASPDAC-Lai-Roychowdhury-OscPLL-invited.pdfinefficient for even 1-transistor

ASP-DAC 2007. Copyright © 2001-2006, J Roychowdhury and ASVG, Univ of Minnesota Slide 24

Spontaneous Pattern Formation: 160,000coupled Brusselator oscillators (g=1/15)

Simulation time: 200 minutes for 160 cycles (MATLAB); est speedup 1200x

Page 25: Advanced Tools for Simulation and Design of Oscillators/PLLspotol.eecs.berkeley.edu/~jr/research/PDFs/2007-ASPDAC-Lai-Roychowdhury-OscPLL-invited.pdfinefficient for even 1-transistor

ASP-DAC 2007. Copyright © 2001-2006, J Roychowdhury and ASVG, Univ of Minnesota Slide 25

Summary

Nonlinear oscillator macromodel captures: injection locking PLL lock and capture PLL cycle slipping phase noise and jitter in oscillators and PLLs pattern formation in biochemistry

Productivity enhancer for in design flows 10x faster?

Better, more completely explored designs