ADVANCED PWM SCHEMES FOR 3-PHASE …cascaded H-bridge multilevel inverter, simulated for di erent...

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ADVANCED PWM SCHEMES FOR 3-PHASE CASCADED H-BRIDGE 5- LEVEL INVERTERS Devineni Gireesh Kumar 1 , Dr. C. Subbarami Reddy 2 , Dr. N. Bhoopal 3 1 Assistant Professor, 2,3 Professor, Department of EEE BVRIT, Narsapur, Medak dist. Telangana July 18, 2018 Abstract A multilevel inverter is a power electronic device that is used for high voltage and high power applications such as flexible AC transmission systems, uninterruptible power supplies and PV systems and their performance is better to that of conventional two-level inverters due to higher number of dc voltage sources, reduced harmonic distortion and lower EMI. A Carrier phase-sifted PWM technique is used for the proposed multilevel inverter because it offers great advantages such as is improved output voltage wave- forms, minimize total harmonic distortion, and control EMI when compared with other PWM techniques. The perfor- mance evaluation of a five level cascaded multilevel inverter (MLI) using advance pulse width modulation (PWM) tech- niques for constant switching frequency (CSF) operation are presented in this paper. Multilevel inverter operation for CFO with Phase disposition (PD), Phase opposition disposition (POD), Alternate phase opposition disposition (APOD) PWM control methods is simulated in MATLAB. Also variations in MLI performance parameters such as To- tal Harmonic Distortion (THD) in output voltage, peak 1 International Journal of Pure and Applied Mathematics Volume 120 No. 6 2018, 7795-7807 ISSN: 1314-3395 (on-line version) url: http://www.acadpubl.eu/hub/ Special Issue http://www.acadpubl.eu/hub/ 7795

Transcript of ADVANCED PWM SCHEMES FOR 3-PHASE …cascaded H-bridge multilevel inverter, simulated for di erent...

Page 1: ADVANCED PWM SCHEMES FOR 3-PHASE …cascaded H-bridge multilevel inverter, simulated for di erent con-trol techniques (PD, POD, APOD) and the results are compared in terms of total

ADVANCED PWM SCHEMES FOR3-PHASE CASCADED H-BRIDGE 5-

LEVEL INVERTERS

Devineni Gireesh Kumar1,Dr. C. Subbarami Reddy2, Dr. N. Bhoopal3

1Assistant Professor, 2,3Professor,Department of EEE

BVRIT, Narsapur, Medak dist. Telangana

July 18, 2018

Abstract

A multilevel inverter is a power electronic device thatis used for high voltage and high power applications suchas flexible AC transmission systems, uninterruptible powersupplies and PV systems and their performance is betterto that of conventional two-level inverters due to highernumber of dc voltage sources, reduced harmonic distortionand lower EMI. A Carrier phase-sifted PWM technique isused for the proposed multilevel inverter because it offersgreat advantages such as is improved output voltage wave-forms, minimize total harmonic distortion, and control EMIwhen compared with other PWM techniques. The perfor-mance evaluation of a five level cascaded multilevel inverter(MLI) using advance pulse width modulation (PWM) tech-niques for constant switching frequency (CSF) operationare presented in this paper. Multilevel inverter operationfor CFO with Phase disposition (PD), Phase oppositiondisposition (POD), Alternate phase opposition disposition(APOD) PWM control methods is simulated in MATLAB.Also variations in MLI performance parameters such as To-tal Harmonic Distortion (THD) in output voltage, peak

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International Journal of Pure and Applied MathematicsVolume 120 No. 6 2018, 7795-7807ISSN: 1314-3395 (on-line version)url: http://www.acadpubl.eu/hub/Special Issue http://www.acadpubl.eu/hub/

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value of fundamental component of voltage, etc. are an-alyzed with each PWM control strategy. The effects of loadperturbation on the profile of phase, line voltage and currentin MLI are also described. A comparative study is presentedin terms of THD, peak value of fundamental component ofvoltage and current under different load conditions.

1 INTRODUCTION

Multilevel inverters are very popular because they had great advan-tages over conventional inverters[9]. The Multilevel inverters usessemiconductor switches for their circuit construction and provideshigh voltage and high power levels at their output. With the in-crease in number of levels in output, the harmonic content as wellas the electromagnetic interference (EMI) will reduce. The need fordesigning the multilevel inverters is to achieve the high power out-put from low voltage batteries. The multilevel output seems likea staircase (stepped wave), which is almost similar to sinusoidalwave shape. The output of low distortion is thus obtained by pro-viding control signals to the gates of semiconductor switches tocontrol their switching frequencies. In this work the control signalsto the semiconductor switches of multilevel inverters are generatedfrom PWM schemes. This paper presenting a 5-level three phasecascaded H-bridge multilevel inverter, simulated for different con-trol techniques (PD, POD, APOD) and the results are comparedin terms of total harmonic distortion in each technique. The figure(1), shows the 5-level single phase cascaded multilevel inverter, heretwo full bridge inverters are cascaded to form a single phase 5-levelH- bridge inverter, which uses eight semiconductor switches andtwo batteries or DC voltage sources. The resultant output magni-tude of the cascaded inverter is equal to sum of the input batteryvoltages. The DC source voltage of inverter-1 is V1 and inverter-2is V2. The cascaded connection provides the magnitude of voltageas V = V1 + V2.

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Figure 1: Single phase cascaded 5-level inverter

2 CONTROL SCHEMES FOR 3-PHASE

5-LEVEL INVERTER

There are various control schemes available for cascaded H-bridgemultilevel inverters, which are shown in figure (2).

Figure 2: Control schemes for multilevel inverters

The control schemes for MLI are classified as two types based ontheir switching frequencies, namely low switching frequency mod-ulation scheme and high switching frequency modulation scheme.Low switching frequency control techniques are not much popu-

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lar, due to their lower dynamic response, whereas High frequencyswitching techniques are classified into three types, they are MC-SPWM, SVPWM and SHEPWM. Among these the MCSPWMgives better results which is further classified as PS-SPWM (Phaseshifted SPWM) and LS-SPWM (Level shifted SPWM). The threecategories of level shifted SPWM schemes, namely Phase Dispo-sition (PD), Phase Opposition Disposition (POD) and AlternatePhase Opposition Disposition (APOD) are implemented for mul-tilevel inverter. A general multi carrier based SPWM scheme isshown in figure (3). It consists of two carrier waves (triangular)and a reference wave (sinusoidal).

Figure 3: Multi Carrier Sine Pulse Modulation Scheme

The three phase multilevel inverter is designed with multi car-rier based PWM schemes. Further the results of all these schemesare compared. The three phase 5-level inverter is shown in belowfigure (4). In consists of 3- single phase 5-level inverters, which arecascaded to get a three phase output.

2.1 Control Schemes

For the 5-level inverter, the Phase Disposition technique requires 4-carrier waves and a reference wave. This control method is shownin below figure (5) with 4triangular carriers with one sinusoidalreference waveform. Here all the carrier waves are displaced withsame phase.

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Figure 4: 3-Phase 5-level cascaded H-bridge inverter

Figure 5: Phase Disposition carrier arrangement for 5- Level in-verter

Thus, the number of carrier wave forms required for an ’n’ levelinverter is ’n-1’.

For an ’n’ level inverter is, n = 2N+1, Where N= number offull bridges and n = number of levels.

This control scheme requires n-1 carrier waveforms, for an n-level output. In POD control scheme, there are 4-carrier waveformsare divided in two sets. Upper 2-carriers are set-1, which are insame phase. Lower 2-carriers are set-2, which are arranged with1800 phase shift to upper set-1.

This APOD control scheme requires n-1 carrier waveforms, for

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Figure 6: Phase Opposition Disposition carrier arrangement for 5-Level inverter

an n-level output, these are to be phase disposed by each other with1800 phase shift alternatively as shown in figure (6). In this controlscheme 4-carrier signals are considered as 2-sets. Each carrier signalin the set is 1800 out of phase with other, and the same will repeatfor the remaining sets too.

Figure 7: Alternate Phase Opposition and Disposition carrier ar-rangement for 5- Level inverter

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Figure 8: Injection of 3rd harmonic

Figure 9: 3-phase output voltage waveforms for 5-level inverter withPD

Figure 10: 3-phase output voltage waveforms for 5-level inverterwith POD

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Figure 11: 3-phase output voltage waveforms for 5-level inverterwith APOD

Figure 12: Total Harmonic Distortion of 5-level inverter with PD

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Figure 13: Total Harmonic Distortion of 5-level inverter with POD

Figure 14: Total Harmonic Distortion of 5-level inverter withAPOD

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3 CONCLUSION

In the present work, performance of cascaded five level inverterusing advance pulse width modulation technique has been ana-lyzed. The topology used in this technique reduces the numberof power switches and switching losses. The cascaded H-bridgemultilevel inverter become most popular in the multilevel inverterfamily. Among various PWM techniques multi carrier based PWMtechnique gives less harmonic distortion. In this paper, three dif-ferent advanced PWM schemes named as PD, POD and APODare simulated for 5-level cascaded H-bridge inverter. From the har-monic distortion analysis, it is seen that the Phase Disposition (PD)scheme has less harmonics in its output compared to remainingtwo schemes. From the FFT analysis we get minimum THD of17.17% and the fundamental frequency 50Hz shows performanceof the cascaded hybrid five level inverter with Phase Dispositioncontrol scheme at modulation index of 0.6. The simulation resultsshow that this hybrid five level inverter topology can be appliedfor high power applications. Thus the proposed method will reducethe cost, and also used less number of switches, harmonic reductionand the heat losses.

References

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Cost-Efficiency Based SWT/ Solar Interconnection TopologiesPertaining to Micro Grids. International Journal of Pure andApplied Mathematics, Volume 119 No. 10 2018, 231-245.

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