Advanced Mobile Memory Technology - jedec.org · Post-PC Market Dynamics WW S/P + Tablet Installed...

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Advanced Mobile Memory Technology Advanced Mobile Memory Technology (LPDDR4) (LPDDR4) Mobile Forum 2013 Copyright © 2013 [JungYong Choi, Samsung Semiconductor, Inc.].

Transcript of Advanced Mobile Memory Technology - jedec.org · Post-PC Market Dynamics WW S/P + Tablet Installed...

Page 1: Advanced Mobile Memory Technology - jedec.org · Post-PC Market Dynamics WW S/P + Tablet Installed Base > PC in Q2’13 36% of Email is Now Opened on a Mobile Device Source: KPCG

Advanced Mobile Memory TechnologyAdvanced Mobile Memory Technology(LPDDR4)(LPDDR4)

Mobile Forum 2013

Copyright © 2013 [JungYong Choi, Samsung Semiconductor, Inc.].

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Post-PC Market Dynamics

WW S/P + Tablet Installed Base > PC in Q2’13

36% of Email is Now Opened on a Mobile Device

Source: KPCG Internet Trends

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Where Will Users Spend their Time?

8X

Average Traffic Per Mobile Device Type

Smartphones and Tablets will Soon Drive Similar Data Levels as PCs

2X

7X

4X

8X

Source: Cisco VNI

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What is Driving High Bandwidth - 1

Larger screen size

TabletSmartphone Notebook

10”6” 7” 11”

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What is Driving High Bandwidth - 2

High resolution

3.4X

5.7X

9X

4.5X

HD FHD QXGA WQXGA QSXGA UHD1280/720 1920/1080 2048/1536 2560/1600 2560x2048 3840x2160

1X

3.4X

2.3X

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What is Driving High Bandwidth - 3

Advanced camera functionality

Burst Shot FeatureBurst Shot Feature HDRHDR Augmented RealityAugmented Reality

Panoramic ShotPanoramic Shot

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B/W Requirement is Driven by Graphics

12.8GB/s

19.2GB/s

25.6GB/s

32.0GB/s

LPDDR3E

LPDDR4

LPDDR4E

UD (Ultra Definition)

6.4GB/s

12.8GB/s

LPDDR2

LPDDR3

2013 2014 2015 2016 2017

WQXGA

Tablet application

Source: Samsung

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What is LPDDR4 ?

Low Power DDR4� Evolutionary solution

- Higher “Pin Bandwidth”

vs. Wide IO2: Revolutionary solution- Much wider “Pin Width”

Page 9: Advanced Mobile Memory Technology - jedec.org · Post-PC Market Dynamics WW S/P + Tablet Installed Base > PC in Q2’13 36% of Email is Now Opened on a Mobile Device Source: KPCG

LPDDR4 Key Features

Evolutionary DRAM technology enables 3.2Gbps and faster

Items LPDDR3 LPDDR4 Comments

Speed

CLK400-800MHz

(~1066MHz w/ LP3E)800-1600MHz

2X, Pursues higher

speed

CMD/ADDR DDR SDR -

DQ DDR DDR

Band Width 12.8GB/s+ (2ch) 25.6GB/s+ (2ch) 2XBand Width 12.8GB/s+ (2ch) 25.6GB/s+ (2ch) 2X

Voltage VDD2/VDDQ/VDD1 1.2/1.2/1.8 1.1/1.1/1.8 Total Pd 10%↓

Architecture

[# o Ch & DQs]/ Die x32 2x16 IDD4 20% ↓

# of Bank/channel 8 8 -

Page Size 4K 2K IDD0 10%↓

BL 8 16 32B/ch

Interface

I/O interface HSUL LVSTL 40% I/O power reduction (vs. POD)DQ ODT

No term (VDDQterm option)

VSSQ Term

CA ODT No term VSSterm Optional

Vref External Internal

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Innovative Low Power Interface - LVSTL

LVSTL (Low Voltage Swing Terminated Logic)• High frequency operation with less IO power

consumption• No DC power consumption when driving “low”• Lower Cio, small Xtalk and SSN, because of small swing• Stronger reference plane• Easy voltage scaling

0

2

4

6

8

10

CTT POD_VDDQ LVSTL_VSSQ

DDR3 DDR4 LPDDR4

(mW/Gbps/pin)

32%

40%

VDDQ

VOH

LPDDR4 LVSTL I/O Power by Interfaces

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LPDDR4 3.2Gbps and Beyond

LPDDR4 LVSTL enables stable 3.2Gbps with 70% UI• Initial SI study result shows prominent 4.3Gbps with 60% UI

@ 350mV swing• Further enhancement by reducing trace length, optimizing

channel - SOC/PKG/DRAM and lower Cio

3.2Gbps Data Eye Diagram (ODT=60ohm) 4.3Gbps Data Eye Diagram (ODT=60ohm)

218218140140

Over 70%Over 60%

Source : Samsung memory DRAM Design Team (Feb’13)

Source : Samsung

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Close Collaboration for Timing Closure

Less than half of UI & less than 1/3 of Amplitude• Accurate simulation ���� Board level verification ���� Set level

optimization• Verification/test/FA tools required

LPDDR3-1600Mbps LPDDR3-1866Mbps LPDDR4-3200Mbps

[Real scale]

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Power Efficiency Enhanced Architecture

Core power reduction by adopting advanced low power-friendly architecture

x32

BL8

32Byte

Low Power 32-bit Architecture Access Granularity & Page-size/Ch

x16

BL16

LPDDR4 : Activated Page 2KB(1Kx16)

32Byte

~20% IDD4 reduction ~10% IDD0 reduction

x16

LPDDR3 : Activated Page 4KB(1Kx32)

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Power Efficiency by DRAM Technology

ODT

I/O

CoreDDR4

-40%

mW/GB

More than 40% power efficiency improvement by adopting new architecture, circuits and low VDD

LP3_1600 LP3_1866 LP3_2133 LP3_4Ch LP4 WIO2

12.8GB/s 14.6GB/s 17GB/s 25.6GB/s

Source : Samsung

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Power Saving with Advanced Technology

LPDDR4 consumes much less power than LPDDR3 for performing certain tasks

Time

Power Active

StandbyLPDDR3

Time

Time

Power Active

StandbyLPDDR4

Power(Area)@LP4 << Power@LP3

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New Technology is Just Around the Corner

JEDEC is working diligently to define the LPDDR4 spec to prepare for production in ‘15

‘13 ‘14 ‘15

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2

JEDECVer 0.5 Ver 0.9Consensus

Industry(Est.)

Production

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Thank you !!