Advanced Current Mirrors and Opamps - University of …roman/teaching/530/2004/hando… · ·...

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© D.A. Johns, K. Martin, 1997

rs

University of Toronto

Advanced Current Mirroand Opamps

David Johns and Ken MartinUniversity of Toronto

([email protected])([email protected])

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ors

de mirrore region

t Iin=

L⁄2

--------

L⁄


Wide-Swing Current Mirr

• Used to increase signal swing in casco • Bias drains of Q2 and Q3 close to triod

• set to nominal or max value of

Q5 Q4

Q3 Q2

Q1

W L⁄n

2-------------

Ibias IinVout

Iou

Vbias W

n-----

WW L⁄

W L⁄n 1+( )2

-------------------

I bias I in

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ors

(1)

times smaller

(2)

(3)

(4)

(5)

L⁄ )-----------

Vtn

f Vtn+ ) Veff=


Wide-Swing Current Mirr • Q3 and Q4 act like a single transistor

• has same drain current but

• Similarily

• Puts Q2 and Q3 right at edge of triode

V eff V eff 2 V eff 3

2I D2

µnCox W(----------------------= = =

Q5 n 1+( )2

Veff5 n 1+( )Veff=

Veff1 Veff4 nVeff= =

VG5 VG4 VG1 n 1+( )Veff += = =

VDS2 VDS3 VG5 VGS1– VG5 nVef(–= = =

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ors

(6)

(7)

swing mirror

tting to active region

low outpute tolerated)

ff

I bias


Wide-Swing Current Mirr • Min allowable output voltage

• If

• With typical value of Veff of 0.2 V, wide-can operate down to 0.4 V

• Analyzed with . If varies, semax will ensure transistors remain in

• Setting to nominal will result in impedance during slewing (can often b

Vout Veff1 Veff2+> n 1+( )Ve=

n 1=

Vout 2Veff>

I bias I in= I in

I in

I bias I in

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aller to bias

nts whileff)inimum

ite small)

lengths sincetwice


Design Hints • Usually designer would take sm

Q2 and Q3 slightly larger than minimum

• To save power, bias Q5 with lower currekeeping same current densities (and Ve

• Choose lengths of Q2 and Q3 close to mallowable gate length (since Vds are qu— maximizes freq response

• Choose Q1 and Q4 to have longer gateQ1 often has larger voltages ( perhaps minimum allowable gate length)— Reduces short-channel effects

W L⁄( )5

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rrent Mirror

table

(8)

en drain and

t

ut


Enhanced Output-Impedance Cu

• Use feedback to keep Vds across Q2 s

• Limited by parasitic conductance betwesubstate of Q1

Iou

AVbias

Q1

Q2

Iin

Q3

Rout

Vo

Rout gm1rds1rds1 1 A+( )≅

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dance Mirror

ove-source

out

Q1

Q2


Simplified Enhanced Output-Impe

• Rather than build extra opamps, use ab • Feedback amplifier realized by common

amplifier of Q3 and current source

IIB1IB2Iin

Q3

Q4

Q5

Q6

I B1

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dance Mirrorqual to ,in

(9)

operatesults in

ing —lower supply

rds3

I B2


Simplified Enhanced Output-Impe • Assuming output impedance of is e

loop gain will be , resulting

• Circuit consisting of Q4, Q5, Q6, , andlike a diode-connected transistor — resaccurate matching of to

• Note that shown circuit is NOT wide-swrequires output to be above

I B1

gm3rds3( ) 2⁄

rout

gm1gm3rds1rds2rds3

2--------------------------------------------------≅

I in

I out I in

2V eff V tn+

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t Impedancege swing

nsity — 2Veff

nors

Q1

Q2

80

70

4Ibias

Iout Iin=


Wide-Swing with Enhanced Outpu • Add wide-swing to improve output volta

• Q3 and Q7 biased at 4 times current de

• Requires roughly twice power dissipatio • Might need local compensation capacit

Q3Q4

Q5

Q6

Q7 Q8

10

80

70

101010

Ibias Ibias

4Ibias

Iin 7Ibias≅

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p

Q6

Q10

Q8

Vout

CL


Folded-Cascode Opam

Ibias1

Ibias2

Q1 Q2

Q3 Q4Q11

Q12 Q13 Q5

Q7Q9

Vin

VB1

VB2

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p

acitorore stable

driving

e quite large

g mirrors

slew-rate


Folded-Cascode Opam

• Compensation achieved using load cap • As load increases, opamp slower but m • Useful for driving capacitive loads only • Large output impedance (not useful for

resistive loads) • Single-gain stage but dc gain can still b

(say 1,000 to 3,000) • Shown design makes use of wide-swin • Simplified bias circuit shown • Inclusion of Q12 and Q13 for improved

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p

(10)

(11)

ghly )

(12)

(13)

gmrds2 2⁄


Folded-Cascode Opam

• is output impedance of opamp (rou

• For mid-band freq, capacitor dominates

AV

Vout s( )Vin s( )------------------- gm1ZL s( )= =

AV

gm1rout

1 sroutCL+----------------------------=

rout

AV

gm1

sCL----------≅

ωt

gm1

CL---------=

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p response (if

an output

l noiseof Q5 and Q6t these nodes

t stage


Folded-Cascode Opam • Maximizing gm of input maximizes freq

not limited by second-poles • Choose current of input stage larger th

stage (also maximizes dc gain) • Might go as high as 4:1 ratio • Large input gm results in better therma • Second poles due to nodes at sources • Minimize areas of drains and sources a

with good layout techniques • For high-freq, increase current in outpu

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atege

(14)

r negative

m slew-rateloser to

se biasd benefit)reby


Folded-Cascode Slew-R • If Q2 turned off due to large input volta

• But if , drain of Q1 pulled neapower supply

• Would require a long time to recover fro • Include Q12 (and Q13) to clamp node c

positive power supply • Q12 (and Q13) also dynamically increa

currents during slew-rate limiting (adde • They pull more current through Q11 the

increasing bias current in Q3 and Q4

SRI D4

CL--------=

I bias2 I D3>

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le

with 4:1 ratio

3 (or Q4)th of 300um)

(15)

(16)

(17)

10I B

40 µA=


Folded-Cascode ExampDesign Goals

• +-2.5V power supply and 2mW opamp of current in input stage to output stage

• Set bias current in Q11 to be 1/30 of Q • Channel lengths of 1.6um and max wid

with Veff=0.25 (except input transistors • Load cap = 10pFCircuit Design

I total 2 I D1 I D6+( ) 2 4I B I B+( )= = =

I B I D5 I D6

I total

10----------- 2mW( ) 5 V⁄

10--------------------------------= = = =

I D3 I D4 5I D5 200 µA= = =

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(18)

(19)

iting to

arbitrarily

11 10/1.612 10/1.613 10/1.6


• To find transistor sizing:

rounding to nearest factor of 10 (and lim300um width) results in

• Widths of and were somewhat chosen to equal the width of

• Transconductance of input transistors

I D1 I D2 4I D5 160 µA= = =

WL-----

i

2I Di

µiCoxV effi2

--------------------------=

Q1 300/1.6 Q6 60/1.6 QQ2 300/1.6 Q7 20/1.6 QQ3 300/1.6 Q8 20/1.6 QQ4 300/1.6 Q9 20/1.6Q5 60/1.6 Q10 20/1.6

Q12 Q13

Q11

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(20)

(21)

(22)

(23)

(24)

(25)

A/V

MHz


• Unity-gain frequency

• Slew rate without clamp transistors

• Slew rate with clamp transistors

gm1 2 ID1

µnCox W L⁄( )1 2.4 m= =

ωt

gm1

CL--------- 2.4 8×10 rad/s= = f t⇒ 38=

SRI D4

CL-------- 20 V/µs= =

I D12 I D3+ I bias2 320 µA= =

I D3 30I D11=

I D11 6.6 µA I D12+=

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(26)

(27)

(28)

slew-rate


• Solving above results in

which implies

leading to slew-rate

• More importantly, time to recover from limiting is decreased.

I D11 10.53 µA=

I D3 I D4 30I D11 0.32 mA= = =

SRI D4

CL-------- 32 V/µs= =

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uals inverse

(29)

ty-gain freq of)

pendent of

itor ise and current-

e


Linear Settling Time • Time constant for linear settling time eq

of closed-loop 3dB freq, where

where is feedback factor and is uniamplifier (not including feedback factor

• For 2-stage opamp, is relatively indeload capacitance

• This is NOT the case where load capaccompensation capacitor (folded-cascodmirror opamps)

• Need to find equivalent load capacitanc

ω3dB

ω3dB βωt=

β ωt

ωt

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(30)

(31)

Cload

C2

C p C2+---------------------


Linear Settling TimeC2

C1

Vin Cp CC

β1 s C1 C p+( )[ ]⁄

1 s C1 C p+( )[ ]⁄ 1 sC2( )⁄+-------------------------------------------------------------------

C1 +------------= =

CL CC Cload

C2 C1 C p+( )C1 C p C2+ +---------------------------------+ +=

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pledercent

opamp

(32)

(33)

pF

08 rad/s


Linear Settling Time Exam • Given an

, find settling time for 0.1 paccuracy (i.e. 7 ) for the current-mirror

Solution:

• Equivalent load capacitance

which results in a unity gain freq of

C1 C2 CC Cload 5 pF= = = =C p 0.46 pF=

τ

CL 5 5 5 5 0.46+( )5 5 0.46+ +-----------------------------+ + 12.61= =

ωt

K gm1

CL-------------- 2 1.7 mA/V×

12.61 pF--------------------------------- 2.70 1×= = =

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ple

(34)

(35)

ear settling

limiting time.


Linear Settling Time Exam • Feedback factor given by

causing a first-order time constant

• For 0.1 percent accuracy, we need a lintime of or 54 ns.

• This does not account for any slew-rate

β 55 0.46 5+ +----------------------------- 0.48= =

τ 1βωt--------- 7.8 ns= =

7τ

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s

rejectearities

arities but

ed

FB) circuitryould be fastge

slower since


Fully Differential OpampAdvantages

• Use of fully-differential signals helps tocommon-mode noise and even-order lin— rejection only partial due to non-linemuch better than single-ended designs

• Fast since no extra current mirror need

Disadvantages

• Requires common-mode feedback (CM— sets average output voltage level, sh— adds some capacitance to output sta— might limit output signal swing

• Negative going single-ended slew-rate set by bias current — not dynamic

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e Opamp

Vout

CMFBcircuit

Vcntrl


Fully Differential Folded-Cascod

Ibias

Q1 Q2

Q3 Q4

Q5 Q6

Q8

Q7Q9

Q10

Vin

VB2

VB1

VB3

Q11Q12

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ircuits

t Vcntrlsis

Vout–

B/2 ∆I+


Common-Mode Feedback C

• Balanced signal on Vout does not affec • Does not depend on small-signal analy

IBIB

Vcntrl

IB

IB

Q1

Q2 Q3

Q4

Q5

Q6

Vout+

I B/2 ∆I+I B/2 ∆I–

II B/2 ∆I–

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ircuits

of Cc

Vbias

φ1

φ1


Common-Mode Feedback C

• Useful for switched-capacitor circuits • Caps Cs set nominal dc bias at bottom • Large output signal swing allowed

Vcntrl

CCCC CSCS

Vout+ Vout–φ1

φ1

φ2

φ2 φ2

φ2

Advanced Current Mirrors and Opamps - University of …roman/teaching/530/2004/hando… · ·...

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