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Advanced Analog Integrated Circuits

Operational Transconductance Amplifier III

Bernhard E. BoserUniversity of California, Berkeley

boser@eecs.berkeley.edu

Copyright © 2016 by Bernhard Boser

EE240B – OTA III

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Telescopic OTA

EE240B – OTA III

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Output Swing versus Gain

EE240B – OTA III

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Cascoded Telescopic OTA

EE240B – OTA III

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Realizing Vbias

EE240B – OTA III

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Input Capacitance

EE240B – OTA III

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Neutralization Capacitor Layout

EE240B – OTA III

• Cn• Note that this layout

also minimizes wiring Cgd

• For high-speed applications

Ref: Z. Deng, Thesis, 12/2011

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Improved Swing: Folded Cascode

EE240B – OTA III

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Folded Cascode Noise

EE240B – OTA III

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Advanced Analog Integrated Circuits

Slewing

Bernhard E. BoserUniversity of California, Berkeley

boser@eecs.berkeley.edu

Copyright © 2016 by Bernhard Boser

EE240B – OTA III

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Differential Pair Transconductance

EE240B – OTA III

-ISS

Gm

Vid

Vid

Iod

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Initial Transient

• Differential mode half circuit:

EE240B – OTA III

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Circuit Model During Slewing

EE240B – OTA III

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Initial Transient

EE240B – OTA III

Time

[V]

V*

0

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Linear Settling

EE240B – OTA III

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Settling Time with Slewing

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Design Procedure with Slewing

• For circuits with significant slewing (large input compared to 𝑉∗, small closed-loop gain 𝑐)1. Start by assuming a slewing time, e.g. 50% of ts2. Design and verify that linear settling completes within tlin (apply

only small steps during simulation to avoid slewing)3. Now verify with a full-scale input step and check the actual ratio

of tslew/tlin4. Iterate until the design and verification match

• Typically you get convergence in a few iterations

• Slewing is power efficient– Entire bias current used to charge load– But limits maximum speed

EE240B – OTA III

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Advanced Analog Integrated Circuits

Two Stage OTA

Bernhard E. BoserUniversity of California, Berkeley

boser@eecs.berkeley.edu

Copyright © 2016 by Bernhard Boser

EE240B – OTA III

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Miller Compensated 2-Stage OTA

EE240B – OTA III

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Process Insensitive Realization of Rz

EE240B – OTA III

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Slewing in 2-Stage Miller OTA

EE240B – OTA III

Ref: M. Yavari et al, “An accurate analysis of slew rate for two-stage CMOS opamps,” TCAS-II, March 2005, pp. 164-7.

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Asymmetric Slewing

EE240B – OTA III

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Why is Symmetric Slewing Important?

EE240B – OTA III

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Advanced Analog Integrated Circuits

OTA Design Flow

Bernhard E. BoserUniversity of California, Berkeley

boser@eecs.berkeley.edu

Copyright © 2016 by Bernhard Boser

EE240B – OTA III

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Divide and Conquer Design Flow

• Determine suitable topology based on specifications, e.g.– Single or multi-stage– Gain boosting

• Script based design– Step 1: small-signal

• Make reasonable assumptions (output range, L, a etc.)• Ignore slewing

– Step 2: large-signal• Compute slewing time (use ideal CMFB, biasing), re-optimize• Add CMFB, verify stability and settling

– At this point your design should meet the settling and dynamic range requirements

• Add biasing, check static settling accuracy• Proceed to layout phase: # fingers for transistors, …

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Remedies (Examples)

EE240B – OTA III

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Advanced Analog Integrated Circuits

OTA Examples

Bernhard E. BoserUniversity of California, Berkeley

boser@eecs.berkeley.edu

Copyright © 2016 by Bernhard Boser

EE240B – OTA III

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High Gain

[Bult, JSSC 1992]

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Differential Boosters

[Ahmadi, TCAS-II, 2006]

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Boosted Boosters

[Chiu, JSSC 2004]

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2-Stage OTA with 2 CMFB Loops

[Yang, JSSC 2001]

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2-Stage OTA with Ribner Compensation

[Abo, JSSC 1999]

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Simpler?

[Nauta OTA, Irfansyah, 2014]

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pseudo-differential

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Differential & Low Power

[Groenen, ISSCC 2016]

EE240B – OTA III