Advance Nano Device Lab. Fundamentals of Modern VLSI Devices 2 nd Edition Yuan Taur and Tak H.Ning 0...

Advance Nano Device Lab. 1

Fundamentals of Modern VLSI Devices 2nd EditionYuan Taur and Tak H.Ning

Ch5. CMOS Performance Factors


Ch5.1 Basic CMOS Circuit Elements


CMOS Inverters


CMOS Inverter Transfer Curve


CMOS Inverter Transfer Curve

(5.1)


CMOS Inverter Noise Margin

(5.2)


CMOS Inverter Switching Characteristics

(5.3)


CMOS Inverter Switching Characteristics

(5.4) (5.5)


Switching Energy and Power Dissipation

(5.6)


Quasistatic Assumption

(5.7)

(5.8)


CMOS NAND and NOR Gates


Two-Input CMOS NAND Gate


Noise Margin of NAND Circuits


Layout of a Single Device


Layout of a CMOS Inverter


Layout of a Two-Input CMOS NAND


Ch5.2 Parasitic Elements


Source-Drain Resistance


Accumulation-Layer Resistance and Spreading Resistance

(5.9)


Sheet Resistance

(5.10)


Contact Resistance

(5.11)

(5.12)

(5.13)

(5.14)


Resistance in a Self-Aligned Silicide Technology


Parasitic Capacitances


Junction Capacitance

(5.15)

(5.16)


Overlap Capacitance

(5.17)


Overlap Capacitance

(5.18)

(5.20)

(5.19)


Gate Resistance

(5.21) (5.22)


Gate Resistance

(5.23)

(5.24)

(5.25)


Gate Resistance

(5.26)

(5.27)


Gate Resistance

(5.28)

(5.29)


Interconnect R and C



(5.30)


Interconnect Scaling


Interconnect Resistance

(5.31)

(5.32)

(5.33)


RC Delay of Global Interconnects


Ch5.3 Sensitivity of CMOS Delay to Device Parameters


Propagation Delay of a CMOS Inverter Chain



(5.34)

(5.35)


Bias-Point Trajectories in a Switching Event


Bias-Point Trajectories in a Switching Event

(5.36)

(5.37)

(5.38)


Delay Equation: Switching Resistance, Input and Output Capacitance

(5.39)

(5.40)


Delay Equation: Switching Resistance, Input and Output Capacitance

(5.41)

(5.42)


CMOS Delay Sensitivity to pMOSFET/nMOSFETwidth ratio


Device Width Effect with Respect to Load Capacitance

(5.43)

(5.44)

(5.45)


Sensitivity of Delay to Channel Length


Sensitivity of Delay to Gate Oxide Thickness


Sensitivity of Delay to Power-Supply Voltage and Thresh-old Voltage


Power and Delay Tradeoff

(5.46)


Sensitivity of Delay to Series Resistance


Sensitivity of Delay to Overlap Capacitance


Miller Effect

(5.47)

(5.48)

(5.49)


Sensitivity of Delay to Junction Capacitance


Top and Bottom Switching of a Two-Way NAND Gate


Top and Bottom Switching of a Two-Way NAND Gate

(5.50)


Ch5.4 Performance Factors of Advanced CMOS Devices


Small-Signal Equivalent Circuit

(5.51)


Small-Signal Equivalent Circuit


Unity-Current-Gain Frequency of an Intrinsic MOSFET

(5.52)

(5.53)

(5.54)


Unity-Current-Gain Frequency of an Intrinsic MOSFET

(5.55)

(5.56)

(5.57)


Effect of Transport Parameters on CMOS Performance

(5.58)

(5.59)


Low-Temperature CMOS

Advance Nano Device Lab. Fundamentals of Modern VLSI Devices 2 nd Edition Yuan Taur and Tak H.Ning 0...

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