Taking evolutionary circuit design from experimentation to implementation: some

useful techniques and a silicon demonstration

Adrian Stoica Ricardo S. ZebulumXin Guo* Didier Keymeulen

M. I. Ferguson Vu Duong

2

Outline

• Multi-function NAND/NOR circuit controlled by the power supply voltage (Vdd);– Programmable Logic Cells.

• New methods to ensure that circuits produced by evolution can be fabricated;

• The circuit was fabricated in a 0.5-micron CMOS technology and silicon tests showed good correspondence with the simulations.

3

Methods used in evolutionary design-for-fabrication

• Need for comprehensive testing to ensure that evolved solutions cover the intended operational space;

• Opposing to conventional design, no assumptions on the circuits’ performance outside the points tested during evolution can be reliably made.

4

Methods used in evolutionary design-for-fabrication

• Candidate logic circuits were tested in transient analysis for all possible transitions of combinations of input levels;

• For example, a circuit may respond well as an AND gate to input combinations of levels 0-0, 0-1, 1-0, 1-1. However, it may have a long switching time when inputs 1-1 following 0-0 - and not 1-0 as above, which is not tested in the simple scheme;

• Increased transient analysis: seven input configuration cases opposed to four.

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Methods used in evolutionary design-for-fabrication

• Loading problem: preliminary experiments showed that evolved circuits were not able to drive similar circuits;

• Problem: Input/Output impedance of circuit to be evolved is not known in advance;

• Use of domain knowledge may help: in the case of logic gates we constrain the circuit inputs to connect only to transistor gate terminals, opposed to source or drain: increase input resistive impedance.

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Methods used in evolutionary design-for-fabrication

• Timescale Problem: preliminary evolved logic gates changed their behavior over a "frequency range“, i.e. different responses when tested with slow/DC signals and faster input changing signals;

• Testing in micro-seconds timescale → Transient solutions;

• Testing in seconds timescale → Slow gates;

• Solution: extend the transient analysis duration to avoid transient solutions while keeping the transient analysis step small enough to assess the gate speed.

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Evolved Circuit

• GA parameters: Population of 40 Individuals running for 400 generations

If Vdd = 3.3VIn1In2

Out

If Vdd = 1.8VIn1In2

OutIn1 In2

Out

Vdd

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Circuit Layout

Layout of the multi-functional logic gate. Chip was manufactured using HP 0.5u technology.

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Circuit Response

In1

In2

CLoad = 40p

Time(s)

Ou

t(V

)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

0.30.60.91.21.51.82.12.42.7

3

Time(s)

In1(

V)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

0.20.40.60.8

11.21.41.61.8

2

Time(s)

In2(

V)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

0.20.40.60.8

11.21.41.61.8

2

Time(s)

Inve

rted

Ou

tpu

t(V

)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

0.30.60.91.21.51.82.12.42.7

3

CLoad

In1

In2

CLoad= 40p

Time(s)

Inve

rted

Ou

tpu

t(V

)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

0.20.40.60.8

11.21.41.61.8

2

Time(s)

Ou

tpu

t(V

)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

0.20.40.60.8

11.21.41.61.8

2

Time(s)

In1(

V)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

0.20.40.60.8

11.21.41.61.8

2

Time(s)

In2(

V)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

0.20.40.60.8

11.21.41.61.8

2

CLoad

NAND function (VDD = 3.3V)

In1 In2 Out

0 0

1 1

0 0

1 1

1 1 1

0

In1 In2 Out

NOR function (VDD = 1.8V)

0 0

1 1

1 1 0 0

1

0 0 0

Test Configuration

Test Configuration

Simulation Silicon

In1

In2

Out

In1

In2

Out

10

Remarks

• Stable for 10% variations of Vdd and for temperatures –20oC and 200oC;

• Evolution obtained a creative novel topology more compact than what has been achieved by multiplexing a NAND and a NOR gate (conventional solution using a standard digital library with external voltage control).

• No conventional design is available with the logic function controlled by Vdd;

• Design a 6-transistor NAND/NOR gate controlled by Vdd is a complex task for a human designer;

• To be published in the IEE computing/digital techniques journal on evolvable hardware. To be published in 2004. Andy Tyrrell (editor), London, England.