ADLIB SYNTAX - Springer978-1-4613-2269...Appendix A: ADLIB Syntax 169 A.3 Predeclared Identifiers...

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APPENDIX A ADLIB SYNTAX A.I Low-Level Syntax The basic format of ADLIB programs is patterned closely after Pascal. However, a few differences exist. 1. Identifiers may include the underscore" _", and the use of upper or lower case characters is insignificant. 2. In order to shorten the code, reduce programmer effort, and eliminate transcription errors, a user may "include" files into his or her ADLIB source. The syntax is (starting in column 1): %include "<filename>" "Filename" must be a valid, unambiguous file name. Its syntax may depend on the operating system employed. 3. Comments are delimited by "(>10" and ">lor and may be nested to any depth. (The original version of ADLIB also supported a convention where comments ran from" I" to the end of line.)

Transcript of ADLIB SYNTAX - Springer978-1-4613-2269...Appendix A: ADLIB Syntax 169 A.3 Predeclared Identifiers...

APPENDIX A

ADLIB SYNTAX

A.I Low-Level Syntax

The basic format of ADLIB programs is patterned closely after Pascal. However, a few differences exist.

1. Identifiers may include the underscore" _", and the use of upper or lower case characters is insignificant.

2. In order to shorten the code, reduce programmer effort, and eliminate transcription errors, a user may "include" files into his or her ADLIB source. The syntax is (starting in column 1):

%include "<filename>"

"Filename" must be a valid, unambiguous file name. Its syntax may depend on the operating system employed.

3. Comments are delimited by "(>10" and ">lor and may be nested to any depth. (The original version of ADLIB also supported a convention where comments ran from" I" to the end of line.)

168 Multi-Level Simulation for VLSI

A.2 Summary of Operators

operator operation operand result

Universal: ASSIGN net assignment expression ,net ,timing clause :- assignment any type except file Arithmatic: +(unary) identity integer same -(unary) sign inversion + addition - subtraction

• multiplication DIV integer division integer integer MOD modulus integer / real division integer or real real Relational:

- equality scalar ,string, boolean <> inequality set or pointer < less than scalar or string > greater than <- less or equal scalar or string

-or-set inclusion set

>- greater or scalar or string equal -or-set inclusion set

Logical: NOT negation boolean boolean OR disjunction AND conjunction Sets: IN set membership scalar, and set + union any set type T T - set difference • intersection

Appendix A: ADLIB Syntax 169

A.3 Predeclared Identifiers

The following are the standard, predefined identifiers in ADLIB. A user is free to use or redefine any of them, and implementors are at liberty to include additional predefined constants, types, variables, and subroutines wherever they might be useful. An asterisk (*) indicates those that are in ADLIB, but not Pascal.

1. Constants:

2. Types:

false, true, maxint

bit., boolean, char, integer, real, register., text

3. Nettypes:

semaphore

4. Files:

input, output

5. Functions:

abs, arctan, chr, cos, eof, eoln, exp, ln, odd, ord, pred, round, sin, sqr, sqrt, succ, trunc

6. Procedures: desensitize., detach., get, inhibit.,

new, pack, page, permit., put, read, readln, reset, rewrite, sensitize., stopsim., unpack, write, writeln

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A.4 Reserved Words

An asterisk indicates those that are in ADLIB, but not Pascal. A plus sign indicates DEC-10 Pascal extension.

AND PROCEDURE ARRAY PROGRAM ASSIGN* RECORD BEGIN REPEAT CASE SET CHECK* SUBPROCESS* CLOCK* SYNC* COMPTYPE* THEN CONST TO DEFAULT* TRANSLATOR* DELAY* TRANSMIT* DIV TYPE DO UNTIL DOWNTO UPON* ELSE VAR END WAITFOR* EXTERN WHILE EXTERNAL* WITH FOR FILE FORTRAN+ FORWARD FUNCTION GO TO IF IN INWARD * INTERNAL* LABEL MOD NETTYPE* nil NOT OF OTHERS+ OUTWARD* OR PACKED PHASE*

Appendix A: ADLIB Syntax 171

A.S Backus-Naur Form

To describe the syntax, a modified Backus-Naur Form is used. Non­terminals are denoted by words such as "statement." Terminal symbols are written in CAPITAL LETTERS if they are reserved words, or enclosed in 'single quote marks' if they are not. Since there are two forms of quote character, one may be used to quote the other, i.e. "'" or '''' Each syntactic rule (production) has the form:

S ... E; ... E;

where S is a syntactic entity and E is a syntax expression denoting the set of sentential forms (sequences of symbols) for which S stands. If more than one expression is shown, then each is allowed. Comments are enclosed with "I"" and ""I".

The syntax for ADLIB is as follows:

program ... MODULE 'ident' ';' mod block ... PACKAGE 'ident' ';' mblock '.'

mblock ... mblock_parts ; ... mblock mblock_parts ;

mblock_parts ... use_part ; ... label_decl_part ; ... const_deCpart ; ... type_deCpart ; ... nettype_decLpart ; ... var_decl_part ; ... proc_func_decl_part ; ... compound_stat;

modblock ... modblock_parts ; ... modblock modblock_parts ;

modblock_parts ... use_part ; ... time_unit_stat ; ... const_deCpart ; ... type_deCpart ; - nettype_decLpart ; ... clock_deCpart ; ... comp_deCpart ;

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/*********** USE DECLARATIONS ****************/ use_part - USE use_list ';'

use Jist - 'ident' ; - use Jist ',' 'ident' ;

/*********** TIME UNIT STATEMENT *************/ time_unit_stat - TIME UNITS 'integer' ';' ;

/*********** LABELS ********"'**************/ label_dec1_part - LABEL labeClist ';' labeUist - 'integer' ; - label_list',' 'integer' ;

/****** .. *** CONSTANTS *********"'****"'** .. ****/ conscdeLpart - CONST const_deUist ';' consCdeLlist - 'ide nt' '=' constant; - const_deLlist ';' 'ident' '=' constant;

constant - unsigned_num - '+' unsigned_num ; - '.' unsigned_num - 'ident' ; - '+' 'ident' ; - '.' 'ident' - 'string' ;

unsigned_num - 'integer' ; - 'real' ;

/ ........ "'***.. TYPES ***************************/ type_deLpart - TYPE type_deLlist ';'

type_defJist - 'ident' '=' type; - type_defJist ';' 'ident' '=' type;

type - simple_type ; - structured_type; - pointer_type;

simple_type - scalar_type - subrange_type - 'ident' ;

Appendix A: ADLIB Syntax

scalactype ... '(' idenUist ')' ;

subrange_type ... constant' . .' constant ;

structured_type ... array_type ... record_type ... set_type ... reg_type ;

array _type ... ARRAY '[' indexJist ']' OF type ;

indexJist ... simple_type ; ... index_list ',' simple_type ;

record_type ... RECORD fieldJist END;

field_list ... fixed_part ; ... fixed_part ';' variancpart ; ... variancpart ;

fixed_part ... record_section ; ... fixed_part ';' record_section;

record_section ... ; ... idenUist ':' type

variant-part ... CASE tag_field OF varianUist ;

tag_field ... 'ident' ; ... 'ident' ':' tag_type

tag_type ... 'ident' ;

variant_list ... variancsection ; ... variantJist ';' variancsection ;

variant_section ... case_labeUist ':' '(' fieldJist ')' ; .... , seCtype ... SET OF simple_type;

reg_type ... REGISTER T subrange_type ']' ; ... REGISTER T 'ident' ']' ;

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174 Multi-Level Simulation for VLSI

pointer_type .. ,A, 'ident' ;

, ••••••••• NETTYPES ........................... ,

nettype_decCpart .. NETTYPE nettype_decUist ';'

nettype_decUist .. 'ident' '=' type; - nettype_decUist ';' 'ident' '=' type;

, ......... VARIABLES ....................... , var_dec1_part - VAR var_decUist ';' ;

vacdecUist - var_list ; - var_decUist ';' var_list ;

varJist - idenUist ':' type ;

, ......... CLOCKS ............................. ,

c1ock_deCpart - CLOCK c1ock_deClist ';'

c1ock_deClist - 'ident' '(' 'integer' ',' 'integer' ')' c1ock_def ; - c1ock_deUist ';' 'ident' '(' 'integer' ',' 'integer' ')' c1ock_def ;

c1ock_def - ; - DEFAULT

,......... PROCEDURES'FUNCTIONS ............. , proc_func_dec1_part - PROCEDURE 'ident' formal_parms ';' block ';' ; .. FUNCTION 'ide nt' formal_parms ':' 'ident' ';' block ';' - FUNCTION 'ident' ';' block ';' ;

block .. block_parts ; .. block block_parts ;

block_parts - label_dec1_part ; .. conscdeCpart ; - type_deCpart ; .. var_decl_part ; - proc_func_dec1_part ; - compound_stat; .. EXTERN; .. FORWARD;

Appendix A: ADUB Syntax

... FORTRAN;

formaCparms ... ; ... 'r formaCparm_secJist ')' ;

formal_parm_sec_list ... formaCparm_sec ; ... formaCparm_sec_list ';' formal_parm_sec ;

formal_parm_sec ... idenClist ':' 'ident' ... V AR idenUist ':' 'ident' ;

/********** .. COMPONENT TYPES ................ **** ........................ / comp_deCpart ... COMPTYPE 'ident' formal_parms ';' cblock ';' ; ... TRANSLATOR 'ident' formal_parms ';' cblock ';'

cblock ... cblock_parts ; ... cblock cblock_parts ;

cblock_parts - defaulCpart ; ... net_reCpart ; ... label_decl_part ; ... consCdeCpart ; ... type_deCpart ; ... vacdecl_part ; ... proc_func_decl_part ; ... subp_decCpart ; ... compound_stat;

default_part ... DEFAULT defaulUist ';'

defaulClist ... 'ident' '=' constant; ... defaulUist ';' 'ident' '=' constant;

neCreCpart ... INWARD net_reClist ';' ... OUTWARD necreClist ';' ; ... BOTHWAYS net_reClist ';' ; ... INTERNAL net_reClist ';'

neCreClist ... net_list; ... net_reClist ';' neClist ;

net_list ... idenUist ':' 'ident'

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subp_decUist - subp_decl ; - subp_decUist subp_decl ;

subp_decl - 'ident' ':' TRANSMIT expression qualifier TO variable

timing_clause ';' ; - 'ident' ':' TRANSMIT

expression qualifier TO variable ';' - 'ident' ':' UPON

expression qualifier DO statement ';'

qualifier - checkJist ; - timing_clause ;

timing_clause - DELAY expression - ; /" null timing clause"/ - SYNC; - SYNC 'ident' ; - SYNC 'ident' PHASE expression - SYNC PHASE expression ;

checkJist - CHECK check_net_list

check_neClist - neUd ; - check_net_list ',' neUd ;

/ " "" "" "" "" "" ST ATE ME NT S "" """ "" """ "" '" "" "" "" "" / statement - unlabelled_stat; - 'integer' ':' unlabelled_stat

unlabelled_stat - ; - structured_stat; - assign_stat; - proc_stat ; - goto_stat ; - netassign_stat ; - waitfor_stat ; - detach_stat;

assign_stat - variable_list ':=' expression

Appendix A: ADLIB Syntax

variableJist - variable ; - variableJist ',' variable

variable - 'ident' ; - variable T indexesJist '1' - variable': 'ident' ; _ variable ,A, ;

... variable '[' expression'.: expression '1';

indexes_list - expression ; - indexes_list',' expression ;

expression - simple_exp ; - simple_exp reCoperator simple_exp

reCoperator - '=' - '<>' -to '<' ; .... '<=' .... '>=' .... '>' ... IN ;

simple_exp - term ; - '+' term; - '-' term ; - simple_exp add_operator term

add_operator - '+' .... '-' ; -OR;

term - factor; - term mulCoperator factor

muicoperator - '*' .... '/' ;

- DIV ; -MOD -AND - 'II' ;

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factor .. variable; .. '(' expression ')'

Multi-Level Simulation for VLSI

.. 'ident' '(' expressionJist ')' ~ '[' ']' ; .. '[' elemenUist ')' .. NOT factor .. 'string' ; .. nil ; .. unsigned_num ;

elemenUist .. element ; .. elementJist ',' element ;

element .. expression ; .. expression ' . .' expression

proc_stat .. 'ident' ; .. 'ident' '(' expressionJist ')'

goto_stat .. GOTO 'integer' ;

structured_stat .. compound_stat; .. cond_stat ; .. repetitive_stat; .. with_stat;

compound_stat .. BEGIN statemenUist END

statemenClist .. statement; .. statementJist ';' statement;

cond_stat .. IF expression THEN statement .. IF expression THEN statement ELSE statement .. CASE expression OF case_elemenUist otherwise3lause END

case_elementJist .. case_element; .. case_element_list ';' case_element;

case_element .. ; .. case_label_list ':' statement

caseJabeUist .. constant; .. caseJabeUist ',' constant;

otherwise_clause .. ; .. OTHERWISE statement ;

Appendix A: ADLIB Syntax

repetitive_stat - WHILE expression DO statement ; - REPEAT statementJist UNTIL expression ; - FOR 'ident' ':=' expression TO expression DO statement - FOR 'ident' ':=' expression DOWNTO expression DO statement

rec_var_list - variable; - rec_var_Iist ',' variable;

ne tassign_s ta t - ASSIGN indexes_list TO neUd_list timing_clause; - ASSIGN indexes_list TO neUd_list; - ASSIGN TRANSPORT indexes_list TO neUd_list timing_clause - ASSIGN TRANSPORT indexes_list TO neUd_Iist ;

waitfor_stat - W AITFOR check_list - W AITFOR timing_clause ; - W AITFOR expression qualifier

detach_stat - DETACH ;

/******"***"* MISCELLANEOUS *"***********"**"*/ idenUist - 'ident' ; - idenUist ',' 'ident' ;

neUd_list - neUd ; - neUdJist ',' neUd

neUd - 'ident' ;

expression_list - expression io_length ; - expression_list ',' expression io_length ;

io_length - ; - ':' 'integer' ; - ':' 'integer' ':' 'integer'

A.6 Comments on Syntax

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In the syntax for "timing_clause," if no expression is present, the expression "0" is assumed. If no 'ident' is present after SYNC, the default clock is used.

The DEC-lO version has a sightly different syntax for "case_element." Instead of OTHERWISE, it uses "OTHERS:." Its syntax for "program"

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allows an asterisk to appear after file names, which indicate that the file should not be rewritten. It also has a slightly different syntax for parameters to function parameters. The original version of ADLIB also requires names for subprocesses and supports only check lists for controlling them.

APPENDIX B

PACKAGES

One objective indesigning ADLIB was that the language itself should remain small, but at the same time be easily extensible, both by the user or the CAD implementor. In the case of the implementor, this is accomplished by supplying additional predeclared data types and subroutines, which is painless to the user because it does not imply any syntax changes or extensions, and does not require the user to learn about features not relevant to his or her own area of work.

Users, on the other hand, can enhance the software environment in another way by creating packages. This appendix describes one of such package, called rndpak, which provides a set of random number generators with various distributions and other facilities. In order to access a package, the user must the add the headings of its subroutines into his or her source program. This can accomplished with the USE statement, as in:

USE regpack;

B.I Rndpak

Rndpak is a set of random number generators useful for stochastic simulations. They are listed below.

1. PROCEDURE rndset(newseed : integer);

Rndset resets the internal random number generator mechanism using newseed. It is only necessary to call rndset if multiple simulation runs are to be performed using different random inputs.

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2. FUNCTION rndO 1 : real;

Rnd01 produces a random number between 0.0 and 1.0 by using one random number generator to scramble the results of another, thereby lowering the autocorrelation.

3. FUNCTION rndnexp (lambda : real) : real;

Rndnexp returns a number drawn from the negative exponential distribution with mean and standard deviation 1.0/lambda (lambda must be positive).

4. FUNCTION rnderlang(lambda : real; k : integer) : real;

Rnderlang returns a number drawn from the Erlang distribution with mean (lIlambda) and standard deviation lI(sqrt(k)*lambda). (Minimum k=1, higher k makes for a tighter distribution.)

5. FUNCTION rndnormal (mean, variance : real) : real;

Rndnormal returns a number drawn from the Normal distribution with the mean and variance specified. The distribution is approximated by summing 32 uniformly distributed random values.

6. FUNCTION rndint (low , high: integer) : integer;

Rndint produces an integer evenly distributed among the numbers from low to and including high.

7. FUNCTION rnddraw(p : real) : boolean;

Rnddraw returns true with probability p.

8. FUNCTION rnduniform(low, high: real) : real;

Rnduniform produces a random real number uniformly distributed between low and high. (Note that the probability of returning a value exactly equal to low or high is vanishingly small.)

Data Analysis Facility

9. PROCEDURE rndhisto(data : real; command: integer);

Rndhisto collects, analyzes and plots a random variable. It produces a histogram automatically scaled to the width of the paper. Maximum number of bins=200. Its commands are as follows:

o 1 2 3 4 5 6 7 8

Appendix B: Packages

reset all tallies, and data values set high limit to data (default = 10.0) set low limit to data (default = -10.0)

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set number of bins to "data (default = 20) accept data as a point to be plotted plot results in file output plot results at tty set paper width to data reset all parameters to default values

The print out includes: the number of points, the value of the highest and lowest points, the number of points out of range high and low (if any), the mean, variance, sum, standard deviation, sum of squares, and the auto covariance and autocorrelation of adjacent terms. The following trivial program shows an example of its use:

PROGRAM x; VAR i : integer; FUNCTION rnderlang (lambda :real;k :integer) :real; EXTERN; PROCEDURE rndhisto (data :real ;command: integer) ;EXTERN;

BEGIN FOR i := 1 TO 1000 DO

rndhisto (rnderlang (3.0,4),4); rndhisto (0.0,5); END.

This produces the output:

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-9.50000 -8.50000 -7.50000 -6.50000 -5.50000 -4.50000 -3.50000 -2.50000 -1.50000

0> 0> 0> 0> 0> 0> 0> 0> 0>

Multi-Level Simulation for VLSI

-5.00000E-01 7> 5.00000E-01 134>XXXXXXXXXXXXXX 1.50000 297>XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 2.50000 3.50000 4.50000 5.50000 6.50000 7.50000 8.50000 9.50000

NUM POINT=

262>XXXXXXXXXXXXXXXXXXXXXXXXXXXXX 154>XXXXXXXXXXXXXXXXX 82>XXXXXXXXX 32>XXX 17>X 8>X 6> 0>

1000 LOWVAL= 1.826466932E-01 HIGHVALUE= 1. 178417652E+0 1 1 POINT(S) WERE TOO HIGH 0 POINT(S) WERE TOO LOW MEAN= 2.976368099 VARIANCE= 2.365632474 SUM= 2.976368099E+03 SUMSQ= 1.122203394E+04 SUM PROD= 8.85480 1416E+03 STD DEV= 1.538061276 AUTO COVARIANCE=-6.792426109E-03 AUTOCORRELATION=-2.871293902E-03

APPENDIX C

TRANSLATOR EXAMPLES

As discussed in Chapter 4, multi-level simulation between components using different net types to represent the same information can be accomplished with the use of translators. This appendix contains two examples of such translators, the first one being the one used in Chapter 4 to convert between an alu function and a group of independent nets, and the second one second being two-value logic into multi-value logic converter.

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TRANSLATOR functo10g; INWARD f :a1u_function; OUTWARD is ,i4 ,i3 :logtype;

PROCEDURE update (iSva1 ,i4va1,i3va1 :logtype); BEGIN ASSIGN iSva1 TO is; ASSIGN i4va1 TO i4; ASSIGN i3va1 TO i3; END;

SUBPROCESS UPON true CHECK f DO

CASE f OF

BEGIN END;

fadd: fsubr: fsubs: flor: fand: fnotrs: fexor: fexnor: END;

update (10 ,10 ,10); upda te (10 ,10 ,hi); upda te (10 ,hi ,10); upda te (10 ,hi ,hi); upda te (hi ,10 ,10); update (hi ,10 ,hi); update (hi ,hi ,10); upda te (hi ,hi ,hi) ;

Appendix C: Translator Examples

NETTYPE multinet .. (x, u, d, 1, h, s);

(*converts two value logic to multi-value.) (* when the input net changes, it first assigns ** the going up (u) or going down (d) value. ** When the input net stablizes, it assigns ** the high (h) or low (1) values*) TRANSLATOR tomulti; INWARD

a : boolnet; EXTERNAL

out multinet; INTERNAL

int boolnet; SUBPROCESS

checker : UPON a .. int CHECK int DO

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IF a THEN ASSIGN h TO out ELSE assign 1 TO out; BEGIN ASSIGN initval TO out; WAITFOR DELAY 0.0; permit (checker); sensitize (a); WHILE true DO BEGIN

DETACH; IF a THEN ASSIGN u TO out DELAY 0.0 ELSE ASSIGN d TO out DELAY 0.0; ASSIGN a TO int DELAY 1.0; END;

END;

APPENDIX D

SYMBOLIC SIMULATION SUPPORT ROUTINES

The following routines are used to support the symbolic simulation capabilities, as described in Chapter 5.

(* dynamic allocation and garbage collection *) PROCEDURE newe(VAR e:eptr);

BEGIN IF fsh = nil THEN NEW(e) ELSE

BEGIN e:=fsh; fsh :=e" .left END;

WITH e" DO BEGIN e" .operator :=boole; e" .left :=nil; e" .right :=nil END

END;

PROCEDURE disposee (VAR e :eptr ) ; BEGIN e" .left :=fsh; fsh:=e; e :=nil; END;

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PROCEDURE vari (n :alph) :eptr; VAR e:eptr; BEGIN newe(e) ; WITH e~ DO

BEGIN e~ .operator :-xvar; eA.name:=n; END;

vari:=e; END;

(* return constant boolean symbolic expression, true or false *) FUNCTION bc (bval :BOOLEAN) :eptr ;

BEGIN IF bval THEN bc:-symbtrue ELSE bc:=symbfalse END;

(* return constant integer symbolic expression with given value *) FUNCTION ic (i val :INTEGER) :eptr ;

VAR e:eptr; BEGIN IF (symplo <= ival) AND (ival <= symbhi) THEN e:=symbconst[ivalJ ELSE

BEGIN newe (e); eA.operator:ainteg; eA.i :=ival END;

ic:=e END;

(* return true if symbolic expression is true *) FUNCTION etrue (e :eptr) :BOOLEAN;

BEGIN IF e=nil THEN etrue:=false ELSE IF e A .operator=boole THEN etrue :=e~.b ELSE etrue:=false END;

(* return false if symbolic expression is false *) FUNCTION efalse (e :eptr) :BOOLEAN;

BEGIN IF e=nil THEN efalse:=false

Appendix D: Symbolic Simulation Routines

ELSE IF e~.operator-boole THEN efalse:=NOT e~.b ELSE efalse:-false END;

(* return true if symbolic expression has value of 1 *) FUNCTION eone (e :eptr ) :BOOLEAN ;

BEGIN IF e=nil THEN eone:afalse ELSE IF e~ .operatorainteg THEN eone :-e~ .I= 1 ELSE eone:-false END;

(*. return true if symbolic expression has value of 0 *) FUNCTION ezero (e :eptr ) :BOOLEAN:

BEGIN IF e=nil THEN ezero:-false ELSE IF e~ .operatorainteg THEN ezero :-e~ .i-O ELSE ezero:-false END;

(* return true if symbolic expression is a constant *) FUNCTION econst (e :eptr ) :BOOLEAN;

BEGIN IF e-nil THEN econst:afalse ELSE econst:-(e~.operator-boole) OR (e~.operator=integ)

END;

(* return true if two symbolic expressions are identical *) FUNCTION esame (e 1,e2 :eptr) :BOOLEAN ;

BEGIN IF (e1=nil) OR (e2-nil) THEN esame:=e1=e2 ELSE IF e1~.operator.e2~.operator THEN

CASE e1A .operator OF boole :esame:_e1A .b_e2A.b; integ :esame:_e1A .i_e2A.i; xvar: esame :-e 1A .name_e2A .name; xodd ,xord ,xnot ,xand ,xor ,times ,xdev ,xmod ,plus ,nega te ,

minus ,equal ,ntequal ,greater ,less .grequal .lsequal: esame:- (e1A .left_e2A .left) and (e 1A .right=e2A .right)

END ELSE esame:=false END;

(* simplify an expression *)

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PROCBDURB simplify(var e :eptr); VAR l,r ,temp :eptr;

ti :INTBGBR ; tb :BOOLBAN ; op:ops;

BBGIN IF eonil THBN

BEGIN 1 :-e" _left; r :-e" .right; op :-e" .operator; IF op IN binaryops THEN

BEGIN IF econst (1) AND econst(r) THEN

BEGIN disposee (e); CASE op OF

xand: tb:=l".b AND r" .b; xor: tb :=l".b OR r".b; times: ti :=l".i * r".i; xdiv: ti:=l".i DIV r".i; xmod: ti :;ll".i MOD r".i; plus: ti:=l".i + r" .i; minus: ti :=l".i - r".i; equal: tb :=l".i = r".i; ntequal: tb :=l".i <> r".i; greater: tb:=l".i > r".1; less: tb :=l".i < r".1; grequal: tb :=l".i >= r".i; lsequal: tb :=l".i <= r".i END;

IF op IN booleanops THEN BEGIN IF tb THEN e:=symbtrue ELSE e:=symbfalse END

ELSE BEGIN

END

IF (symblo <= til AND (ti <= symbhil THEN e:=symbconst[ti] ELSE e :=ic (ti l END

ELSE (* reducible binaryop? *l BEGIN IF etrue (l l THEN CASE op OF

Appendix D: Symbolic Simulation Routines

xand ,equal ,lsequal: BEGIN disposee (e); e :::r END; xor ,grequal :BEGIN disposee (e); e :=symbtrue END; less :BEGIN disposee (e); e :::symbfalse END; times ,xdiv ,xmod ,plus ,minus ,ntequal,greater: END

ELSE IF etrue(r) THEN CASE op OF xand ,equal ,grequal: BEGIN disposee(e); e:=l END; xor ,lsequal: BEGIN disposee (e); e :asymbtrue END; greater :BEGIN disposee (e); e :=symbfalse END; times ,xdi v ,xmod ,plus ,minus ,n tequal,less: END

ELSE IF efalse(l) THEN CASE op OF xand,greater: BEGIN disposee(e)j e:=symbfalse END; lsequal :BEGIN disposee (e); e :=symbtrue END; xor ,ntequal ,less :BEGIN disposee (e); e :=r END; times ,xdiv ,xmod ,plus ,minus ,equal ,grequal: END

ELSE IF efalse(r) THEN CASE op OF xand ,less :BEGIN disposee (e); e :=symbfalse END; grequal :BEGIN disposee (e); e :::1 END; times ,xdiv ,xmod ,plus ,minus ,equal ,lsequal: END

ELSE IF ezero(l) THEN CASE op OF times :BEGIN disposee (e); e :::symbconst [0] END; plus :BEGIN dispolsee (e); e :::r END; minus :BEGIN e~ .operator :::negate; e~ .left :::nil END; xand ,xor ,xdi v ,xmod ,equal ,n tequal ,grea ter ,less,

grequal,lsequal: END ELSE IF ezero(r) THEN CASE op OF

times:BEGIN disposee(e); e:::symbconst[O] END; plus ,minus :BEGIN disposee (e); e :::1 END; xand ,x or ,xdiv ,xmod ,equal ,ntequal ,greater,

less ,grequal ,lsequal: END ELSE IF eone(l) THEN

BEGIN IF op=times THEN BEGIN disposee (e); e :::r END END

ELSE IF eone(r) THEN CASE op OF times,xdiv:BEGIN disposee(e); e:::l; END; xmod :BEGIN disposee (e); e :=symbconst [0] END; xand ,xor ,plus ,minus ,equal ,ntequal ,grea ter,

less ,grequal ,lsequal: END ELSE IF esame (1 ,r) THEN

BEGIN

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IF (op=xand) OR (op=xor) THEN BEGIN disposee(e); e:::l END ELSE I? op In [greater,less,ntequal] THEN

BEGIN disposee (e); e :=syrr.bfalse END ELSE IF op In [greq\lal,lseq\lal ,equal] THEN

194 Multi-Level Simulation for VLSI

BEGIN disposee (e); e :=symbtrue END ELSE IF op=minus THEN BEGIN disposee(e); e:=symbconst[O] END END

ELSE IF l<>nil THEN IF r<>nil THEN

BEGIN IF «1 ~ .operator=xnot }AND esame(l A .right ,r)} OR

«r~ .operator=xnot }AND esame(r~ .right ,l)} THEN CASE op OF

xand :BEGIN disposee (e); e :zsymbfalse END; xor :BEGIN disposee (e); e :=symbtrue END; greater:BEGIN disposee(e}; e:zl END; times ,xdiv ,xmod ,plus: END

ELSE IF «1 ~ .operatorznegate)AND esame(l ~ .right,r» OR «r~ .operatorznegate )AND esame(r~ .right ,1» THEN

IF op=plus THEN BEGIN disposee(e); e:=symbconst[O] END END

END END

ELSE (* unary operations *) BEGIN IF econst(r) THEN

BEGIN disposee (e ) ; CASE op OF

xodd :tb :=odd (r~ .i); xnot:tb:=NOT r~ .b; negate :ti :=-r~ .i; xord :ti :=r~ .i; END;

IF op IN booleanops THEN IF tb THEN e:=symbtrue ELSE e:=symbfalse

ELSE IF (symblo <= ti)AND(ti <=symbhi) THEN e:=symbconst[ti] ELSE e :=ic (ti) END

ELSE BEGIN IF op=xnot THEN

IF r<>nil THEN IF r~ .operator=xnot THEN BEGIN disposee (e); e :=rA .right END;

IF op=negate THEN IF r<>nil TEEN

IF rA .operator=negate THEN BEGIN disposee (e); e :=r A .right END END

Appendix D: Symbolic Simulation Routines 195

END; IF e<>nil THEN

IF C Ce A .operator IN [binaryops+unaryops] )AND Ce A .rightanil) lOR CCe" .operator IN[binaryops] )ANDCe" .leftanil» THEN

END END;

diposee(e)

C* two routines used to create new copies of symbolic expressions *) FUNCTION bx Cop :ops; l.r :eptr ) :eptr ;

VAR e:eptr; BEGIN neweCe); WITH e" DO

BEGIN e A .opera tor :-op; e" .left:-l; e" .right :ar; END;

simplify(e); bx:=e END;

FUNCTION ux Cop :ops; r :eptr ) :eptr ; VAR e:eptr; BEGIN neweCe); WITH e" DO

BEGIN e" .operator :-op; e" .left :anil; e" .right:-r; END;

simp lify (e ); ux:=e END;

C* assign one symbolic expression to another *) PROCEDURE assignsymbCenew:eptr;var eold:symbolicnet;pd:integer);

VAR e:eptr; BEGIN e:=eold; IF not esameCenew,e) THEN ASSIGN enew TO eold DELAY pd END;

APPENDIX E

BIBLIOGRAPHY

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[AGR82] Agrawal, V.D., "Synchronous Path Analysis in MOS Circuit Simulation," Proceedings of the 19th Design Automation Conference, Minneapolis, 1980, pp. 626-633.

[ANL79] Anlauff, P. Funk, and P. Meinen, "PHPL - A New Computer Hardware Description Language for Modular Description of Logic and Timing, "Proceedings of the 4th International Symposium on Computer Hardware Description Languages, Palo Alto, Ca., Oct., 1979, pp. 124-130.

[ANT78] Antoniadis, D. A., S. E. Hansen, and R. W. Dutton, Suprem I1 -A Program for IC Process Modeling and Simulation, Tech. Report Number 5019-2, SEL 78-020, Stanford Electronics Lab., June 1978.

[BAR77] Barbacci, M. et al., "An Architectural Research Facility - ISP, Descriptions, Simulations and Data Collection," Proceedings of AFI PS NCC, 1977, pp. 161-173.

[BAR79] Barbacci, M. R., G. E. Barnes, R. G. Cattell, D. P. Siewiorek, The ISPS Computer Description Language, CMU-CS-79-137, Departments

198 Multi-Level Simulation for VLSI

of Computer Science and Electrical Engineering, Carnegie-Mellon University, 16 August 1979.

[BAR79-2] Barbacci, M. R., W. B. Dietz, L. J. Szewerenko, "Specification, Evaluation, and Validation of Computer Architectures Using Instruction Set Procesor Descriptions," Proceedings of the 4th International Symposium on Computer Hardware Description Languages, Palo Alto Ca., Oct., 1979, pp. 14-20.

[BA Y79] Bayegan, H. M., O. Baadsvik, O. Kirkaune, "An Interactive Graphic High Level Language for Hardware Design," Proceedings of the 4th International Symposium on Computer Hardware Description Languages, Palo Alto, Ca., Oct. 1979, pp. 184-190.

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[BIR73] Birtwistle, G. M., O-J Dahl, B. Myhrhaug, K. Nygaard, SIMULA BEGIN, Auerbach Publishers, Inc., Philadelphia, Pa. 1973.

[BOS77] Bose, A. K., S. A. Szygenda, "Detection of Static and Dynamic Hazards in Logic Nets," Proceedings of the 14th Annual Design Automation Conference, New Orleans, La. June 1977, pp. 220-224.

[BRE76] Breuer, M. A., A. D. Friedman, Diagnosis Reliable Design of Digital Systems, Computer Science Press, Inc., Woodland Hills, Ca, 1976.

[BRY81] Bryant, R.E., "MOSSIM: A Switch-Level Simulator for MOS LSI", Proceedings of the Eighteenth Design Automation Conference, July 1981, pp.786-790.

[CAS78] Case, G. R., J. D. Stauffer, "Salogs-IV A Program to Perform Logic Simulation and Fault Diagnosis," Proceedings of the 15th Design Automation Conference, Las Vegas, June 1978, pp. 392-397.

[CHA76] Chappell, S. G., P. R. Menon, J. F. Pellegrin, A. Schowe, "Functioinal Simulation in the Lamp System," Proceedings of the 13th Design Automation Conference, San Francisco, 1976, pp. 42-47.

[CHE78] Chen, A. C., J. E. Coffman, "Multi-Sim, A. Dynamic Multi­Level Simulator," Proceedings of the 15th Design Automation Conference,

Appendix E: Bibliography 199

Las Vegas, June 1978, pp. 386-391.

[CHU65] Chu, C. Y., "An ALGOL-like Computer Design Language," Communications of the ACM, Vol. 8, No. 10, Oct. 1965, pp. 607-615.

[CHU74] Chu, Yaohan, "Introducing COL," Computer, December 1974.

[COE83] Coelho, D., and W.M.VanCleemput, "HELIX, A Tool for Multi-Level Simulation of VLSI Systems," International Semi-Custom IC Conference, London, November, 1983.

[COE83] Coelho, D., "HELIX, A Tool for Multi-Level Simulation of VLSI Systems," International Semi-Custom IC Conference,November,I983.

[COE84] Coelho, D., "Behavioral Simulation of LSI and VLSI Circuits," VLSI Design Magazine, February, 1984.

[COE84] Coelho, D., and C. Neti, "Timing Verification Using a General Behavioral Simulator," ICCD, October, 1984.

[COE85] Coelho, D., "Implementation Tradeoffs in High Level Simulators and How They Affect the User," ADEE West, March 1985.

[COE85] Coelho, D., "High--Level Design Using HELIX," ACM Computer Science Conference, March 1985

[COE85] Coelho, D., "Integrating the Electronic Development Environment with a Multi--Level Behavioral Simulator," 1985 Summer Computer Simulation Conference, July 1985

[COE85] Coelho, D., "Hardware Design Standards - A CAD Vendors Perspective," Computer Standards Conference, May 1986 future directions

[COP74] Coplaner, H. D., and J. A. Janhu, "Top Down Approach to LSI System Design." Computer Design Vol. 13, No.8, Aug. 1974, pp. 143-148.

[COR79] Cory, W. E., J. R. Duley, W. M. vanCleemput, An Introduction to the DDL-P Language, Computer Systems Lab. Technical Report No. 163, Stanford University, Stanford, Ca. March 1979.

[COR79-2] Cory, W. E., Syndia User's Guide Systems Lab. Technical Report No. 176, Stanford University, Stanford, Ca. August 1979.

200 Multi-Level Simulation for VLSI

[COR80] Cory, W.E. and W.M.vanCleemput. "Developments in Verification of Design Correctness - A Tutorial". In Rex Fice (editor), Tutorial - VLSI Support Technologies: Computer-Aided Design. Testing and Packaging. pages 169-177. IEEE Computer Society Press, Los Alamitos, CA, 1982. Reprinted from Proceedings of the 17th Design Automation Conference, pages 156-164, IEEE and ACM, Minneapolis, June 1980.

[COR81], Cory, W.E., "Symbolic Simulation for Functional Verification with ADLIB and SDL," In Proceedings of the 18th Design Automation Conference, pages 82-89. IEEE and ACM, Nashville, June 1981. for chapter 5

[CRA79] Crawford, J. D., A. R. Newton, D. O. Pederson, G. R. Boyle, "A Unified Hardware Description Language for CAD Programs," Proceedings of the 4th International Symposium on Computer Hardware Description Languages, Palo Alto, Ca., Oct., 1979, pp. 151-154.

[DAH70] Dahl, O. J., B. Myhrhaug and K. Nygaard, Simula Common Base Language, Norwegian Computing Center, Oslo, Publication S-22, Oct. 1970.

[DEM79] Demou, H., G. Arnout, DIANA - Principles of Operation, Lisco Inc., Technical Report Number D04, Belgium 1979.

[DIE75] Dietmeyer, D. L., and J. R. Duley, "Register Transfer Languages and Their Translation," in Digital System Design Automation, edited by M. A. Breuer, Computer Science Press, Inc., Woodland Hills, Ca., 1975, pp. 117-218.

[DIJ75] Dijkstra, E., "Guarded Commands, Nondeterminacy and Formal Derivation of Programs," Communications of the ACM, 18(8), August, 1975.

[DUN83] Dunlugol, D, H.J. Derlam, P. Stivers, G.G. Schrooten, "Local Relaxation Algorithms for Event-Driven SImulation of MOS Networks Including Assignable Delay Modelling," IEEE Transactions on CAD, Vol CAD-2 Number 3, July, 1983.

[FAL64] Falkoff, A. D., K. E. Iverson, E. H. Sussenguth, "A Formal Description of the SYSTEM/360," IBM Systems Journal, Volume 3, Number 3, 1964, pp. 198-262.

[GAR77] Gardner, Robert 1., "Multi-Level Modeling in SARA,"

Appendix E: Bibliography 201

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[GEH86] Gehani, N. H. and W. D. Roome., "Concurrent C," To appear in Software--Practice & Experience.

[G0079] Goodel, R., "An ISPS Microassembler," Proceedings of the 4th International Symposium on Computer Hardware Description Languages, Palo Alto, Ca., Oct. 1979, pp. 62-67.

[HAN77] Hansen, Per Brinch, The Architecture of Concurrent Programs, Prentice-Hall, Englewood Cliffs, New Jersey, 1977.

[HP] Hewlett-Packard, A Pocket Guide to Hewlett-Packard Computers, Palo Alto, Ca.

[HIL79-1] Hill, Dwight D. and W. M. vanCleemput, "SABLE: A Tool for Generating Structured, Multi-level Simulations," Proceedings of the 16th Design Automation Conference, San Diego, Ca., June 1979.

[HIL79-2] Hill, D. D., ADLIB - SABLE User's Guide, Computer Systems Lab, Technical Report No. 177, Stanford Univ., Stanford, 1979.

[HIL79-3] Hill, D. D., "ADLIB: A Modular, Strongly-Typed Computer Design Language," Proceedings of the 4th International Symposium on Computer Hardware Description Languages, Palo Alto, Ca., Oct. 1979, pp.75-81.

[HILSO] Hill, D. D., Language and Environment for Multi-Level Simulation, Ph. D. Thesis, Stanford University, 1980. (available through University Microfilms ).

[HIL 73] Hill, Frederick J. and Gerald R. Peterson, Digital System Hardware Organization and Design, John Wiley and Sons, 1973.

[HIL79] Hill, F. J., Z. Navabi, "Extending Second Generation AHPL Software to Accommodate AHPL III," Proceedings of the 4th I nternational Symposium on C amputer Hardware Description Languages, Palo Alto, Ca., Oct. 1979, pp. 47-53.

[173] Intel, 8008 8 Bit Parallel CPU Users Manual, Santa Clara, Ca., 1973.

[JEN74] Jensen, K. and N. Wirth, Pascal User Manual and Report,

202 Multi-Level Simulation for VLSI

Springer-Verlag, New York, 1974.

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[KIN75] King, J. C., "A New Approach to Program Testing," ACM Sigplan Notices, 10(6):228-233, June, 1975.

[KIN76] King, J. C., "Symbolic Execution in Program Testing," Communications of the ACM, 19(7):385-394, July, 1976.

[KIV69] Kiviat, P. J., R. Villanueva, and H. Markowitz, The SIMSCRIPT II Programming Language, Prentice Hall, Inc., Englewood Cliffs, N.J. 1969.

[KOH70] Kohavi, Zvi, Switching and Finite Automata Theory, McGraw­Hill Book Company, San Francisco, Ca., 1970.

[KUS76] Kusik, .R and P. Wesley, "Hierarchical Logic Simulation for Digital Systems Development," Proceedings of Electrol76, Boston, Mass,May 1976,pp 26.3.1-26.3.8.

[LAN79] Langlet, T., private communication, Burroughs Corporation, Mission Viejo, Ca. 1979.

[LOS75] Losleben, P., Design Validation in Hierarchical Systems, Proceedings of the 12th Design Automation Conference, Boston, 1975, pp.431-438.

[MCW78] McWilliams, T. M. and L. C. Widdoes, SCALD: Structured Computer-Aided Logic Design, Digital Systems Lab. Tech. Report No. 152, Stanford U., March 1978.

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[MCW80] McWilliams, T. M., "Verification of Timing Constraints on Large Digital Systems," Proceedings of the 17th DAC, Minneapolis, Minn, June 1980, pp 139-147.

[MEL84] Melamed, B., R. J. T. Morris, "Visual Simulation: The Performance Analysis Workstation," Computer, August, 1985, pp. 87-94.

Appendix E: Bibliography 203

[NAG73] Nagel, L. W. and D. O. Pedersim, SPICE rSimulatoin Program with Integrated Circuit Emphasis, Berkeley, Calif. University of California, Electronics Research Laboratory, Memorandum ERL-M382, April 12, 1973.

[NEW78] Newton, R. A., The Simulation of LSI Circuits, University of Cal., Berkeley, Memo No. UCB/ERL M78/52, July 1978.

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[PAR79] Parker, A., D. E. Thomas, S. Crocker, R. G. G. Cattell, "ISPS: A Retrospective View," Proceedings of the 4th International Symposium on Computer Hardware Description Languages, Palo Alto Ca., Oct. 1979, pp.21-27.

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[ROS75] Rose, C. W. and M. Albarran, "Modeling and Design Description of Hierarchical Hardware / Software Systems," Proceedings of the 12th Design Automation Conference, Boston, 1975, pp. 421-430.

[SCH74] Schriber, T. J., Simulation Using GPSS, John Wiley & Sons, New York,1974.

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[SZY77] Szygenda, S. A., A. A. Lekkos, "Integrated Techniques for Functional and Gate-Level Digital Logic Simulation," Proceedings of the 10th Design Automation Workshop, Portland, Oregon, June 1973, pp. 159-172.

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[TAN81] Tanenbaum, A., Computer Networks, Prentice Hall, 1981.

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[TOK78] Takara, M., M. Sato, M. Ishigami, E. Tamura, T. Ishimitsu, H. Ohara, A Module Level Simulation Technique for Systems Composed of LSI's and MSI's, Proceedings of the 15th Design Automation Conference, Las Vegas 1978, pp. 418-427.

[V AN77] vanCleemput, W. M., "An Hierarchical Language for the Structural Description of Digital Systems," Proceedings of the 14th Design Automation Conference, New Orleans, 1977, pp. 377-385.

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[WIL 76] Wilcox, P., and H. Rombeek, "F/LOGIC - An Interactive Fault and Logic Simulator for Digital Circuits,"

[WIR75] Wirth, N., "An Assessment of the Programming Language Pascal," IEEE Transactions of Software Engineering, Vol. SE 1, 2, June 1975.

[WIR78] Wirth, N., Modula - 2, Instut fur Informatik ETH CH-8092, Zurich, Dec. 1978. Proceedings of the 13th Design Automation Conference, San Francisco, 1976, pp. 68-73.

[WOL78] Wold, M.A. "Design Verification and Performance Analysis," Proceedings of the Fifteenth Design Automation Conference. Las Vegas,Nevada, June 1978,pp 264-270.

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APPENDIX F

INDEX

ADLIB (acronym) ALU model 82

14

AM2901 Destination decoder SO AM2901 hierarchical example 95 AM2901 schematic 69 ASPOL 22 Ada 162 Algorithm debugging Bit-encoding scheme Blackjack 34 CDL 4

94

CLOCK definitions, implementation 153 CLOCK primitive 28 Component type parameters 153 Concurrency, in implementation 143 DDL 8 DETACH, use in NAND gate 102 DIANA 8 Data level 14 Declared (definition) 52 Defined (definition) 52 Densitize 31 Driver Model 102 EDIF 164 Event Scheduling 156 Event cycle 158 Events per second 159 Four-Level Logic Simulation 67 Functional testing 3 GOTOs in ADLIB implementation 143 GPSS 3 Guarded Command Language 4 Guards, in components 115 HELIX 164 HELIX (acronym) 14 IEEE 165 IMP 84

IMP - comptype 86 ISP 4 Implementation, system programs Implementation-based Inertial delay model

testing 159

Latch model 79 MODULE 50 MOTIS 6 MULTI-SIM 8 Macro hierarchy Main body, use of Memory, component Model Initialization Multi-level 14

15 101

110 119

Multiplexer example 17 Multiplexer example 18 NAND gate 101 N AND gate details 65 Name space conflicts 141 Nesting level 14 Net types, implementation 148 Net types, initial values 121 Net types, pointer 117 PACKAGE 50 PACKAGE - 2901 73 PAW 3 PDP-8 40 PHASE primitive 30 PROLOG 13 Parameters to components in

implementation 144 Pascal, Hamburg 139 Pointer, assignment 118 Ports, direction in implementation Protocol, Frame Handling 89 Protocol, data-link layer 83 Protocol, piggy-back ACK 91 RAM multiplexer model 75

139 3

149

206 Multi-Level Simulation for VLSl

ROM model 112 RS Flip-Flop 61 Receptor records 153 Receptor records 155 Recursive descent parser 140 Restart command 121 SABLE (acronym) 14 SARA 9 SCALD 15 SDL 23 SDL for RS-Flip Flop 63 SIMSCRIPT 22 SIMULA67 9 SPLICE 8 SSH 3 Semaphores 32 Sensitize 31 Sensitize, desensitize, implementation lSI Signal procedure 32 Simulation, run-time data structures 154 Singly-linked lists 156 Software - modeling 83 Statement. ASSIGN 26 Statement, CASE 26 Statement. DETACH 31 Statement. FOR 26 Statement. GOTO 26 Statement, IF 25 Statement, WAITFOR 30 Statement, WHILE 26 States, component 110 Subprocess, memory 33 Subprocess, rule-of-thumb 115 Subroutines, implementation 149 TRANSLATOR 22 TRANSMIT, synthesis 166 Timing assertion file 125 Timing constraint verification 121 Timing model for inverter 123 Timing verification algorithm 122 Top-down design 15 Translator, 2 to multi-value 187 Translator, alu function to bus 186 Transport delay 159 Transport mode 30 Type, character 39 Type, enumerated 39 Type, integer 39 Type, real 39 Type-setting convention 17 Typechecking 141 USE 50 Utlrestart VHDL

121 164

Wait procedure Wired-gate_ model

32 108

Wired-gate, rules 109 Wired-gates, insertion 105 Writing Efficient Models 114 Z9 prefix 142 Z9_createJlecvalue 157