Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement Architecture...
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Optimization for Loop Execution Targeting DSP with Auto- Increment/Decrement Architecture Wei-Kai Cheng Youn-Long Lin* Computer & Communications Research Laboratories *CS Department, NTHU Taiw an
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Transcript of Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement Architecture...
Addressing Optimization for Loop Execution Targeting DSP
with Auto-Increment/Decrement Architecture
Wei-Kai Cheng
Youn-Long Lin*
Computer & Communications Research Laboratories
*CS Department, NTHU Taiwan
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Overview
Features: – Auto-Increment/Decrement for Address
Generation– Constraints for Loop Execution
Optimization Methods:– Multi-Phase Data Ordering– Graph-Based Address Register Allocation
» Block Access Graph
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Auto-Increment/Decrement
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New Constraints
Loop Execution– Data Ordering Constraint– Address Register Allocation Constraint
Architectural Constraint– Different arrays are stored in disjoint memory
space– Multiple auto-increment/decrement ranges in
the instruction set architecture
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Data Ordering Constraint
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Address Register Allocation Constraint
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Architectural Constraint
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Data Lists
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Approach
Split the access sequence into data lists– Array– Iteration Stride
Data Ordering Address Register Allocation
– Data Lists Merging or Splitting
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Access Graph
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Data Ordering
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Address Register Allocation
# data lists > # address registers:– data list merging
# data lists < # address registers:– data list splitting
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Two-Way Data List Splitting
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Block Access Graph Construction
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Block Access Graph Partition
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Experimental Results
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fir
iir
dft
fft
edge dct
wie
ner
#data lists
#ordering applied
* number of data lists and data ordering applied
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Experimental Results (Cont.)
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0.2
0.4
0.6
0.8
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fir iir dft fft edge dct wiener
T.o+T.a
O.o+T.a
T.o+O.a
O.o+O.a
* ratio over TI’s compiler in term of inserted instructions
T: TI’s compilerO: Our algorithm
o: data orderinga: address register allocation
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Experimental Results (Cont.)
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0.2
0.4
0.6
0.8
1
fir iir dft fft edge dct wiener
T.o+T.a
O.o+T.a
T.o+O.a
O.o+O.a
* ratio over TI’s compiler in term of execution cycles
T: TI’s compilerO: Our algorithm
o: data orderinga: address register allocation
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Conclusions
Data ordering is not so effective in loop execution
Data list splitting is more important than data list merging
