of 27

• date post

04-Jun-2018
• Category

## Documents

• view

220

0

Embed Size (px)

1/27

Verification

D. W. Parent

1

2/27

This is a very efficient 1 bit full adder.

2

3/27

generate

propagate

carry

sum

3

4/27

Derive the schematic.

4

5/27

It is easier to manage the design if you partition items into

blocks

The Generate PropagateBlock (4 bits seemed

easier to do.)

5

6/27

The look ahead carry generate block

Ver similar

to 4 bit CLA

but note ther

P and

G

6

term.

7/27

The sums are broken up into 4 bits each. This will help with

LVS later.

7

8/27

WN/WP for a 16 bit CLA Adder in Static

wiring capacitance.

8

9/27

WN/WP for a 16 bit CLA Adder in dynamic

9

10/27

Higher order adders are too complex to draw at the circuit

level

-

4 input 3 input

Note: Twoi:j

Buffer

Gray

Cell

:Black

Cell

:output vectors

i:ji:j,

i:j

10

11/27

Higher order diagrams can be made as well

i:k k-1:l l-1:m m-1:j

11

12/27

The Manchester Carry Chain can be greatly simplifies in

multiple output domino logic

123:0 2:0 1:0 0:0

13/27

MCC PG Group

an or ac ne ns e

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

G=C

13Final Sum XOR inside

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

14/27

Example: Find the Delay of the 16bit MCC adder.

Assume the MCC domino vs Static

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

14

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

15/27

This example shows how the logic was

ver e o a ogge tone er

Convert grey and black cells to schematics

15

16/27

When doing a completely new logic just

use e g a par s n e

Schematic

Make sure to

Symboledit the labelsso that they can be

seen in a large

16

.

17/27

Once could use AOI or NAND NAND to implement these cells.

Schematic

A Grey cell is a Black cell

Symbolwithout the grouppropagate

17

18/27

Tree Diagram of KS adder from

David Harris

18

19/27

8 bit KS adder schematic with carry in and carry out

19

20/27

try and show the equivalence of a ripple,

Not my strong suit.

20

21/27

Create and verify a 1 bit full adder

21

22/27

22

23/27

-

This will be used to compare the carry out

and sum signals of both adders.

23

24/27

Create a test bench that will

feed the same test

24

and compare their outputs.

25/27

adder Search for 1. If signals are different then XOR will give

one.

25

Can not really see if there is a 1 value at this time scale.

26/27

Export Data Into Text

NC verilog tracks the changes only. WE

can see that no signal was a 1 and since

we did all test vectors the adders are

logically equivalent.

This is all the data.

26

27/27