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Transcript of Adc Manual Ece 2013 Reg
ANALOG AND DIGITAL COMMUNICATION
Laboratory Manual
K. Michael Mahesh M.E, MISTE, AMIE, MIET, MIEEE Assistant Professor / ECE
St. Joseph College of Eng., Chennai.
Abstract Analog and Digital Communication Laboratory Manual for ECE Department 2013 Regulation
1
ST. JOSEPH COLLEGE OF ENGINEERING Chennai - 602117
NAME :
ROLL NO :
CLASS / SEM : II B.E -ECE / III SEM
SECTION :
SUBJECT CODE : EC6311
SUBJECT NAME : ANALOG AND DIGITAL CIRCUITS LABORATORY
Prepared by
Mr. K. Michael Mahesh.,
M.E, MISTE, AMIE, MIET, MIEEE
Assistant Professor / ECE
St. Joseph College of Eng., Chennai.
2
LABORATORY REGULATIONS AND SAFETY RULES
The following Regulations and Safety Rules must be observed in all concerned
laboratory location.
It is the duty of all concerned who use any electronics laboratory to take all
reasonable steps to safeguard the HEALTH and SAFETY of themselves and
all other users and visitors.
Be sure that all equipment is properly working before using them for
laboratory exercises. Any defective equipment must be reported immediately
to the Lab. Instructors or Lab. Technical Staff.
Students are allowed to use only the equipment provided in the experiment
manual.
Power supply terminals connected to any circuit are only energized with the
presence of the Instructor or Lab. Staff.
Avoid any part of your body to be connected to the energized circuit and
ground.
Switch off the equipment and disconnect the power supplies from the circuit
before leaving the laboratory.
Observe cleanliness and proper laboratory housekeeping of the equipment and
other related accessories.
Make sure that the last connection to be made in your circuit is the power
supply and first thing to be disconnected is also the power supply.
Equipment should not be removed, transferred to any location without
permission from the laboratory staff.
Students are not allowed to use any equipment without proper orientation and
actual hands on equipment operation.
3
EXTRACT OF ANNA UNIVERSITY SYLLABUS
ANALOG AND DIGITAL CIRCUITS LABORATORY
LIST OF EXPERIMENTS
LIST OF ANALOG EXPERIMENTS:
1. Frequency Response of CE / CB / CC amplifier
2. Frequency response of CS Amplifiers
3. Darlington Amplifier
4. Differential Amplifiers- Transfer characteristic.
5. CMRR Measurment
6. Cascode / Cascade amplifier
7. Determination of bandwidth of single stage and multistage amplifiers
8. Spice Simulation of Common Emitter and Common Source amplifiers
LIST OF DIGITAL EXPERIMENTS
9. Design and implementation of code converters using logic gates
(i) BCD to excess-3 code and vice versa
(ii) Binary to gray and vice-versa
10. Design and implementation of 4 bit binary Adder/ Subtractor and BCD adder using IC
7483
11. Design and implementation of Multiplexer and De-multiplexer using logic gates
12. Design and implementation of encoder and decoder using logic gates
13. Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple
counters
14. Design and implementation of 3-bit synchronous up/down counter
15. Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- flops
4
INDEX
S.NO
DATE
EXPERIMENT NAME
MARKS
SIGN
I CYCLE EXPERIMENTS ( ANALOG EXPERIMENTS)
1 (a) COMMON EMITTER AMPLIFIER
(b) COMMON BASE AMPLIFIER
(c) COMMON COLLECTOR AMPLIFIER
2 COMMON SOURCE AMPLIFIER
3 DARLINGTON AMPLIFIER
4 DIFFERENTIALAMPLIFIER
5 CASCODE AMPLIFIER
6 CASCADED AMPLIFIER
SIMULATION EXPERIMENT
7 COMMON EMITTER AMPLIFIER
8 COMMON SOURCE AMPLIFIER
II CYCLE EXPERIMENTS ( DIGITAL EXPERIMENTS)
9(a) BCD TO EXCESS-3 CODE
(b) EXCESS-3 TO BCD
(c) BINARY TO GRAY CODE
(d) GRAY TO BINARY CODE
10(a) 4 BIT BINARY ADDER/ SUBTRACTOR
(b) BCD ADDER USING IC 7483
11(a) MULTIPLEXER USING LOGIC GATES
(b) DEMULTIPLEXER USING LOGIC GATES
12(a) ENCODER
(b) DECODER
13(a) 4 BIT RIPPLE COUNTER
(b) MOD-10 / MOD-12 RIPPLE COUNTERS
14 3-BIT SYNCHRONOUS UP
COUNTER/DOWN COUNTER
15 SHIFT REGISTERS USING FLIP- FLOPS
5
EXP. NO : 1 (a) DATE:
COMMON EMITTER AMPLIFIER
Aim : To construct a Common Emitter Amplifier circuit and to plot it’s frequency
response characteristics.
Components Required :
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. Transistor BC547 1
2. Resistors 63KΩ,12KΩ,600Ω,2.5KΩ Each 1
3. Capacitors 0.78µF,0.63 µF,2.6 µF Each 1
4. DC power supply 12 V 1
5. Function Generator 0 – 10MHz 1
6. CRO Dual channel,30MHz 1
7. Probes - 2
8. Breadboard - 1
9. Connecting Wires - Few
OVERVIEW :
This type of biasing is otherwise called Emitter Biasing. The necessary biasing is provided
using 3 resistors: R1, R2 and RE. The resistors R1 and R2 act as a potential divider and give a
fixed voltage to the base. If the collector current increases due to change in temperature or change
in β, the emitter current IE also increases and the voltage drop across RE increases, reducing the
voltage difference between the base and the emitter. Due to reduction in VBE, base current IB and
hence collector current IC also reduces. This reduction in VBE, base current IB and hence collector
current IC also reduces. This reduction in the collector current compensates for the original change
in IC.
The stability factor S= (1+β) * ((1/ (1+β)). To have better stability, we must keep RB/RE
as small as possible. Hence the value of R1 R2 must be small. If the ratio RB/RE is kept fixed, S
increases with β.
6
SCHEMATIC REPRESENTATION WITH VALUES
MODEL GRAPH :
7
PROCEDURE
1. Connect the circuit as shown in the circuit diagram.
2. Apply an input of 50mV peak-to-peak and 10 Hz frequency using function generator
3. Measure the output voltage Vo (p-p) for various values of frequencies.
4. Tabulate the readings in the tabular column.
5. The voltage gain can be calculated by using the expression 20*log(V0/Vi) in dB.
6. For plotting the frequency response the input voltage is kept constant at 50mV peak-to-peak
and the frequency is varied from 10Hz to 2MHz using function generator
7. Note down the value of output voltage for each frequency.
8. All the readings are tabulated and voltage gain in dB is calculated by using the expression 20
log10 (V0/Vi)
9. A graph is drawn by taking frequency on x-axis and gain in dB on y-axis on a semi-log graph.
10. The bandwidth is calculated from the frequency response graph as BW=f2-f1.
Tabular Column: Vi = _______ V
S.No.
Input signal
frequency in (Hz)
Output Voltage Vo
(volt)
Gain in db
=(20 log (Vo/Vi))
RESULT:
Thus the Common Emitter Amplifier circuit is constructed and it’s frequency response is
plotted.
8
EXP. NO : 1 (b) DATE:
COMMON BASE AMPLIFIER
Aim : To construct a Common Base Amplifier circuit and to plot it’s frequency response
characteristics.
Components Required :
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. Transistor 2N2222 1
2. Resistors 15KΩ,10KΩ,4.7KΩ,3.3KΩ,1
KΩ
Each 1
3. Capacitors 10µF,100 µF 2,1
4. DC power supply 20 V 1
5. Function Generator 0 – 10MHz 1
6. CRO Dual channel,30MHz 1
7. Probes - 2
8. Breadboard - 1
9. Connecting Wires - Few
OVERVIEW :
Common-base transistor amplifiers are so-called because the input and output voltage points
share the base lead of the transistor in common with each other, not considering any power
supplies.
The current gain of a common-base amplifier is always less than 1. The voltage gain is a
function of input and output resistances, and also the internal resistance of the emitter-base
junction, which is subject to change with variations in DC bias voltage. Suffice to say that the
voltage gain of a common-base amplifier can be very high.
The ratio of a transistor's collector current to emitter current is called α. The α value for any
transistor is always less than unity, or in other words, less than 1. Some of it’s applications include
radio frequency amplifiers. The grounded base helps shield the input at the emitter from the
collector output, preventing instability in RF amplifiers. The common base configuration is usable
at higher frequencies than common emitter or common collector.
9
SCHEMATIC REPRESENTATION WITH VALUES
MODEL GRAPH :
0
0
0
0
0
R4
4.7k
R3
15k
R2
3.3k
R1
10k
Q1
Q2N2222
C3
10u
C2
100u
C1
10u
R5
1k
V1
V3
20V
10
PROCEDURE
1. Connect the circuit as shown in the circuit diagram.
2. Apply an input of 50mV peak-to-peak and 10 Hz frequency using function generator
3. Measure the output voltage Vo (p-p) for various values of frequencies.
4. Tabulate the readings in the tabular column.
5. The voltage gain can be calculated by using the expression 20*log(V0/Vi) in dB.
6. For plotting the frequency response the input voltage is kept constant at 50mV peak-to-
peak and the frequency is varied from 10Hz to 2MHz using function generator
7. Note down the value of output voltage for each frequency.
8. All the readings are tabulated and voltage gain in dB is calculated by using the expression
20 log10 (V0/Vi)
9. A graph is drawn by taking frequency on x-axis and gain in dB on y-axis on a semi-log
graph.
10. The bandwidth is calculated from the frequency response graph as BW=f2-f1.
Tabular Column: Vi = _______ V
S.No.
Input signal
frequency in (Hz)
Output Voltage Vo
(volt)
Gain in db
=(20 log (Vo/Vi))
RESULT:
Thus the Common Base Amplifier circuit is constructed and it’s frequency response is
plotted.
.
11
EXP. NO : 1 (C) DATE:
COMMON COLLECTOR AMPLIFIER
Aim : To construct a Common Collector Amplifier circuit and to plot it’s frequency
response characteristics.
Components Required :
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. Transistor 2N2222 1
2. Resistors 200KΩ,10KΩ,100KΩ 2,1,1
3. Capacitors 0.01µF 2
4. DC power supply 15 V 1
5. Function Generator 0 – 10MHz 1
6. CRO Dual channel,30MHz 1
7. Probes - 2
8. Breadboard - 1
9. Connecting Wires - Few
OVERVIEW :
Common-collector transistor amplifiers are so-called because the input and output voltage
points share the collector lead of the transistor in common with each other, not considering any
power supplies.
The common-collector amplifier is also known as an emitter-follower. The output voltage
on a common-collector amplifier will be in phase with the input voltage, making the common-
collector a non-inverting amplifier circuit.
The current gain of a common-collector amplifier is equal to β plus 1. The voltage gain is
approximately equal to 1. A popular application of the common-collector amplifier is for
regulated DC power supplies, where an unregulated (varying) source of DC voltage is clipped
at a specified level to supply regulated (steady) voltage to a load.
12
SCHEMATIC REPRESENTATION WITH VALUES
MODEL GRAPH :
0
0
0
R2
10k
R3
200k
R4
200k
C1
0.01u
V1
V3
15V
Q1
Q2N2222
C2
0.01u
R6
1000k
13
PROCEDURE
1. Connect the circuit as shown in the circuit diagram.
2. Apply an input of 50mV peak-to-peak and 10 Hz frequency using function generator
3. Measure the output voltage Vo (p-p) and thus calculate the Io (p-p)= Vo (p-p) / Ro for
various values of frequencies.
4. Tabulate the readings in the tabular column.
5. The current gain can be calculated by using the expression 20*log (I0/Ii) in dB.
6. For plotting the frequency response the input voltage is kept constant at 50mV peak-to-
peak and the frequency is varied from 10Hz to 2MHz using function generator
7. Note down the value of output voltage for each frequency.
8. All the readings are tabulated and the current gain in dB is calculated by using the
expression 20 log10 (I0/Ii).
9. A graph is drawn by taking frequency on x-axis and gain in dB on y-axis on a semi-log
graph.
10. The bandwidth is calculated from the frequency response graph as BW=f2-f1.
Tabular Column: Ii = _______ mA
S.No.
Input signal
frequency in (Hz)
Output Voltage
Vo
(volt)
Output Current
Io= Vo/ Ro
(mA)
Gain in db
=20 log (I0/Ii)
RESULT:
Thus the Common Collector Amplifier circuit is constructed and it’s frequency response
is plotted.
14
EXP. NO : 2 DATE:
COMMON SOURCE AMPLIFIER
Aim : To construct a Common Source Amplifier circuit and to plot it’s frequency
response characteristics.
Components Required :
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. Transistor BFW10 1
2. Resistors 220KΩ,68KΩ,2.2KΩ,
3.9KΩ, 5.6KΩ,1.5k
1 each
3. Capacitors 1µF, 10µF,6.8µF 1 each
4. DC power supply 20 V 1
5. Function Generator 0 – 10MHz 1
6. CRO Dual channel,30MHz 1
7. Probes - 2
8. Breadboard - 1
9. Connecting Wires - Few
OVERVIEW :
The common-source (CS) amplifier may be viewed as a transconductance amplifier or as
a voltage amplifier.As a transconductance amplifier, the input voltage is seen as modulating the
current going to the load. As a voltage amplifier, input voltage modulates the amount of current
flowing through the FET, changing the voltage across the output resistance according to Ohm's
law. However, the FET device's output resistance typically is not high enough for a reasonable
transconductance amplifier, nor low enough for a decent voltage amplifier.
15
SCHEMATIC REPRESENTATION WITH VALUES
MODEL GRAPH :
0
0
J1
J2N3819
R4
2.2k
R1
3.9k
R5
68kC1
10u
C3
1u
C2
6.8u
V1
20V
R6
5.6k
V2
R13
1.5k
R14
220k
16
PROCEDURE
1. Connect the circuit as shown in the circuit diagram.
2. Apply an input of 50mV peak-to-peak and 10 Hz frequency using function generator
3. Measure the output voltage Vo (p-p) for various values of frequencies.
4. Tabulate the readings in the tabular column.
5. The voltage gain can be calculated by using the expression 20*log(V0/Vi) in dB.
6. For plotting the frequency response the input voltage is kept constant at 50mV peak-to-
peak and the frequency is varied from 10Hz to 2MHz using function generator
7. Note down the value of output voltage for each frequency.
8. All the readings are tabulated and voltage gain in dB is calculated by using the expression
20 log10 (V0/Vi)
9. A graph is drawn by taking frequency on x-axis and gain in dB on y-axis on a semi-log
graph.
10. The bandwidth is calculated from the frequency response graph as BW=f2-f1.
Tabular Column: Vi = _______ V
S.No.
Input signal
frequency in (Hz)
Output Voltage Vo
(volt)
Gain in db
=(20 log (Vo/Vi))
RESULT:
Thus the Common Source Amplifier circuit is constructed and it’s frequency response is
plotted.
17
EXP. NO : 3 DATE:
DARLINGTON AMPLIFIER
Aim : To construct a Darlington Amplifier circuit and to find it’s frequency response.
Components Required :
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. Transistor 2N2222 2
2. Resistors 15KΩ,4.7KΩ,2.2KΩ,1KΩ,
1000KΩ
Each one
3. Capacitors 10µF 2
4. Dual DC power supply 20 V 1
5. Function Generator 0 – 10MHz 1
6. CRO Dual channel,30MHz 1
7. Probes - 2
8. Breadboard - 1
9 Connecting Wires - Few
OVERVIEW :
In Darlington connection of transistors, emitter of the first transistor is directly connected
to the base of the second transistor .Because of direct coupling dc output current of the first stage
is (1+hfe )Ib1.If Darlington connection for n transistor is considered, then due to direct coupling
the dc output current for the last stage is nx(1+hfe ) times Ib1 .Due to a very large amplification
factor even two stage Darlington connection has large output current.
In Darlington transistor connection, the leakage current of the first transistor is amplified
by the second transistor and overall leakage current may be high, which is not desired.
18
SCHEMATIC REPRESENTATION WITH VALUES
MODEL GRAPH :
0
0R7
15kC4
10u
V3
20V
V4
R36
1k
Q28
Q2N2222Q29
Q2N2222R34
1000k
C20
10u
R37
4.7k
R38
2.2k
19
PROCEDURE
1. Connect the circuit as shown in the circuit diagram.
2. Apply an input of 50mV peak-to-peak and 10 Hz frequency using function generator
3. Measure the output voltage Vo (p-p) for various values of frequencies.
4. Tabulate the readings in the tabular column.
5. The voltage gain can be calculated by using the expression 20*log(V0/Vi) in dB.
6. For plotting the frequency response the input voltage is kept constant at 50mV peak-to-
peak and the frequency is varied from 10Hz to 2MHz using function generator
7. Note down the value of output voltage for each frequency.
8. All the readings are tabulated and voltage gain in dB is calculated by using the expression
20 log10 (V0/Vi)
9. A graph is drawn by taking frequency on x-axis and gain in dB on y-axis on a semi-log
graph.
10. The bandwidth is calculated from the frequency response graph as BW=f2-f1.
Tabular Column: Vi = _______ V
S.No.
Input signal
frequency in (Hz)
Output Voltage Vo
(volt)
Gain in db
=(20 log (Vo/Vi))
RESULT:
Thus the Darlington Amplifier circuit is constructed and it’s frequency response is plotted.
20
EXP. NO : 4 DATE:
DIFFERENTIALAMPLIFIER
Aim : To construct a Differential Amplifier circuit and to find its transfer Characteristics
and measure it’s CMRR.
Components Required :
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. Transistor 2N2222 2
2. Resistors 2KΩ,1 KΩ 1,2
3. Dual DC power supply 5 V 1
4. Function Generator 0 – 10MHz 1
5. CRO Dual channel,30MHz 1
6. Probes - 2
7. Breadboard - 1
8. Connecting Wires - Few
OVERVIEW :
The differential amplifier can be implemented using BJTs and is a commonly used building block
in analog IC design. The BJT implementation of the differential pair as emitter-coupled, common-emitter
(or emitter-resist or) amplifiers.
The simplest form of the differential amplifier is formed using two matched transistors (Q1and
Q2), in the E configuration whose emitters have been tied together. The differential pair has two inputs
(v1and v2), and three possible outputs (vo1, vo2, and vout). It is necessary that RE have a large value to keep
the voltage drop across it nearly constant with reasonable changes n current. It is absolutely imperative
however, that whatever is in the collector circuit ensures that Q1and Q2 never enter saturation.
For the differential mode operation the input is taken from two different sources and for the
common mode operation the applied signals are taken from the same source
Common Mode Rejection Ratio (CMRR) is an important parameter of the differential amplifier.
CMRR is defined as the ratio of the differential mode gain Ad to the common mode gain, Ac.In ideal cases,
the value of CMRR is very high.
21
SCHEMATIC REPRESENTATION WITH VALUES
MODEL GRAPH : Voltage transfer characteristic
0
0
00
Q19
Q2N2222
Q17
Q2N2222
R30
1k
R29
1k
R31
2k
V18
5V
V17
5V
V19 V20
22
CALCULATION OF CMRR
COMMON MODE GAIN
AC=VOUT/[(V1+V2)/2]
DIFFERENTIAL MODE GAIN
AD=VOUT/(V1-V2)
CMRR = | AD/AC |
TABULAR COLUMN
VOLTAGE TRANSFER CHARACTERISTICS
V1 (V) V2 (V) VO1 (V)
VO2 (V)
VID=V1-V2(V) VOD= VO1- VO2(V)
23
CMRR CALCULATION
MODES V1 (V) V2 (V) VO (V)
COMMON MODE
DIFFERENTIAL
MODE
PROCEDURE
1. Connections are given as per the circuit diagram.
2. To determine the common mode gain, set the input signal same at both inputs and
determine Vo at the collector terminals. Calculate common mode gain, from
AC=VOUT/[(V1+V2)/2]
3. To determine the differential mode gain, set the input signals with voltages V1 and V2 at
the two inputs. Find Vo at the collector terminals. Calculate differential mode gain, from
AD=VOUT/(V1-V2)
4. Calculate CMRR=AD/Ac.
5. For different values of input and the corresponding outputs in differential mode, the
voltage transfer characteristic graph is drawn.
RESULT:
Thus the Differential Amplifier circuit is constructed and it’s transfer characteristics
and CMRR are measured.
24
EXP. NO : 5 DATE:
CASCODE AMPLIFIER
Aim : To construct a Cascode Amplifier circuit and to plot it’s frequency response
characteristics.
Components Required :
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. Transistor 2N2222 2
2. Resistors 6.8KΩ,5.6KΩ,4.7KΩ1.1KΩ,1.8KΩ,1KΩ Each 1
3. Capacitors 10µF,5µF,20µF 1,2,1
4. DC power supply 20 V 1
5. Function Generator 0 – 10MHz 1
6. CRO Dual channel,30MHz 1
7. Probes - 2
8. Breadboard - 1
9. Connecting Wires - Few
OVERVIEW :
The cascode is a two-stage amplifier composed of a trans conductance amplifier followed by a
current buffer.
Compared to a single amplifier stage, this combination may have one or more of the following
characteristics: higher input-output isolation, higher input impedance, high output impedance, higher gain
or higher bandwidth.
The cascode amplifier is constructed from two BJTs, with one operating as a common emitter and
the other as a common base. The cascode improves input-output isolation (or reverse transmission) as there
is no direct coupling from the output to input. This eliminates the Miller effect and thus contributes to a
much higher bandwidth.
25
SCHEMATIC REPRESENTATION WITH VALUES
0
0
0 R4
5.6k
R3
4.7kR2
1.1k
C2
20u
C4
5u
V2
Q2
Q2N2222
V1
18V
R6
1k
C1
10u
C3
5uQ1
Q2N2222
R1
1.8k
R5
6.8k
26
MODEL GRAPH :
PROCEDURE
1. Connect the circuit as shown in the circuit diagram.
2. Apply an input of 50mV peak-to-peak and 10 Hz frequency using function generator
3. Measure the output voltage Vo (p-p) for various values of frequencies.
4. Tabulate the readings in the tabular column.
5. The voltage gain can be calculated by using the expression 20*log(V0/Vi) in dB.
6. For plotting the frequency response the input voltage is kept constant at 50mV peak-to-
peak and the frequency is varied from 10Hz to 2MHz using function generator
7. Note down the value of output voltage for each frequency.
8. All the readings are tabulated and voltage gain in dB is calculated by using the expression
20 log10 (V0/Vi)
9. A graph is drawn by taking frequency on x-axis and gain in dB on y-axis on a semi-log
graph.
10. The bandwidth is calculated from the frequency response graph as BW=f2-f1.
27
Tabular Column: Vi = _______ V
S.No.
Input signal
frequency in (Hz)
Output Voltage Vo
(volt)
Gain in db
=(20 log (Vo/Vi))
RESULT:
Thus the Cascode Amplifier circuit is constructed and it’s frequency response is plotted.
28
EXP. NO : 6 DATE:
CASCADED AMPLIFIER
Aim : To construct a single stage and two -stage amplifier circuit and determine it’s
bandwidth.
Components Required :
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. Transistor 2N2222 2
2. Resistors 15KΩ,2.2KΩ,4.7KΩ1KΩ,10 KΩ 2,2,2,2,1
3. Capacitors 10µF,20µF 3,2
4. DC power supply 20 V 1
5. Function Generator 0 – 10MHz 1
6. CRO Dual channel,30MHz 1
7. Probes - 2
8. Breadboard - 1
9. Connecting Wires - Few
OVERVIEW :
When we want to achieve higher amplification than a single stage amplifier can offer, it is
a common practice to cascade various stages of amplifiers, as it is shown in Fig.1.a. In such a
structure the input performance of the resulted multistage amplifier is the input performance of the
first amplifier while the output performance is that of the last amplifier. The total voltage gain of
cascade connection is the product of the individual stage i.e. Av=Av1*Av2.But the bandwidth is
decreased. Hence there is a trade-off between the gain and bandwidth of the amplifier as the
number of stages is increased.
29
SCHEMATIC REPRESENTATION WITH VALUES
SINGLE STAGE AMPLIFIER
0
0
R28
10k
R24
2.2k
R26
15k
R20
4.7k
R22
1kC17
20u
C18
10uQ14
Q2N2222
V15
20V
C16
10u
V16
30
TWO-STAGE AMPLIFIER
MODEL GRAPH :
0
0
R18
10k
R16
15k
R15
15k
R14
2.2k
R131k
R12
1kR11
4.7kR10
4.7k
Q5
Q2N2222
Q4
Q2N2222
R17
2.2k
C8
10u
C7
20u
C6
10u
C10
10u
C9
20u
V5
20V
V6
31
PROCEDURE
1. Connect the circuit as shown in the circuit diagram.
2. Apply an input of 50mV peak-to-peak and 10 Hz frequency using function generator
3. Measure the output voltage Vo (p-p) for various values of frequencies.
4. Tabulate the readings in the tabular column.
5. The voltage gain can be calculated by using the expression 20*log(V0/Vi) in dB.
6. For plotting the frequency response the input voltage is kept constant at 50mV peak-to-
peak and the frequency is varied from 10Hz to 2MHz using function generator
7. Note down the value of output voltage for each frequency.
8. All the readings are tabulated and voltage gain in dB is calculated by using the expression
20 log10 (V0/Vi)
9. A graph is drawn by taking frequency on x-axis and gain in dB on y-axis on a semi-log
graph.
10. The bandwidth is calculated from the frequency response graph as BW=f2-f1.
Tabular Column:
SINGLE STAGE AMPLIFIER
Vi = _______ V
S.No.
Input signal
frequency in (Hz)
Output Voltage Vo
(volt)
Gain in db
=(20 log (Vo/Vi))
32
TWO-STAGE AMPLIFIER
Vi = _______ V
S.No.
Input signal
frequency in (Hz)
Output Voltage Vo
(volt)
Gain in db
=(20 log (Vo/Vi))
RESULT:
Thus the single stage and two -stage amplifier circuit is constructed and it’s frequency it’s
bandwidth is measured.
33
EXP. NO : 7 DATE:
SIMULATION EXPERIMENT
COMMON EMITTER AMPLIFIER
Aim : To simulate a Common Emitter Amplifier in ORCAD PSPICE and to obtain it’s
frequency response characteristics.
SOFTWARE REQUIRED:
ORCAD PSPICE
SCHEMATIC REPRESENTATION WITH VALUES
0
0
R1
2.2kR2
910k
R4
1.2k
R5
220kC1
20u
C2
10uC3
5u
V1
15V
R6
1k
V2
Q1
Q2N2222
34
OVERVIEW :
This type of biasing is otherwise called Emitter Biasing. The necessary biasing is provided
using 3 resistors: R1, R2 and RE. The resistors R1 and R2 act as a potential divider and give a
fixed voltage to the base. If the collector current increases due to change in temperature or change
in β, the emitter current IE also increases and the voltage drop across RE increases, reducing the
voltage difference between the base and the emitter. Due to reduction in VBE, base current IB and
hence collector current IC also reduces. This reduction in VBE, base current IB and hence collector
current IC also reduces. This reduction in the collector current compensates for the original change
in IC.
The stability factor S= (1+β) * ((1/ (1+β)). To have better stability, we must keep RB/RE
as small as possible. Hence the value of R1 R2 must be small. If the ratio RB/RE is kept fixed, S
increases with β.
MODEL GRAPH :
35
PROCEDURE:
1. Select File >> New >> Project. Name your project and select the directory as the
location field. Be sure that you selected “Analog or Mixed A/D”.
2. Now, select “Create a blank project” at the appeared diagram box below
3. An empty page in Schematic Editor will be opened. Now draw the given circuit in the
Schematic Editor. To work your circuit properly, don’t forget to add Ground to your
circuit. Set the parameters as shown in the circuit above.
36
37
38
4. After the construction of the circuit, create a new profile using Pspice >> New
Simulation Profile from toolbar. Write a name in the New Simulation Name.
5. After clicking on the Create button, the following dialog box will appear. For frequency
response characteristics specify the type of analysis as ‘AC Sweep /Noise’. Since the
input frequency is varied , enter the start frequency as 20Hz and end frequency as
20KHz. Enter the total number of points per decade in the Points/Decade box
39
6. Run your program by using toolbar as Pspice >> Run.
7. Another window will be opened and the frequency response characteristics will be
displayed.
40
SIMULATION REPORT:
Circuit Schematic:
Simulation Graph :
0
0
R1
2.2kR2
910k
R4
1.2k
R5
220kC1
20u
C2
10uC3
5u
V1
15V
R6
1k
V2
Q1
Q2N2222
Frequency
1.0Hz 1.0KHz 1.0MHz 1.0GHz
20* LOG(V(R28:2)/0.00005)
-100
0
100
200G
a
i
n
i
n
d
B
41
Output file :
**** 05/28/14 20:07:32 ********* PSpice 9.0 (Nov 1998) ******** ID# 0 ********
** circuit file for profile: ce-1
**** CIRCUIT DESCRIPTION
******************************************************************************
** WARNING: DO NOT EDIT OR DELETE THIS FILE
*Libraries:
* Local Libraries :
* From [PSPICE NETLIST] section of pspice.ini file:
.lib "nom.lib"
*Analysis directives:
.AC DEC 10 1Hz 10000000000Hz
.PROBE
*Netlist File:
.INC "ce-1-SCHEMATIC1.net"
*Alias File:
**** INCLUDING ce-1-SCHEMATIC1.net ****
* source CE-1
R_R1 N00069 N00054 2.2k
R_R2 N00049 N00054 910k
R_R4 0 N00107 1.2k
R_R5 0 N00049 220k
C_C1 0 N00107 20u
C_C2 N00069 N00203 10u
C_C3 N00238 N00049 5u
V_V1 N00054 0 15V
R_R6 0 N00203 1k
V_V2 N00238 0 DC 0V AC 100mV
+SIN 0V 100mV 1000Hz 0 0 0
Q_Q1 N00069 N00049 N00107 Q2N2222
**** RESUMING ce-1-SCHEMATIC1-ce-1.sim.cir ****
.INC "ce-1-SCHEMATIC1.als"
**** INCLUDING ce-1-SCHEMATIC1.als ****
.ALIASES
42
R_R1 R1(1=N00069 2=N00054 )
R_R2 R2(1=N00049 2=N00054 )
R_R4 R4(1=0 2=N00107 )
R_R5 R5(1=0 2=N00049 )
C_C1 C1(1=0 2=N00107 )
C_C2 C2(1=N00069 2=N00203 )
C_C3 C3(1=N00238 2=N00049 )
V_V1 V1(+=N00054 -=0 )
R_R6 R6(1=0 2=N00203 )
V_V2 V2(+=N00238 -=0 )
Q_Q1 Q1(c=N00069 b=N00049 e=N00107 )
.ENDALIASES
**** RESUMING ce-1-SCHEMATIC1-ce-1.sim.cir ****
.END
**** 05/28/14 20:07:32 ********* PSpice 9.0 (Nov 1998) ******** ID# 0 ********
** circuit file for profile: ce-1
**** BJT MODEL PARAMETERS
******************************************************************************
Q2N2222
NPN
IS 14.340000E-15
BF 255.9
NF 1
VAF 74.03
IKF .2847
ISE 14.340000E-15
NE 1.307
BR 6.092
NR 1
RB 10
RC 1
CJE 22.010000E-12
MJE .377
CJC 7.306000E-12
MJC .3416
TF 411.100000E-12
XTF 3
43
VTF 1.7
ITF .6
TR 46.910000E-09
XTB 1.5
CN 2.42
D .87
**** 05/28/14 20:07:32 ********* PSpice 9.0 (Nov 1998) ******** ID# 0 ********
** circuit file for profile: ce-1
**** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.000 DEG C
******************************************************************************
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
(N00049) 1.8564 (N00054) 15.0000 (N00069) 12.7880 (N00107) 1.2139
(N00203) 0.0000 (N00238) 0.0000
VOLTAGE SOURCE CURRENTS
NAME CURRENT
V_V1 -1.020E-03
V_V2 0.000E+00
TOTAL POWER DISSIPATION 1.53E-02 WATTS
JOB CONCLUDED
TOTAL JOB TIME .27
RESULT:
Thus a Common Emitter Amplifier in ORCAD PSPICE is simulated and it’s frequency
response characteristics is obtained.
44
EXP. NO : 8 DATE:
SIMULATION EXPERIMENT
COMMON SOURCE AMPLIFIER
Aim : To simulate a Common Source Amplifier in ORCAD PSPICE and to obtain it’s
frequency response characteristics.
SOFTWARE REQUIRED:
ORCAD PSPICE
SCHEMATIC REPRESENTATION WITH VALUES
0
0
J1
J2N3819
R4
2.2k
R1
3.9k
R5
68kC1
10u
C3
1u
C2
6.8u
V1
20V
R6
5.6k
V2
R13
1.5k
R14
220k
45
OVERVIEW :
The common-source (CS) amplifier may be viewed as a trans conductance amplifier or as
a voltage amplifier. As a trans conductance amplifier, the input voltage is seen as modulating the
current going to the load. As a voltage amplifier, input voltage modulates the amount of current
flowing through the FET, changing the voltage across the output resistance according to Ohm's
law. However, the FET device's output resistance typically is not high enough for a reasonable
trans conductance amplifier, nor low enough for a decent voltage amplifier.
MODEL GRAPH:
46
PROCEDURE:
1. Select File >> New >> Project. Name your project and select the directory as the location
field. Be sure that you selected “Analog or Mixed A/D”.
2. Now, select “Create a blank project” at the appeared diagram box below
3. An empty page in Schematic Editor will be opened. Now draw the given circuit in the
Schematic Editor. To work your circuit properly, don’t forget to add Ground to your circuit.
Set the parameters as shown in the circuit above.
47
48
49
4. After the construction of the circuit, create a new profile using Pspice >> New Simulation
Profile from toolbar. Write a name in the New Simulation Name.
5. After clicking on the Create button, the following dialog box will appear. For frequency
response characteristics specify the type of analysis as ‘AC Sweep /Noise’. Since the input
frequency is varied , enter the start frequency as 20Hz and end frequency as 20KHz. Enter
the total number of points per decade in the Points/Decade box
50
6. Run your program by using toolbar as Pspice >> Run.
7. Another window will be opened and the frequency response characteristics will be
displayed.
51
SIMULATION REPORT:
Circuit Schematic:
Simulation Graph :
0
0
J1
J2N3819
R4
2.2k
R1
3.9k
R5
68kC1
10u
C3
1u
C2
6.8u
V1
20V
R6
5.6k
V2
R13
1.5k
R14
220k
Frequency
1.0Hz 1.0KHz 1.0MHz 1.0GHz 1.0THz
20* LOG(V(R6:2)/1)
-100
-50
0
50G
a
i
n
i
n
d
B
52
Output file :
**** 05/28/14 20:13:13 ********* PSpice 9.0 (Nov 1998) ******** ID# 0 ********
** circuit file for profile: common source-fet
**** CIRCUIT DESCRIPTION
******************************************************************************
** WARNING: DO NOT EDIT OR DELETE THIS FILE
*Libraries:
* Local Libraries :
* From [PSPICE NETLIST] section of pspice.ini file:
.lib "nom.lib"
*Analysis directives:
.AC DEC 10 1Hz 4000000000Hz
.PROBE
*Netlist File:
.INC "common source-fet-SCHEMATIC1.net"
*Alias File:
**** INCLUDING "common source-fet-SCHEMATIC1.net" ****
* source COMMON SOURCE-FET
J_J1 N00069 N00044 N00107 J2N3819
R_R4 0 N00107 2.2k
R_R1 N00069 N00061 3.9k
R_R5 0 N00044 68k
C_C1 0 N00107 10u
C_C3 N01480 N00044 1u
C_C2 N00069 N00203 6.8u
V_V1 N00061 0 20V
R_R6 0 N00203 5.6k
V_V2 N00241 0 DC 0V AC 1V
+SIN 0V 1V 1000Hz 0 0 0
R_R13 N00241 N01480 1.5k
R_R14 N00061 N00044 220k
**** RESUMING "common source-fet-schematic1-common source-fet.sim.cir" ****
53
.INC "common source-fet-SCHEMATIC1.als"
**** INCLUDING "common source-fet-SCHEMATIC1.als" ****
.ALIASES
J_J1 J1(d=N00069 g=N00044 s=N00107 )
R_R4 R4(1=0 2=N00107 )
R_R1 R1(1=N00069 2=N00061 )
R_R5 R5(1=0 2=N00044 )
C_C1 C1(1=0 2=N00107 )
C_C3 C3(1=N01480 2=N00044 )
C_C2 C2(1=N00069 2=N00203 )
V_V1 V1(+=N00061 -=0 )
R_R6 R6(1=0 2=N00203 )
V_V2 V2(+=N00241 -=0 )
R_R13 R13(1=N00241 2=N01480 )
R_R14 R14(1=N00061 2=N00044 )
.ENDALIASES
**** RESUMING "common source-fet-schematic1-common source-fet.sim.cir" ****
.END
**** 05/28/14 20:13:13 ********* PSpice 9.0 (Nov 1998) ******** ID# 0 ********
** circuit file for profile: common source-fet
**** Junction FET MODEL PARAMETERS
******************************************************************************
J2N3819
NJF
VTO -3
BETA 1.304000E-03
LAMBDA 2.250000E-03
IS 33.570000E-15
ISR 322.400000E-15
ALPHA 311.700000E-06
VK 243.6
RD 1
RS 1
CGD 1.600000E-12
CGS 2.414000E-12
M .3622
54
VTOTC -2.500000E-03
BETATCE -.5
KF 9.882000E-18
**** 05/28/14 20:13:13 ********* PSpice 9.0 (Nov 1998) ******** ID# 0 ********
** circuit file for profile: common source-fet
**** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.000 DEG C
******************************************************************************
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
(N00044) 4.7222 (N00061) 20.0000 (N00069) 8.9240 (N00107) 6.2480
(N00203) 0.0000 (N00241) 0.0000 (N01480) 0.0000
VOLTAGE SOURCE CURRENTS
NAME CURRENT
V_V1 -2.909E-03
V_V2 0.000E+00
TOTAL POWER DISSIPATION 5.82E-02 WATTS
JOB CONCLUDED
TOTAL JOB TIME .34
RESULT:
Thus a Common Source Amplifier in ORCAD PSPICE is simulated and it’s frequency
response characteristics is obtained.
55
EXP. NO : 9 (a) DATE:
BCD TO EXCESS-3 CODE
Aim : To design and implement BCD to Excess-3 code converter
Components Required :
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. NOT GATE IC 7404 2
2. AND GATE IC 7408 1
3. OR GATE IC 7432 2
4. XOR GATE IC 7486 2
5. IC TRAINER KIT - 1
6. PATCH CORDS - 35
OVERVIEW :
Numeric codes represent numeric information i.e. only numbers as a series of 0’s and 1’s.
Numeric codes used to represent decimal digits are called Binary Coded Decimal (BCD) codes. A
BCD code is one, in which the digits of a decimal number are encoded-one at a time into group of
four binary digits. Since there are a large number of BCD codes in order to represent decimal digits
0, 1, 2,……9, it is necessary to use a sequence of at least four binary digits. An Excess-3 code is
a non-weighted code. It is also a self-complementing BCD code used in decimal arithmetic units.
. The Excess-3 code for the decimal number is performed in the same manner as BCD except that
decimal number 3 is added to the each decimal unit before encoding it to binary.
The availability of a large variety of codes for the same discrete elements of information
results in the use of different codes by different digital systems. It is some time necessary to use
the output of one system as the input to the other. The conversion circuit must be inserted between
the two systems if each uses different codes for the same information. Thus a code converter is a
circuit that makes the two systems compatible even though each uses a different code.
56
TRUTH TABLE:
Decimal
Number
BCD Input Excess – 3 Output
B3 B2 B1 B0 E3 E2 E1 E0
0
1
2
3
4
5
6
7
8
9
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
57
K-Map for E3:
E3 = B3 + B2B0 + B2B1
E3 = B3 + B2 (B0 + B1)
K-Map for E2:
58
K-Map for E1:
K-Map for E0:
59
LOGICAL REPRESENTATION
PROCEDURE:
(i) Give connections as per circuit diagram.
(ii) Apply logical inputs as given in the truth table
(iii) Observe the logical output and verify with the truth table.
RESULT:
Thus a BCD to Excess-3 code converter is designed and implemented.
60
EXP. NO : 9 (b) DATE:
EXCESS-3 TO BCD CODE
Aim : To design and implement Excess-3 to BCD converter using logic
gates.
Components Required:
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1 NOT GATE IC 7404 2
2 AND GATE IC 7408 2
3 OR GATE IC 7432 2
4 X-OR GATE IC 7486 2
5 IC TRAINER KIT - 1
6 PATCH CORDS - 35
OVERVIEW :
Numeric codes represent numeric information i.e. only numbers as a series of 0’s and 1’s.
Numeric codes used to represent decimal digits are called Binary Coded Decimal (BCD) codes. A
BCD code is one, in which the digits of a decimal number are encoded-one at a time into group of
four binary digits. Since there are a large number of BCD codes in order to represent decimal digits
0, 1, 2,……9, it is necessary to use a sequence of at least four binary digits. An Excess-3 code is
a non-weighted code. It is also a self-complementing BCD code used in decimal arithmetic units.
. The Excess-3 code for the decimal number is performed in the same manner as BCD except that
decimal number 3 is added to the each decimal unit before encoding it to binary.
The availability of a large variety of codes for the same discrete elements of information
results in the use of different codes by different digital systems. It is some time necessary to use
the output of one system as the input to the other. The conversion circuit must be inserted between
the two systems if each uses different codes for the same information. Thus a code converter is a
circuit that makes the two systems compatible even though each uses a different code.
61
TRUTH TABLE:
| Excess – 3 Input | BCD Output |
X1 X2 X3 X4 A B C D
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
62
K-Map for A:
A = X1 X2 + X3 X4 X1
K-Map for B:
63
K-Map for C:
K-Map for D:
64
LOGICAL REPRESENTATION
PROCEDURE:
(i) Give connections as per circuit diagram.
(ii) Apply logical inputs as given in the truth table
(iii) Observe the logical output and verify with the truth table.
RESULT:
Thus an Excess-3 to BCD code converter is designed and implemented.
65
EXP. NO : 9 (c) DATE:
BINARY TO GRAY CODE
Aim : To design and implement Binary to Gray code converter
Components Required :
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. XOR GATE IC 7486 3
2. IC TRAINER KIT - 1
3. PATCH CORDS - 35
OVERVIEW :
Each code uses four bits to represent a decimal digit. There are four inputs and four
outputs. Gray code is a non-weighted code.
The input variable are designated as B3, B2, B1, B0 and the output variables are designated
as G3, G2, G1, Go and from the truth table, the combinational circuit is designed. The Boolean
functions are obtained from K-Map for each output variable.
A two-level logic diagram may be obtained directly from the Boolean expressions derived
by the maps. These are various other possibilities for a logic diagram that implements this circuit.
The availability of a large variety of codes for the same discrete elements of information results in
the use of different codes by different digital systems. It is some time necessary to use the output
of one system as the input to the other. The conversion circuit must be inserted between the two
systems if each uses different codes for the same information. Thus a code converter is a circuit
that makes the two systems compatible even though each uses a different code.
66
TRUTH TABLE:
| Binary input | Gray code output |
B3 B2 B1 B0 G3 G2 G1 G0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
67
K-Map for G3:
G3 = B3
K-Map for G2:
68
K-Map for G1:
K-Map for G0:
69
LOGICAL REPRESENTATION
PROCEDURE:
(i) Give connections as per circuit diagram.
(ii) Apply logical inputs as given in the truth table
(iii) Observe the logical output and verify with the truth table.
RESULT:
Thus a Binary to Gray code converter is designed and implemented.
70
EXP. NO : 9 (c) DATE:
BINARY TO GRAY CODE
Aim : To design and implement Binary to Gray code converter
Components Required :
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. XOR GATE IC 7486 3
2. IC TRAINER KIT - 1
3. PATCH CORDS - 35
OVERVIEW :
Each code uses four bits to represent a decimal digit. There are four inputs and four
outputs. Gray code is a non-weighted code.
The input variable are designated as B3, B2, B1, B0 and the output variables are designated
as G3, G2, G1, Go and from the truth table, the combinational circuit is designed. The Boolean
functions are obtained from K-Map for each output variable.
A two-level logic diagram may be obtained directly from the Boolean expressions derived
by the maps. These are various other possibilities for a logic diagram that implements this circuit.
The availability of a large variety of codes for the same discrete elements of information results in
the use of different codes by different digital systems. It is some time necessary to use the output
of one system as the input to the other. The conversion circuit must be inserted between the two
systems if each uses different codes for the same information. Thus a code converter is a circuit
that makes the two systems compatible even though each uses a different code.
71
TRUTH TABLE:
| Binary input | Gray code output |
B3 B2 B1 B0 G3 G2 G1 G0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
72
K-Map for G3:
G3 = B3
K-Map for G2:
73
K-Map for G1:
K-Map for G0:
74
LOGICAL REPRESENTATION
PROCEDURE:
(i) Give connections as per circuit diagram.
(ii) Apply logical inputs as given in the truth table
(iii) Observe the logical output and verify with the truth table.
RESULT:
Thus a Binary to Gray code converter is designed and implemented.
75
EXP. NO : 9 (d) DATE:
GRAY TO BINARY CODE
Aim : To design and implement Gray to Binary code converter
Components Required :
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. XOR GATE IC 7486 3
2. IC TRAINER KIT - 1
3. PATCH CORDS - 35
OVERVIEW :
Each code uses four bits to represent a decimal digit. There are four inputs and four
outputs. Gray code is a non-weighted code.
The input variable are designated as G3, G2, G1, Go and the output variables are designated
as B3, B2, B1, B0 and from the truth table, the combinational circuit is designed. The Boolean
functions are obtained from K-Map for each output variable.
A two-level logic diagram may be obtained directly from the Boolean expressions derived
by the maps. These are various other possibilities for a logic diagram that implements this circuit.
The availability of a large variety of codes for the same discrete elements of information results in
the use of different codes by different digital systems. It is some time necessary to use the output
of one system as the input to the other. The conversion circuit must be inserted between the two
systems if each uses different codes for the same information. Thus a code converter is a circuit
that makes the two systems compatible even though each uses a different code.
76
TRUTH TABLE:
| Gray Code | Binary Code |
G3 G2 G1 G0 B3 B2 B1 B0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
77
K-Map for B3:
B3 = G3
K-Map for B2:
78
K-Map for B1:
K-Map for B0:
79
LOGICAL REPRESENTATION
PROCEDURE:
(i) Give connections as per circuit diagram.
(ii) Apply logical inputs as given in the truth table
(iii) Observe the logical output and verify with the truth table.
RESULT:
Thus a Gray to Binary code converter is designed and implemented.
80
EXP. NO : 10 (a) DATE:
4 BIT BINARY ADDER/ SUBTRACTOR
Aim : To design and implement a 4 bit binary Adder/ Subtractor
Components Required:
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. XOR GATE IC 7486 4
2. 4-Bit Binary Full Adder IC 7483 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 35
OVERVIEW :
4 BIT BINARY ADDER:
A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers.
It can be constructed with full adders connected in cascade, with the output carry from each full
adder connected to the input carry of next full adder in chain. The augends bits of ‘A’ and the
addend bits of ‘B’ are designated by subscript numbers from right to left, with subscript 0 denoting
the least significant bits. The carries are connected in chain through the full adder. The input carry
to the adder is C0 and it ripples through the full adder to the output carry C4.
4 BIT BINARY SUBTRACTOR:
The circuit for subtracting A-B consists of an adder with inverters, placed between each
data input ‘B’ and the corresponding input of full adder. The input carry C0 must be equal to 1
when performing subtraction.
4 BIT BINARY ADDER/SUBTRACTOR:
The addition and subtraction operation can be combined into one circuit with one common
binary adder. The mode input M controls the operation. When M=0, the circuit is adder circuit.
When M=1, it becomes subtractor.
81
PIN DIAGRAM FOR IC 7483:
82
TRUTH TABLE:
Input Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
83
LOGICAL REPRESENTATION
PROCEDURE:
(i) Give connections as per circuit diagram.
(ii) Apply logical inputs as given in the truth table
(iii) Observe the logical output and verify with the truth table.
RESULT:
Thus a a 4 bit binary Adder/ Subtractor is designed and implemented.
84
EXP. NO : 10 (b) DATE:
BCD ADDER USING IC 7483
Aim : To design and implement a BDC adder using IC 7483.
Components Required:
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. AND GATE IC 7408 2
2. OR GATE IC7432 2
3. XOR GATE IC 7486 4
4. 4-Bit Binary Full Adder IC 7483 2
5. IC TRAINER KIT - 1
6. PATCH CORDS - 35
OVERVIEW :
Consider the arithmetic addition of two decimal digits in BCD, together with an input carry
from a previous stage. Since each input digit does not exceed 9, the output sum cannot be greater
than 19, the 1 in the sum being an input carry. The output of two decimal digits must be represented
in BCD and should appear in the form listed in the columns. The 2 decimal digits, together with
the input carry, are first added in the top 4 bit adder to produce the binary sum.
85
PIN DIAGRAM FOR IC 7483:
86
TRUTH TABLE:
BCD SUM CARRY
S4 S3 S2 S1 C
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
87
K MAP
Y = S4 (S3 + S2)
LOGICAL REPRESENTATION
88
PROCEDURE:
(i) Give connections as per circuit diagram.
(ii) Apply logical inputs as given in the truth table
(iii) Observe the logical output and verify with the truth table.
RESULT:
Thus a BDC adder using IC 7483 is designed and implemented.
89
EXP. NO : 11 (a) DATE:
MULTIPLEXER USING LOGIC GATES
Aim : To design and implement a Multiplexer using logic gates.
Components Required:
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. 3 I/P AND GATE IC 7411 4
2. OR GATE IC 7432 3
3. NOT GATE IC 7404 2
4. IC TRAINER KIT - 1
5. PATCH CORDS - 32
OVERVIEW :
Multiplexer means transmitting a large number of information units over a smaller number
of channels or lines. A digital multiplexer is a combinational circuit that selects binary information
from one of many input lines and directs it to a single output line. The selection of a particular
input line is controlled by a set of selection lines. Normally there are 2n input line and n selection
lines whose bit combination determine which input is selected.
BLOCK DIAGRAM
90
TRUTH TABLE:
DATA SELECT OUTPUT
S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3
FUNCTION TABLE:
S1 S0 Y
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0
Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0
91
LOGICAL REPRESENTATION
PROCEDURE:
(i) Give connections as per circuit diagram.
(ii) Apply logical inputs as given in the truth table
(iii) Observe the logical output and verify with the truth table.
RESULT:
Thus a 4x1 multiplexer using logic gates is designed and implemented.
92
EXP. NO : 9 (b) DATE:
DEMULTIPLEXER USING LOGIC GATES
Aim : To design and implement a Demultiplexer using logic gates.
Components Required :
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. 3 I/P AND GATE IC 7411 4
2. NOT GATE IC 7404 2
3. IC TRAINER KIT - 1
4. PATCH CORDS - 32
OVERVIEW :
The function of Demultiplexer is in contrast to the multiplexer function. It takes
information from one line and distributes it to a given number of output lines. For this reason, the
demultiplexer is also known as a data distributor. Decoder can also be used as a demultiplexer.
In the 1X 4 demultiplexer circuit, the data input line goes to all of the AND gates. The data
select lines enable only one gate at a time and the data on the data input line will pass through the
selected gate to the associated data output line.
BLOCK DIAGRAM
93
TRUTH TABLE:
INPUT OUTPUT
S1 S0 X D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1
94
FUNCTION TABLE:
S1 S0 D
0 0 X → D0 = X S1’ S0’
0 1 X → D1 = X S1’ S0
1 0 X → D2 = X S1 S0’
1 1 X → D3 = X S1 S0
D = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0
95
LOGICAL REPRESENTATION
96
PROCEDURE:
(i) Give connections as per circuit diagram.
(ii) Apply logical inputs as given in the truth table
(iii) Observe the logical output and verify with the truth table.
RESULT:
Thus a 1x4 Demultiplexer using logic gates is designed and implemented.
97
EXP. NO : 12 (a) DATE:
ENCODER
Aim : To design and implement an Encoder using logic gates.
Components Required :
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. OR GATE IC 7432 9
2. IC TRAINER KIT - 1
3. PATCH CORDS - 32
OVERVIEW :
An encoder is a digital circuit that perform the inverse operation of a decoder. An encoder
has 2n input lines and n output lines. In encoder the output lines generates the binary code
corresponding to the input value. In octal to binary encoder it has eight inputs, one for each octal
digit and three output that generate the corresponding binary code.
98
TRUTH TABLE:
INPUT OUTPUT
Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C
1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 1 1 1
99
LOGICAL REPRESENTATION
PROCEDURE:
(i) Give connections as per circuit diagram.
(ii) Apply logical inputs as given in the truth table
(iii) Observe the logical output and verify with the truth table.
RESULT :
Thus an Encoder using logic gates is designed and implemented.
100
EXP. NO : 12 (b) DATE:
DECODER
Aim : To design and implement a Decoder using logic gates.
Components Required :
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. 3 I/P NAND GATE IC 7410 4
2. NOT GATE IC 7404 3
3. IC TRAINER KIT - 1
4. PATCH CORDS - 32
OVERVIEW :
A decoder is a multiple input multiple output logic circuit which converts coded input into
coded output where input and output codes are different. The input code generally has fewer bits
than the output code. Each input code word produces a different output code word i.e there is a
one to one mapping in the truth table. In the block diagram of decoder circuit the encoded
information is present as n input producing 2n outputs bits.
TRUTH TABLE:
INPUT OUTPUT
E A B D0 D1 D2 D3
1 0 0 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0
101
LOGICAL REPRESENTATION
PROCEDURE:
(i) Give connections as per circuit diagram.
(ii) Apply logical inputs as given in the truth table
(iii) Observe the logical output and verify with the truth table.
RESULT:
Thus a Decoder using logic gates is designed and implemented.
102
EXP. NO : 13 (a) DATE:
4 BIT RIPPLE COUNTER
Aim : To construct and verify a 4 Bit Ripple Counter.
LIST OF PARTS :
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. JK FLIP FLOP IC 7476 2
2. IC TRAINER KIT - 1
3. PATCH CORDS - 32
OVERVIEW :
A counter is a register capable of counting the number of clock pulses arriving at its clock
input. Counter represents the number of clock pulses arrived. A specified sequence of states
appears as counter output. This is the main difference between a register and a counter. There are
two types of counter, synchronous and asynchronous. In synchronous counter a common clock is
given to all flip flop and in asynchronous counter the first flip flop is clocked by external pulse
and then each successive flip flop is clocked by the Q output of the previous stage.The clock of
the second stage is triggered by the output of the first stage. Because of inherent propagation delay
time, all flip flops are not activated at same time which results in asynchronous operation.
103
PIN DIAGRAM
TRUTH TABLE:
CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
104
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 1 1
13 1 0 1 1
14 0 1 1 1
15 1 1 1 1
105
LOGICAL REPRESENTATION
PROCEDURE:
(i) Give connections as per circuit diagram.
(ii) Apply logical inputs as given in the truth table
(iii) Observe the logical output and verify with the truth table.
RESULT :
Thus a 4 Bit Ripple Counter is constructed and verified.
106
EXP. NO : 13 (b) DATE:
MOD-10 / MOD-12 RIPPLE COUNTERS
Aim : To construct and verify a Mod-10 and Mod-12 Ripple Counter.
LIST OF PARTS :
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. JK FLIP FLOP IC 7476 2
2. NAND GATE IC 7400 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 32
OVERVIEW :
A counter is a register capable of counting the number of clock pulses arriving at its clock
input. Counter represents the number of clock pulses arrived. A specified sequence of states
appears as counter output. This is the main difference between a register and a counter. There are
two types of counter, synchronous and asynchronous. In synchronous counter a common clock is
given to all flip flop and in asynchronous counter the first flip flop is clocked by external pulse
and then each successive flip flop is clocked by the Q output of the previous stage.The clock of
the second stage is triggered by the output of the first stage. Because of inherent propagation delay
time, all flip flops are not activated at same time which results in asynchronous operation.
107
PIN DIAGRAM
TRUTH TABLE - MOD - 10 RIPPLE COUNTER:
CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
108
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 0 0 0
LOGICAL REPRESENTATION MOD - 10 RIPPLE COUNTER
109
TRUTH TABLE - MOD - 12 RIPPLE COUNTER:
CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 0 0
110
LOGICAL REPRESENTATION MOD – 12 RIPPLE COUNTER
PROCEDURE:
(i) Give connections as per circuit diagram.
(ii) Apply logical inputs as given in the truth table
(iii) Observe the logical output and verify with the truth table.
RESULT :
Thus a Mod-10 and Mod-12 Ripple Counter is constructed and verified.
111
EXP. NO : 14 DATE:
3-BIT SYNCHRONOUS UP COUNTER/DOWN COUNTER
Aim : To design and implement a 3-Bit Synchronous Up Counter/Down Counter.
LIST OF PARTS :
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. JK FLIP FLOP IC 7476 2
2. 3 I/P AND GATE IC 7411 2
3. OR GATE IC 7432 1
4. XOR GATE IC 7486 1
5. NOT GATE IC 7404 2
6. IC TRAINER KIT - 1
7. PATCH CORDS - 35
OVERVIEW :
A counter is a register capable of counting number of clock pulse arriving at its clock input.
Counter represents the number of clock pulses arrived. An up/down counter is one that is capable
of progressing in increasing order or decreasing order through a certain sequence. An up/down
counter is also called bidirectional counter. Usually up/down operation of the counter is controlled
by up/down signal. When this signal is high counter goes through up sequence and when up/down
signal is low counter follows reverse sequence.
112
STATE DIAGRAM:
CHARACTERISTICS TABLE FOR J-K FLIP FLOP:
Q Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
113
TRUTH TABLE:
Input
Up/Down
Present State
QA QB QC
Next State
QA+1 Q B+1 QC+1
A
JA KA
B
JB KB
C
JC KC
0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1
114
K MAP
LOGICAL REPRESENTATION
115
PROCEDURE:
(i) Give connections as per circuit diagram.
(ii) Apply logical inputs as given in the truth table
(iii) Observe the logical output and verify with the truth table.
RESULT:
Thus a 3-Bit Synchronous Up Counter/Down Counter is designed and implemented.
116
EXP. NO : 15 DATE:
SHIFT REGISTERS USING FLIP- FLOPS
Aim : To implement the following Shift Registers using Flip- Flops
Serial in serial out
Serial in parallel out
Parallel in serial out
Parallel in parallel out
LIST OF PARTS :
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. D FLIP FLOP IC 7474 2
2. OR GATE IC 7432 3
3. IC TRAINER KIT - 1
4. PATCH CORDS - 35
OVERVIEW :
A register, capable of shifting its binary information in one or both directions is known as
shift register. The logical configuration of shift register consists of cascaded D-Flip flops with
output of one flip flop connected to input of next flip flop. All flip flops receive common clock
pulse which causes the shift in the output of the flip flop. The simplest possible shift register is
one that uses only flip flop. The output of a given flip flop is connected to the input of next flip
flop of the register. Each clock pulse shifts the content of register one bit position to the right.
117
PIN DIAGRAM:
CHARACTERISTICS TABLE FOR J-K FLIP FLOP:
Q Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
118
SERIAL IN SERIAL OUT:
TRUTH TABLE:
CLK
Serial in Serial out
1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1
LOGICAL REPRESENTATION
119
SERIAL IN PARALLEL OUT:
TRUTH TABLE:
CLK
DATA
OUTPUT
QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1
LOGICAL REPRESENTATION
120
PARALLEL IN SERIAL OUT:
TRUTH TABLE:
CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1
LOGICAL REPRESENTATION
121
PARALLEL IN PARALLEL OUT:
TRUTH TABLE:
CLK
DATA INPUT OUTPUT
DA DB DC DD QA QB QC QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0
LOGICAL REPRESENTATION
PROCEDURE:
(iv) Give connections as per circuit diagram.
(v) Apply logical inputs as given in the truth table
(vi) Observe the logical output and verify with the truth table.
122
RESULT :
Thus the following Shift Registers using Flip- Flops
Serial in serial out
Serial in parallel out
Parallel in serial out
Parallel in parallel out
is implemented and verified.