ADA Conversion Project Oriented Laboratory

7/27/2019 ADA Conversion Project Oriented Laboratory

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lektronik

abor

Laboratory on Digital and Mixed-Signal

Computer-Aided Design Automation

A / D / A Conversion System

Using DE2 and DA2 Boards

Prof. Dr. Martin J. W. Schubert

Electronics Laboratory

Regensburg University of Applied Sciences

Regensburg


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M. Schubert (P)RED: System Design for DSP Using the DE2 and DA2 Boards Regensburg Univ. of Appl. Sciences

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Abstract. A A/D converter and a D/A converter is to beexplained and built using the DE2 and DA2 boards. This documentdetails several modules of the project.

1 Introduction

RequirementAnalysis

ModuleImplementation

SystemDesign

SubsystemDesign

Module

Design

Module

Test

FunctionalTest

IntegrationTest

SystemTest

Iteration

SystemLayer

SubsystemLayer

ModuleLayer

requirements freeze

design freeze

implementation freeze

test freeze

systemrelease

Fig. 1: V-Model as model to precede with coding and testing of the modules.

This tutorial is addressed to three groups of students:1. A//D and D/A conversion with emphfasis on modulation,2. Digital signal processing (DSP) and

3. Digital circuit designusing VHDL [1], [2], [3] and Matlab [4], [5], [6] and the Altera DE2 board [7], [8], [9].

Preconditions: This tutorial presumes that the user is familiar with the authors documentGetting Started with DE2 and DA2 Boards [10]. Furthermore how write state-machinesusing VHDL [11] and Matlab [12] and some cases how to handle fixed-point numbers [13].

Experience has shown that the most important precondition of circuit design is tounderstand the functionality and translate it into a clear schematics. Take a sheet

of paper or any graphics program to do so, name all components and signals,assign bit-widths and the signal-flow directions. Show it to your supervisor.

The organization of this document is as follows:

Chapter 1 introduction,Chapter 2 presents system- and subsystem-layer information.Chapter 3 presents theoretical background andChapter 4 laboratory project tasks on DSP theory, preferably to be solved with Matlab,Chapter 5 module layer: laboratory VHDL project tasks.

Chapter 6 draws relevant conclusion.


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2 System and Subsystem Layer

2.1 Requirement Analysis

ADC DACdigitalanalog analog

Fig. 2.1: Requirement: Analog-to-digital converter (ADC) and digital-to-analog converter(DAC) as interfaces to the analog world for a Field-Programmable Gate Array (FPGA).

Given is the Altera DE2 Evaluation board [7], [8], [9], [10] operating an Altera Cyclone IIFPGA [7], [9]. Interaction with the analog world requires an ADC that converts an analogvoltage to digital and a DAC that converts digital data to analog voltages.


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2.2 System Layer

Uadc,in Udac,outcAdcOutWidth

ADCcDacInWidth

Ddac,in

DAC

(a) (b)

data rate: fs2 data rate: fs2

rate: fs1rate: fs0

engen(enable-flags generator)

mux0sel1

3

en0

mux1sel0

3

en1

mux2sel2

3

en2

clock_50MHz

enable

CLOCK_50

global_reset

101

10010

110010

1

MHzMHzKHzKHzKHzHzHzHz

eff

e

d

ck

q

r

CLOCK_50

global_reset

z-1d d

digital harmonic

oscillator cOscOutWidth

mux

User Logic

Freqclockenablereset

(c)

analog world analog world

c c

global_enable

cDsr

cUsr

dac1doutdac2dout

01234567

display DsAdcOut

DsAdcOut

OscOut

(a)A/D - D/A conversion system, (b)FF design view, (c)FF DSP view, (d)Top-level viewsynthesized by Quartus II 8.1 [7], [9], [16].

Fig. 2.2: Top-level view oc component de2_adac: Sketched (above) synthezied (below).


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Part(a) of the figure illustrates the block diagram of the digital parts of the A/D/A Conversionsystem within the DE2 board, contained in the top-level component de2_adac.

engen: Enable-flag generator:CLOCK_50: input signal, 50MHz clock rate,

global_enable: input global enable, typically connected to push-buttonkey[1],global_reset: input global enable, typically connected to push-buttonkey[0] ,envec(7:0): output-enable vector, envec(x)is '1' for one out of 10xclock cycles.

muxi: 8-input multiplexer:envec(7:0): input signal, envec(x)is '1' for one out of 10xclock cycles.

seli: input select signal, integer range 0...7,eni: output-enable vector, eni=envec(seli). In the de2_adac component the userselectsfs2bysw(2:0)while and the oversampling ratesfs0,fs1are computed.

ADC: ADC (for ModelSim simulation [14], [15] analog part modeled behavioral):

Uadc,in: input voltage, models as VHDL signal of type REAL.en0: input enable signal, determines oversampling frequencyfs0,cDsr: input constant, down-sampling ratio: cDsr = fs0/fs2,

Dadc,out: digital output word of the ADC delivered at data ratefs2.

DAC: DAC (for ModelSim simulation [14], [15] analog part modeled behavioral):Ddac,in: digital output word of the ADC delivered at data rate.en1: input enable signal, determines oversampling frequencyfs1,cUsr: input constant, up-sampling ratio: cUsr = fs1/fs2,Udac,out: analog output voltage, delivered at data ratefs1.

oscillator: A harmonic digital oscillator which can be used to test the DAC without ADC.

display: 7-segment display driver.

Part (b) of the figure illustrates that all flipflops of this design receive the same global resetsignal and the same clock signal. Theglobal_reset, typically connected to push-button key[0]ofDE2board [7], [10]. The clock input of all flipflops will typically driven by signal CLOCK_50, a 50MHz-

clock signal supplied by Altera [7]. A rising clock edge can toggle a flipflop when its enable entry is '1'.

Part (c) of Fig. 2.2 shows the data processing view of a flipflop with a number of cinput/output bits. The sampling frequencyfsis enclosed withinz=ejTwhereat T=1/fs.

Part (d) of Fig. 2.2 shows the comlete system after Top-level view synthesized by Quartus II8.1 [7], [9], [16]..


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2.3 Subsystem Layer

(a)

constant k

integrator quantizer

Yf

lowpass

modulator demodulator

X'

(c)

m


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3 Theoretical Background

3.1 Sampling, Aliasing and Anti-Aliasing Filters

In the analog domain we use indices Aand B, for attenuation and bandwidth, in the digital

domain we use indices Cand Dfor cutoff and damping, respectively.

3.1.1 Required Anti-Alias Attenuation for M-Bit A/D Conversion

The effective voltage of sinusoidal signal with Amplitude is:2

,U

U effs

)

= .

This sinusoidal voltage has a peak-to-peak voltage of 2.

Assuming that this 2 exactly cover the input voltage range of a M-bit ADC, then this

voltage span is subdivided into 2M

-1 2M

steps of size MMUU

2

2

12

2 ))

= .

Assuming that quantization errors have the same probability to occur within the interval

-/2.../2, then the effective quantization noise voltage is32

,

=effqU (p.336 of [21]).

Inserting the model for delivers3232

2/2

32, M

M

effqUU

U

))

==

= Consequently, the signal-

to-noise ratio caused by the ADCs quantization process is

22

,

,

23

2

=

== M

effq

effs

noise

signal

U

U

P

PSNR

==

23

2log20)(log10 1010M

dB SNRSNR

As a factor 2 corresponds to one bit on the one hand and to ( ) dB0206.62log20 10 = on the

other, and a factor 2/3 corresponds to dB7609.12/3log20 10 = , the signal-to-noise ratio

produced by the quantization process of a M-bit quantizer can be expressed as

dBMSNRSNRdB )76.102.6()(log10 10 +== .

If the signal power of sin(2ft) has to be attenuated to the quantization-noise power of aleast significant bit (LSB or ) forf fA, then the required attenuation of such frequencies is

( )dBMSNRA dBdB 76.102.6 +== .

If the power of an aliasing signal sin(2ft) has to be suppressed to the impact of a half LSBof the ADC, then the required attenuation forf fAis

( ) ( )dBMdBMAdB 78.702.676.102.6)1( +=++= .


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3.1.2 Required Order of Anti-Aliasing Filters

Bandwidth fB denotes the filters pass-band.Stop-band attenuation A is guaranteed for

f fA and AdB=20log10(A).

Assume equal amplitudes at the filters input.Then UBthe pass-band and UAthe attenuatedstop-band output amplitude, so thatUAAUB.

lH(jf)l / dB

0

AdBlog ffAfB

Fig. 3.1.2: lowpass asymptotes.

Abbreviating "log10" with "lg" the required filter order is

B

A

dB

BA

BA

BA

BA

f

fdB

AffUU

ffUUN

lg20

||)/lg()/lg(

)lg()lg()lg()lg(

==

With function ceilfor rounding up minimum filter order is

=

B

A

dB

f

fdB

AceilN

lg20

||

Example:AdB= -60dB, fB=2KHz, fA= 8 KHz Nceil(4.98) N = 5.Consequences: ADCs use high sampling rates to relax the demands of analog anti-aliasing filters. Principle: fA in the formula above is replaced by fA=fs-fD with fs being thesampling rate andfs2fD. Consequently, filter-order reduction is proportional to

N ~ 1/log((fs-fD)/fB) 1/log(fs) if fs.

For moderate sampling rates fs, when the slope of the log function is large, the success is

strong but decreases with increasingfs. On the other hand, we will see in chapter 3.2 that thecosts of digital anti-aliasing filters increase ~fs2 but can be alleviated by using zeros of

particular filters (so-calledsinc-filters). Search the optimum solution on system level.

Practical Comment:If anti-aliasing filtering is necessary, a Butterworth filter is appropriate.It has a flat baseband transfer function and 3dB attenuation in the asymptotes kink at fB,independently from filter orderN.

Butterworth lowpass transfer function:N

B

BWff

jfH2)/(1

1|)(|

+= .


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3.1.3 Matching Analog Anti-Aliasing and Digital Lowpass Filters

fC fs/2fsfD fn1

f'n

aliasingdigital lowpass

digital lowpass

lHfilterl / dB

fs+fDfs-fC fs+fC

0

AdBffB fA=

fs-fD

fn2

analog anti-aliasing filter

Fig. 3.1.3: Necessity for an analog anti-aliasing filter: Guarantee sufficient attenuation atfA=fs-fDto suppress aliasing e.g. fromfntof'n.

Sampling at frequency fsaliases frequencies fn> fs to f'n= |fn-kfs| with kbeing an integral

number such that f'n< fs. A sampler followed by a digital filter with cutoff frequency fCand desired damping reached atfDwill alias all frequencies in the bands kfsfDinto the range0...fD. To avoid this an analog anti-aliasing filter has to be applied before the sampler thatguarantees the desired suppression of alias noise as illustrated by the red dashed curve inFig. 3.1.3.

For this reason, most A/D conversion systems have analog anti-aliasing lowpasses before thesampler. An exception are ADCs: Due to their high sampling frequency they have no orvery relaxed anti-aliasing lowpasses in the analog domain and perform the lowpass filteringafter sampling in the digital domain. Pushing circuitry from the analog to the digital domain isa main reason for their high acceptance for practical applications.

3.1.4 Examples: Tailoring Analog Anti-Aliasing Filters

Exercise 1: Given is a 8-bit ADC. Aliasing noise power must not exceed the quantizationnoise power of a half LSB. What is the required attenuation of aliasing frequencies?

...............................................................

...............................................................

Exercise 2: Situation sketched in Fig. 3.1.4(a): The ADC feeds a telecommunication line,sampling frequency fs=8KHz, baseband edge fB=3.4KHz. What is the required order of theanalog anti-aliasing filter?

...............................................................

...............................................................

...............................................................


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fC fs/2fsfD fn1f

'n

aliasingdigital lowpass

digital lowpass

lHfilterl / dB

fs+fDfs-fC fs+fC

0

ffB fA=

fs-fD

fn2

analog anti-aliasing filter

AdB

(a)

(b)

fB fsfA

fn1f'n

aliasinganalog anti-aliasing filter

lHfilterl / dB

0

AdBf

fs/2

2fsfn2 fn3 fn4

Fig. 3.1.4: Demands for an analog anti-aliasing filter: Guarantee sufficient attenuation atfA=fs-fDto suppress aliasing signals e.g. fromfnxtof'n.

Exercise 3: Situation sketched in Fig. 3.1.4(b): The bandwidth available for thetelecommunication customer remains unchanged at 3.4KHz but will be limited by a digitalfilter: Cutoff frequency fC=3.4KHz, required damping DdB=AdB to be reached at fD=4KHz,

sampling frequency fs= 500KHz. The analog anti-aliasing filters bandwidth is set tofB=16KHz. (It has to be > 3.4KHz but should not attenuate this frequency). What is therequired order of the analog anti-aliasing filter?

Bandwidth of the analog anti-aliasing lowpass:

fB= .........................................................

Attenuation frequency of the lowpass:

fA= .........................................................

Required order of the anti-aliasing lowpass:

N = .........................................................


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3.2 Considerations for Digital Anti-Alias Filtering

In the digital domain we are interested in relativefrequencies F = f/fs=fT rather than the absolutefrequencyfor the sampling frequency fs=1/T. According

to Shannon and Nyquist the relative frequency range isF=0..., becauseF> is subject to aliasing. Figure 3.2.1illustrates with F= that we need 1/F clock cycles and(1+1/F) taps to sample one time period of a wave withfrequencyFand consequently - wavelength 1/F.

t

x

0 1 2

43

Fig. 3.2.1:sampled waveform

A digital lowpass with pass-band FB=fB/fshas to suppress frequencies F > FB. It is a rule ofthumb that the minimum length of a lowpasses impulse response is 1/FBor larger. Dependingon selectivity (i.e.FA/FB) stop-band attenuation and pass-band-ripple the required filter lengthmay be 5...10*1/FB.

Frequencydomain:

fs0= 10fs2= 50fB.

lH(jf)l / dB

0

ffs2fB fs00

Fig. 3.2.2: Top: Frequency situation: The same real world bandwidth fB = fs2/5 = fs0/50.Matlab screen copy, top: FIR lowpass impulse response with a length of 3 wavelengthsof fB, sampled top: withfs2=5fB(15 taps) and bottom withfs0=50fB.(151 taps).

Fig. 3.2.2 demonstrates the problem of digital oversampling and anti-alias filtering. It showstwo FIR lowpasses, both with cut-off frequency fBand an impulse response length of 3/fBin

the time-domain, operated at sampling ratesfs2andfs0=10fs2.


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The upper impulse response is designed for a sampling rate offs2=5fBFB0=0.2.A FIR impulse response comprising 3 wave-lengths requires 3/FB0+1=16 taps.

The lower impulse response is designed for a sampling rate offs0=10fs2=50fBFB=0.02.A FIR impulse response comprising 3 wave-lengths requires 3/FB+1=151 taps.

For every output sample the filter has to perform one multiplication and one addition, termeda MAC (multiply and accumulate) operation. With increasing sampling clock speed thenumber of MAC operations increases also. Consequently, the number of required MACoperations per second, RMAPS, increases quadratic with sampling frequency fs. Consequently,the number of required multipliers increases quadratic withfsalso:Nmult= RMAPS/PMAPS, with

PMAPSbeing the possible number of MAC operations per second and multiplier.

ADCs typically require some more power than other ADCs. This is due to the high clock frequency and required anti-aliasing filters in the digital domain. On the other hand, power consumption and hardware effort must be seen in face of thefact that ADCs need no or significantly relaxed anti-aliasing filters in the analog domain.

Fig. 3.2.2 illustrates the problem for a required decimation factor of 10, but we may needsome 100. This is expensive from hardware costs and power consumption point of views. Onesolution may be to decimate the sampling rate step by step with lowpasses having acceptablerelative cut-off frequencies FB. However, taking advantage ofsincfilter zeros is cheaper.

3.3 Aliasing at Digital Re-Sampling

t10

t

(a) (b)

Fig. 3.3.1: (a)Data rate 1/N decimation symbol: N, (b)factor 10 decimation, time domain.

In Fig. 3.3.1 we decimated the data rate by a factor 10 from fs0 to fs2without prior lowpassfiltering. The consequence is aliasing of frequencies > fs2 to |fs0-kfs2| with k being anintegral number chosen such, that the result is fs2. Applying the 16-tap lowpass of Fig.3.2.2 obtains the transfer characteristics illustrated in Fig. 3.3.2. All noise in the pass-bandsaroundF=1x, 2x, 3x, ... aliases toF=x.

Fig. 3.3.2:Lowpass characteristics forF=0-11. Due to symmetry it is enough to plotF=0-.


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3.4 Application of Sinc Filters for Decimation

Fig. 3.4.1:Decimation with sinc filter. Theirname is due to their frequency domain shape.

10sincfilter

low-pass

fs0 fs0 fs2 fs2

A digital signal processing (DSP) system reduces the data rate by a factorR=10 fromfs0=Rfs2to fs2. Opposite to the situation in the previous subsection this decimation happens afterapplication of a sinc filter as illustrated in Fig. 3.4.1. The sinc filter is particularly easy to

build and is designed such, that its zeros fall ontofz,n=nfs2with n=1,2,3,4... with exception ofmR. This is illustrated in the top of Fig. 3.4.2, left with linear and right on logarithmicordinate. After removing (R-1) out ofRdata samples the lowpass with characteristics shownin Fig. 3.3.2 is applied. In Fig. 3.4.2 this lowpass is plotted in the second row.

The lowpass operated atfs2outputs a samples withfs2corresponding toFs2=1 and a baseband

spectrumFB=0...0.5 in Fig. 3.4.2 below. However, all higher frequencies alias into this range.To avoid this, the sinc filter employed as anti-alias filter at the high sampling frequency fs0suppresses with its zeros the pass-bands of the lowpass aroundF0=1,2,3,4,... The combination

between sinc filter and lowpass is illustrated at the bottom of Fig. 3.4.2. The sinc filtersuppresses the periodic maxima of the lowpass for nfs2with exception of n=mR.

Fig. 3.4.2 shows that less than 20dB suppression of aliasing frequencies as can be seen fromthe logarithmic plot in the right hand side of the figure. The three main possibilities toimprove the situation are using a higher order sinc filter, a narrower or more suitable lowpass.

Fig. 3.4.2: Top-down: |Hsinc|, |Hlowpass|, |HsincHlowpass|,left: linear ordinate,right: in dB.


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3.5 Optimizing Sinc Filters for Decimation

3.5.1 Down-sampling after Decimation

(a)

10sinc

filter 1low-pass

fs0 fs0 fs2 fs2sincfilter 2

sincfilter L

fs0

sincLfilter

(b)

Fig.

3.5.1(a): Decimation withsincLfilter(b):sincL-lowpass optimization. left: Fg0=f/fs1=0.2,right: Fg0=0.125. Top-down:L=

1,2,3,4 for dB(|Hsinc|L|Hlp(Fg0)| ). Black: Hsinc

L, blue: Hlp, red: HsincLHlp

In this subsection we useLsincfilters in series as illustrated in Fig. 3.5.1(a) yielding asincLfilter characteristics in the frequency domain. As a rule of thumb it is recommended to use

L=M+1 sinc filters after a modulator of order M. Fig 3.5.1(b) shows 8 subplots withcharacteristics H(sincL) in black, the lowpass characteristics H(lowpass) in blue and the

product H(sincL)H(lowpass) in red for f=0...fs0F0=0...1.

Variation ofFg=fg/fs0:

The column on the left hand side in Fig. 3.5.2 uses the known lowpass withFg=0.2.The column on the right hand side uses a lowpass withFg=0.125.

Variation ofL:The rows in the figure below use from top to downL=1,2,3 and 4.

The goal of optimization is to have the desired baseband without excessive attenuation in thebasebandF=0...FBand sufficient attenuation in the rangeF=(1-2FB)...1. When using Matlabsfilter design & analysis (FDA) toolbox [4] a particular lowpass that compensates the passband

droop atFgcan be designed using the command d=fdesign.decimator('specification').


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3.5.2 Cascaded-Integrator-Comb (CIC) Filter

z-1

fs0

Dsr

fs1

L integrators

z-1

fs2fs0

sincLfilter

z-1

fs0

z-1

L differentiators

YX

fs2

fs2 fs2

(a)

z-1

fs0

Dsr

fs1

L-1 integrators

z-1

fs2fs0

sincLfilter

z-1

fs0z-1

L-1 differentiators

YX

fs2

fs2 fs2

(b)1 accumulate & daump

= fs0/ Dsr

= fs0/ Dsr

Fig. 3.5.2: (a) Down-sampling done within the middle of integrators and differentiators.(b) Practically we incorporate one accumulate & dump filter.

Eugene B. Hogenauer [22] demonstrated a very efficient way to implement a sincL filter(which is made up of aLcascadedsincfilters) for the particular case that the decimation filterlength equals the down-sampling ratioDsr. ThesincLfilter in Fig. 3.5.1(a) is described by theformula. The formula describing thesincLfilter

Dsrz

zzH

LDsr

cL1

1

1)(

1sin

=

can be re-written as

( )Dsr

zz

zH LDsr

L

cL1

11

1)(

1sin

=

The realization of (1-z

-Dsr

) would requireDsrdelay elements before down-sampling accordingto Fig. 3.5.1(a), but only 1 delay element after down-sampling by Dsr, as illustrated byFig. 3.5.2(a), because the sampling interval after down-sampling is accordingly longer.Practically we save hardware by realizing the last integrator with one additional multiplexeras accumulate & dump filter (see next chapter) and save a differentiator.

Problem: The integrators will overflow. This doesnt matter and can be accepted when: We use an arithmetic (e.g. as 2-complement) where

smallest number 1 = largest number largest number + 1 = smallest number.

The registers bit-width within the total CIC filter is

W L log2(Dsr) + WX with WX being the bit-width of filter inputX.


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3.6 Using Sinc Filters for Interpolation

t

t

t

10

(a)

10 sinc

filter 1low-pass

fs0 fs0fs2fs2

sincfilter 2

sincfilter L

fs0

sincLfilter(c)

(b)

fill in zerosincrease fsand

after sinc1

Fig. 3.6.1: (a) low sampling rate fs0 is (b) up-sampled by including zero-taps and(c) subsequent interpolation using with asincLfilter or a lowpass.

To increase the sampling frequency fromfs0tofs2=Rfs0we confine the bandwidth atfs0with alowpass, include (R-1) zero-samples between the existing pulses and then apply sinc filtersfor interpolation at the high sampling frequencyfs2. The transfer characteristics obtained andthe subsequent considerations are exactly the same as for the decimation case discussedabove.

Of course, we could use a 'simple' lowpass after inclusion of the (R-1) zero-pulses. In thiscase the problems with MAC operations increasing quadratic with fs2is exactly the same asdiscussed for decimation in subsection 3.2.


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3.7 SincFilter Construction

3.7.1 SincFilter as Particular FIR filter

Z-1 Z-1 Z-1

a1 a2 aK

Z-1 Z-1 Z-1

a

xinxin

yout

yout

(a) (b)

1 2 K

(c)

a0

0

Fig. 3.7.1: (a)General FIR filter, (b)sincfilter, (c)sincfilter impulse response

Fig. 3.7(a) show a general finite impulse response (FIR) filter. If all coefficients are identical,i.e. a1=a2=...=aK=: a, we can factor out a to get the topology shown in Fig. part (b). Ifa=1/Kthis is a moving averager and a DC amplification of 1. Typically we do not performthe multiplication with 1/Kand say instead that the filter has a DC amplification ofK.

The impulse response is rectangular and consequently the transfer function as its Fouriertransformed is sinc shaped giving this filter its name. It is also called moving averager(typically with a=1/K) or decimation filter due to its application. The particular suitability fordecimation are its useful zeros and the realization without multiplier. The factor a at theoutput is practically realized by simply removing some trailing bits by truncation or rounding.

General FIR filter formula forK+1 impulse-response taps corresponding to filter order K:

=++++==

K

i

ii

KKgeneral zazazazaazH

0

22

110 ...)( (3.1)

In case of a sinc filter this reduces to

==

K

i

ic zazH

0sin )( (3.2)

which can be shown to be identical to

1

)1(

sin1

1)(

+

=

z

zaKzH

K

c (3.3)


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3.7.2 SincFilter Composed of Combined Comb-Filter

Fig. 3.7.2:K-th ordersincfilterconstructed from 2 nested combfilters. Z

-1 Z-1 Z-1xin

yout1 K2

Z-1

Equation (3.3) describes two comb filters, namely a forward comb with (1-z-(K+1)) and abackward combwith (1-z-1), which is the digital integrator. The digital integrator is unstablebecause it hat a pole at zp=1 on the unit circle. This was unstable if there wasnt a zero zn=1,too, which compensates for zp=1. To make these pole-zero compensation work bit-accuratedata processing is absolutely mandatory within the nested loops. Example: If there is afrequency where we accept an error of a half bit per clock cycle due to rounding or truncation,then this error accumulates to 5 million bits per second at a clock frequency of 10MHz.

3.7.3 SincFilter for CIC Topology

Fig. 3.7.3: sinc filtersaving hardware:(a) down-sampling

after thecomplete sinc

filter,(b) down-sampling

betweenintegrator anddifferentiator.

Z-1 Z-1X

1 K2

Z-1

Z-1

fs0 fs0

fs0

(a)

(b)

Z-1

K

fs0

fs2X

Z-1

fs2

YK

fs2fs1

Y

fs2= fs0/K

fs0 fs2

Fig. 3.7.3 demonstrates how to build (a) sinc filter with down-sampling following it and(b) with down-sampling incorporated between integrator and differentiator. The requirements

for CIC filter constructed on this basis are given in chapter 3.5.2 above.


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3.7.4 Accumulate-and-Dump (ACD) SincFilter Before Decimation

(b)

t

t

Z-1

youtxin

(a)

(b)

reset

xin yout

r

Fig. 3.7.4: (a), (b)integrator with reset, (c)time domainsincfilter with decimation

In the optimal case where the down-sampling frequency ratio R=fs0/fs2equals the number oftaps in the sinc filters impulse response, then the sum of the last R samples at fs0 is onesample of the lower frequencyfs2. Therefore, the lastsincfilter in thesinc

Lchain may be anaccumulate-and-dump filter. As illustrated in Fig. 3.7.3(a) and (b): Clear the integrator and

sums (accumulates) the lastRsamples. While the sum is passed (dumped) as sample atfs2theintegrator is cleared again. While for the sinc filters explained previously any R-th outputsample can be used for sub-sampling, it is important for the ACD-type to dump exactly thelast value of the integrator before reset. For synchronous digital design the reset must berealized synchronous without loosing a data sample at the high frequencyfs0.

Advantages of this of sinc-filter type are the single required delay element, self-adaptation tothe frequency ratio Rand stability due to the repeated clearance of the integrator. Previous

sincfilters should have removed aliasing frequencies prior to decimation.

Unfortunately, only the lastsincfilter in thesincL-chain can be realized as ACD-sinc filter.


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3.7.5 Repeated Sampling of the Same Value for SincInterpolation

(a) Samples a lowfrequencyfs2

(b) Up-sampled by afactorR=10 tofs1, newsamples are zero.

(c) After the firstR-tapssincfilter.

t

t

t

Fig. 3.7.5: Up-sampling using onesincfilter:

Fig. 3.7.5 illustrates the up-sampling situation with a sinc filter havingR=fs1/fs2taps impulseresponse:

(a) The data stream at the low frequencyfs1.

(b) The data stream at the r times higher frequencyfs1. Between the samples overtaken fromfs2were (R-1) zero-samples included.

(c) After the first sinc filter with R taps impulse response and a DC amplification of R(corresponding to a=1 in Fig. 3.7.1(b)). The same result can be obtained without sincfilter by simply re-sampling the last sample at fs2 with higher frequency fs1. This isnearly no effort, always stable and with self-adapting filter-length to R. Unfortunately,this is possible only for the first sinc filter in thesincLchain.

A second and third sinc filter in series with DC amplification of 1 would obtain linear andquadratic interpolation, respectively.


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4 Tasks on Signal Processing Theory

4.1 Some Basic Skills Using Matlab

4.1.1 Computing Roots

Fig. 4.1.1:Solutions of 81

8 11 =

Re(z)

j Im(z)z-Plane

1-1

-j

j

Make yourself aware: The solutions of 81

8 11 = are 82

nj

e

for n=0, 1, 2, 3, 4, ...

Check: Is the result of 8 1 non-ambiguous?

..........................................................................

Check: Given is 82

8/

nj

n ez

= . Is the result of 82

8/ )(mn

jm

n ez

=

non-ambiguous for any n, m?

..........................................................................

Consequence: Use integer exponents rather than fractional numbers.

Line 1. Good 2. Good 3. Bad12345

j = sqr t ( - 1) ;F0 = 0 : 1/ 8 : 7/ 8;F1 = 0 : 1/ 64 : 7/ 64;z0 = exp( j *2*pi *F0) ;z1 = exp( j *2*pi *F1) ;

j = sqr t ( - 1) ;

F1 = 0 : 1/ 64 : 7/ 64;z1 = exp( j *2*pi *F1) ;z0 = z1. 8;

j = sqr t ( - 1) ;F0 = 0 : 1/ 8 : 7/ 8;

z0 = exp( j *2*pi *F0) ;z1 = z0. 8;

In the examples above we want a z0 related to sampling frequency fs1 and a z1 related tosampling frequency fs0=8fs1. Consequently the relative frequencies are F0=f/fs1 and F1=f/fs0.

The related phasors are z0=exp(j2F0) and z1=exp(j2F1). As F0=8F1we have z0=(z1)8

andz1=(z0)1/8. Check with Matlab! (Use f i gure(1) ; pl ot ( z0) ; f i gure(2) ; pl ot ( z1) ). Why

is the bad examples result different from the good ones?

..........................................................................

4.1.2 Computing H(s)

Mat l ab>f =10: 1: 10000; s=j *2*pi *f ; Hs = a0+a1*s+. . . +ak*s. k;

4.1.3 Computing H(z)

Mat l ab>F=0: 1e- 4: 0. 5; z=exp( j *2*pi *F) ; Hz = a0+a1*z+. . . +ak*z. k;


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4.2 The Significance of Zeros and Poles in Transfer Functions

4.2.1 Significance of Zeros and Poles in the s-Plane

R

L

C

CL

R

C1L1

CL

L2

C2

Ui Ui Ui

IiUo Uo Uo Uo

(a) (b) (c) (d)

Fig. 4.2.1: Time-continuous circuits with zeros and poles on the jaxis.

Compute poles and zeros for the 4 circuits in the Fig. above. Simulate the circuit and

demonstrate with Spice or Matlab: A zero on the jaxis is a notch in the zero frequency. A pole on the jaxis is an oscillator in the pole frequency.

PS: The author had problems with LTspice, most probably due to round-off errors.

4.2.2 Significance of Zeros and Poles in the z-Plane

Z-1 Z-1 Z-1xin yout1 K2

a 9-level

ADCcombfilter

sincL

filter

R2RDAC

(a) (b)

Uin Uout

fs1 fs2

Fig. 4.2.2: Time-discrete circuits with zeros and poles on the unit circle.

Show analytically: The combfilter in Fig. 4.2.2(a) is described byH(z) = 1 + az-Kand can bemodeled as

H(z) = 1 +z-K |H(z) | = cos(KF) for a= 1

H(z) = 1 -z-K

|H(z) | = sin(KF) for a= -1

Show that this two combfilters have bothKzeros on the unit circle. These zeros describe thenotches of the filters and are equal to the zeros of the sin and cos functions modelingH(z).

Confirm the results with Matlab simulations computing H(z) =H(z) = 1 + az-K for a=1.

Optional:Practical test according to Fig. 4.2.2(b): Build a combfilter with VHDL, downloadit into the DE2 board and confirm the calculated bode diagram by measurements with theBode100 network analyzer. To increase the number of levels delivered by the 9-level ADCappropriatesincLfilter should be used.


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4.3 Sinc-Filter for Decimation

Explain chapter 3.1 3.3, probably begin of 3.4. Support with Matlab simulations.

4.4 Optimization of the Demodulator withsincL

& Lowpass

Explain chapter end of 3.4 3.5. Support with Matlab simulations.

4.5 Sinc-Filter for Up-Sampling

Chapter 3.7.4: Illustrate impulse responses forsincLfilters, L=1,2,3,4.Show how interpolation becomes smoother for higher L.


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5 Module Layer: Laboratory VHDL Project Tasks

5.1 Module Management

5.1.1 Project Overview

Uadc,in Udac,out

Dadc,out

cAdcOutWidth

dsadc

cDacInWidth

Ddac,inDAC

U

Demo-dulator

dsdemod

Inter-polator

dsinterp

Modulator Mo-dulator

Demo-dulator

dsmod

da2_board

D Aanalog

lowpass

DAC

Anal og(DA2 board)

Digital(DE2 board)

fs0> fs2 fs1> fs2fs2

UD D

(a)

(b)

D/A

A/D

dsmodad

ADC

dsdac

clockreset

DsAdcIn DsAdcOut

cOutWidthcInWidth

dsadccCtrlWidthctrl

enable1

clock

enable0

reset

DsDacIn DsDacOut

dsdaccCtrlWidthctrl

(c) (d)

Anal og(DA2 board)

cInWidth cOutWidthcCtrlWidthcInWidth cOutWidthcDsr cCtrlWidth

cInWidth cOutWidth

dsfb

cUsr

Fig. 5.1.1: (a) Analog-to-Digital-to-Analog Conversion system, (b), resolved into

subsystems, (c)Symbol of digital parts of the

ADC and (d)of the

DAC.

Fig. 5.1.1 gives a finer resolution of the digital components used to resolve the mixedanalog/digital A/D and D/A conversion components. For ModelSim simulations behavioralVHDL models are provided for the analog parts, which are physically located on the DA2

board [7].


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5.1.2 Subproject File Structure

tb_counter

counter

de2_counter

tb_de2_counterde2_counter.qpf

ModelSimVHDL Quartus II 8.1

de2_counter.qsf

de2_counter.sof

FPGA

Fig. 5.1.2: de2_counterfits into the DE2 board and instantiates module counter.

The testbenches tb_de2_counterand tb_counterare located in the ModelSimdirectory whilethe Quartus-project file de2_counter.qpf and respective specification file de2_counter.qsfdefine the project from the Altera side. Files named de2_ fit into the DE2 board.After successful compilation the de2_.sof file can be downloaded into the FPGAusing the Quartus II Programmer.


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5.1.3 Project Directory Structure

Matlab

ModelSim

1.counter

Testbenches

compile_adac.do

adac_bin 2.de2_engen

1.de2_counter

behavioral da2_dsdemod.vhd

QuartusII81

VHDL

configurations

architectures

entitys

ADAC

de2_engen

de2_counter

de2_dsmodad

counter

filter

oscillator

optimizations

tb_counter.vhd

tb_de2_counter.vhd

tb_de2_engen.vhd

+counter.vhd de2_counter.vhd

+engen.vhd de2_engen.vhd

rtl_counter.vhd + rtl_de2_counter.vhd

+rtl_engen.vhd rtl_de2_engen.vhd

con_counter.vhd + con_de2_counter.vhd

+con_engen.vhd con_de2_engen.vhd

de2_counter.qpf + de2_counter.qsf

de2_counter.qpf + de2_counter.qsf

de2_dsmodad.qpf + de2_dsmodad.qsf

+f_counter.m tb_counter.m

Fig. 5.1.3: Used file system modeling the addaxproject.


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5.1.4 Assignment of Keys and Switches of the DE2Board

Table 5.1.4:Assignment of switches on theDE2boardswitch Function Comments

Hint: key(x)='0' when pressed key(0:3)are 4 blue, push buttons

key(3)key(2)

key(1) global enablekey(0) global reset

sw(x)='1' when moved toward board sw(0:17) are 18 sliding switchessw(17:16) controls quantization in qdem No.(output_levels)=2^sw(17:16)+ 1sw(15) Simul. Quantiz.-error in Flash ADC sw(15)='0'/'1' : quantiz. error OFF/ONsw(14) Simul. DAC-nonlinearity in qdem sw(14)='0'/'1' : nonlin-error is OFF/ONsw(13) controls Dyn. Elem. Mat. in qdem sw(13)='0'/'1' : DEM is OFF/ONsw(12) inverts Delta-Sigma-Feedback: sw(12)='0' : dsfb


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5.2 9-Level D/A Converter

5.2.1 Flash-DAC Theory

G2U2

G3U3

G4U4

G5U5

G6U6

G7U7

G1U1

G0U0

DAC2out

Gsum

Usrc

DAC2out

(b) (c)(a)

clock

enable

reset

bin08 bits94

dacd

8

ctrl6

Figure 5.2.1: (a)9-level DAC digital part, (b)analog part (c)equivalent analog model

The analog part of the 9-level flash DAC is realized as illustrated in Fig. 5.2.1(b). Fig. part (c)shows its equivalent circuit that can be modeled as

=

==7

0

1

jjsumout GGZ and j

jsrc U

Gsum

GU j

=

=7

0

.

5.2.2 Binary to Thermometric Conversion & DEM

DAC2(9 levels)

1K

Usrc2

4 8

e

ck

d q

r

reset

eff

DE2 Board

81

0

thermometric

ctrl(5:0)

8

2, 3,5, 9level

5

dacd (DAC digital part)

qdembin2therm 8

bin08

dem

6 ctrl(0)

ctrl(5:1)

bits9

demi

resetenable

clock

Udac2

DA2 Board

anal.low-pass

dsmod

DsOut

Figure 5.2.2: (a)9-level DAC digital part, (b)analog part (c)equivalent analog model


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- 29 -

5.3 Digital-to-Analog Converter

5.3.1 1stOrder -D/A Converter

DsIn

quantizer

b

dsmod

cOutWidthcInWidth

DsOut

cOutWidthcInWidth

(a)

clock

enable

reset

DsInDsOut

cOutWidthcInWidth

dsmodctrl

cInWidth cOutWidth

(b)

cCtrlWidth

cCtrlWidth

Fig. 5.3.1:dsmod: (a)1storder modulator topology, (b)symbol.

Realize the quantizer with 9, 5, 3, 2 output levels depending on the ctrl signal. Use ieeepackagestd_logic_unsigned, so that the signal range has positive numbers only.

5.3.2 2nd

Order -D/A Converter

DsIn Uanaloganalog

lowpass

quantizer

DAC

b1

b2

DsOut

Fig. 5.3.2:dsmod: 2ndorder modulator topology with DAC and analog lowpass.

The symbol of modulator is the same as shown in Fig. 5.3.1(b).Use b2=1 and b1=2. In this case average input and output amplitudes will be equal and thefirst (input) integrator will performs double amplitude (x b1).


Illustrate, that the output of a second order modulator will perform jumps over two levels.This is impossible for a single-bit output and the modulator is said to be overloaded. Oppositeto higher order modulators the second order modulator remains stable in case of overloading.


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5.3.3 3rd

Order -D/A Converter

Uanaloganalog

lowpass

quantizer

DAC

b2

b3

b1

DsIn DsOut

Fig. 5.3.3:dsmod: (a)1storder modulator topology, (b)symbol.

The symbol of modulator is the same as shown in Fig. 5.3.1(b).Use b3=1 and b2=b1=3. In this case average input and output amplitudes will be equal and thefirst two integrators will performs three times the input amplitude (x b2).


Illustrate, that the output of a second order modulator will perform jumps over severallevels. If this is not impossible due to a lack of output levels the modulator is said to beoverloaded and becomes instable.


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5.4 -A/D Converter

5.4.1 1stOrder ADC Using a Capacitor as Integrator

FlashADC

(9 levels)

C02C04...C16

DAC3(9 levels)

1K

Usrc3

8

8

from_flash

Dadc,out

DE2 Board

dsfb =NOT(bits9) when sq(3)='0' ELSE bits9

e

ck

d q

r

reset

digit.low-pass cAdcOutWidth

ctrl(5:0)

2, 3,5, 9level

dsmodad( -mod. ADCdigital part)

eff qdem

dsdemod

bits2bin 4

bin08

1 0

ctrl(5:1)

DA2 Board

CP_in_P

DAC3

ou

t

1K

C3

Integrator

Uadc,in

5

6 ctrl(0)

88

Fig. 5.4.1-1: modulator using capacitor C3as integrator.

Project: Code dsmodadand Assemble the Setup

Listing 5.4.1:VHDL ENTITY of the digital part of the -ADC

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - Modul e : dsmodad- - Desi gner : Mar t i n Schuber t- - Dat e l ast modi f i ed: 18. Oct . 2010- - Pur pose : Del t a- Si gma MODul ator ' s Adc Di gi t al part- -- - Constant s : -- - I nput - Si gnal s : r eset : st d_l ogi c, asynchonous, doni nant r eset- - c l ock : std_l ogi c , c l ock s i gnal- - enabl e : std_l ogi c, f l i pf l ops can t oggl e i f enabl e=' 1'- - f r om_f l ash: st d_l ogi c_vector, f r om Fl ash- ADC, t her m. code- - ct r l ( 5: 0) : cont r ol s Quant i zat i on + Dyn. el em. mat chi ng- - ctr l ( 5: 4) : quant i z. l evel s = 2 ctr l ( 5: 4) + 1

- - ctr l ( 3) : =' 0' / ' 1' : Quant i zer- err or OFF/ ON- - ctr l ( 2) : =' 0' / ' 1' : DAC- nonl i near i t y OFF/ ON- - ctr l ( 1) : =' 0' / ' 1' : DEM i s OFF/ ON- - ctr l ( 0) : dsf b=NOT( bi t s9) WHEN ctr l ( 0) =' 0'- - Out put - Si gnal s: dsf b( 7: 0) : st d_l ogi c_vector, DS f eedback, 9- l evel t her m.- - bi n_08_out : Nat ur al , 9- l evel bi nar y coded- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -LI BRARY i eee; USE i eee. st d_l ogi c_1164. ALL;ENTI TY dsmodad I S

PORT( r eset , cl ock, enabl e: I N st d_l ogi c;ct r l : I N st d_l ogi c_vect or ( 5 DOWNTO 0) ;f r om_f l ash: I N st d_l ogi c_vect or ( 7 DOWNTO 0) ;dsf b : BUFFER st d_l ogi c_vector ( 7 DOWNTO 0) ;bi n08_out : BUFFER st d_l ogi c_vector ( 3 DOWNTO 0)

) ;END ENTI TY dsmodad;


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- 32 -

Behavioral Model of the RC-Integrator on the DA2-Board

Fig. 5.4.1-2:

modulatorusing capacitorC3 as inte-grator.(a) Circuit(b) behavioral

model

CP_in_P1KUadc,in

DAC3(9 levels) 1K

Udac3outC3

(a)

Rsrc

Usrc C3

UC3

(b)U_CPinPU_C3

Rpoti19

Rdac3out

The two sources Uadc,inand Udac3outwith output impedances Rpoti19and Rdac3out, respectively,are summarized to form a common resistive source with output Voltage Usrc and outputresistance Rsrc. We obtain

CPinP

outdacoutdacinadcpoti

outdacpoti

outdacoutdacinadcpotisrc G

UGUGGG

UGUGU 33,19319

33,19 +=++=

with Gx=1/Rxand GCPinP=Gpoti19+Gdac3out=1/Rsrc. The current charging C3in Fig. part (b) is thesources output current through Rsrc:

dt

dUCI

R

UU CC

src

Csrc 333

3 ==

Using Rsrc=1/GCPinP and dUC3/dt=(UC3-UC3,last)/TimeStep and a=RsrcC3/TimeStep obtains theactual value of UC3as

a

aUUU lastCsrcC

+

+=

1,3

3

Operating the Hard- and Software:

We need sw(12)=ctrl(0)='0'causing the digital word assigned to dac3dout to be inverted.This is because we need a feedback voltage which is negative with respect to UB=VDD/2.

The modulator requires a feedback loop with high loop gain. It is best to use onecomparator only, i.e. sw(17:16)=ctrl(5:4)=ctrlqd(4:3)="00" , or adjust a smallquantization step of the flash-ADC, e.g. =delta=VDD/64.

Connect the capacitors voltage to the input of the flash-ADC. On theDA2board you haveto set the respective jumper; in the testbench you need to activate the code line thatconnects UCPinPto UC3:

- - U_CPi nP


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5.4.2 ADC Using PSK2- or DS2-Boards OpAmp Integrators

DS2-Board

CP_in_P

DAC3

ou

t

DA2-Board

k

feedback

network

8

8

FlashADC

(9 levels)

C02C04...C16

DAC3(9 levels)

1K

Usrc3

from_flash

Dadc,out

DE2 Board

dsfb =NOT(bits9) when sq(3)='0' ELSE bits9

e

ck

d q

r

reset

digit.low-pass cAdcOutWidth8

thermometric

ctrl(5:0)

8

2, 3,5, 9level

5

dsmodad ( -mod. ADC digital part)

eff qdem

dsdemod

bits2bin 4

bin08bits9

6 ctrl(0)1 0

ctrl(5:1)

Fig. 5.4.2-1: modulator using PSK2-Board to realize a 1stand 2ndorder integrator.

Project: Code dsmodadand Assemble the Setup

Operating the Hard- and Software:

Same componentdsmodadas used for the capacitor C2as integrator. We need sw(12)=ctrl(0)='1' causing the digital word assigned to dac3dout not to be

inverted. This is because we already use the OpAmp OA1 inverting with respect toUB=VDD/2.

The modulator requires a feedback loop with high loop gain which is delivered by theIntegrators for sufficiently low frequencies. Check for different quantization steps delta,i.e. sw(17:16)=ctrl(5:4=ctrlqd(4:3)= "00","01","10","11". Adjust a reasonablequantization step of the flash-ADC, e.g. =delta=VDD/8.

Hardware: Connect the integrators output voltage to the input of the flash-ADC. TheDA2-board will be used to bridge Uerr1on the PSK2-board.

Simulation with ModelSim: The PSK2 board is integrated in the DA2 board model. In the

componentDA2_dsmodadyou have to activate the code line that connects UCPinPto Uint1:U_CPi nP


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- 34 -

R

2U'in

C2R

1

C1

OA2 OA1

Rb1Rb2

DA2-board Flash-ADC

-1

0V 0V

OUT2 OUT1

(c)

U'in(1st order)

(2ndorder)

DA2-board Udac3out

Fig. 5.4.2-2: modulator part on the PSK2-Board.

Illustrate, that a second order modulator needs to jump over more than one of the flash-

ADC to realize its strong high-frequency amplification by noise-shaping. If it cannot performat lest 2-jumps the modulator is said to be overloaded. While an overloaded 2nd ordermodulator remains stable, 3rdand higher order modulators become unstable producing longseries of 1s and 0s.

5.5 Lowpass for Demodulation:dsdemod

Fig. 5.5: dsdemod:

lowpass system for

demodulation

(a) symbol ,

(b) schematicsfs1

sincS1fs1 digital

lowpass

fs2

fs2

DsDemIn

SincDn

cInWidth

DsDemOut

cOutWidth

dsdemod

cMidWidth

clock

enable0

reset

DsDemIn DsDemOutcOutWidthcInWidth

dsdemod

cDsr cOutWidthcInWidth


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5.6 Sinc-based Decimator for Down-Sampling: SincDn

Fig. 5.6:

SincDn:

lowpass fordecimation

(a) symbol ,

(b) schematicsfs1

sinc

fs2

cWidth1

sinc sinc

fs1

sincacc+dump

fs1 fs1

1 2 S1-1 S1

SincDnOutSincDnIn

cInWidth cOutWidth

SincDn(sincS1for down-sampling (decimation))

clock

enable1

reset

SincDnIn SincDnOut

SincDn

cInWidth cOutWidthcTaps

cWidth2

cOutWidthcIn-Width

5.7 Sinc-based Interpolator for Up-Sampling: SincUp

Fig. 5.7:

SincUp:

lowpass forinterpolation

(c) symbol ,

(d) schema-tics

fs0

sinc

fs2

cWidth2

sinc sinc

fs0 fs0

1 3 S02

SincUpOutSincUpIn

cInWidth cOutWidth

SincUp (sincS0for up-sampling (interpolation))

clock

enable0

reset

SincDnIn SincDnOutcOutWidth

SincUp

cInWidth cOutWidthcTaps

cWidth3

cIn-Width

latch

cinWidth


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5.8 SincFilter

5.8.1 Sinc Filter by Simple Summation: SincSum

Z-1 Z-1 Z-1xin

yout

cInWidth

cOutWidth

1 2 K=cTaps

clock

enable

reset

SincIn SincOutcOutWidthcInWidth

sinc+ rtl_SincSum

cTapscInWidth cOutWidth

(b)(a) rtl_SincSum

Fig. 5.8.1:SincSum: (a)sincfilter in combtopology. (b)Symbol of entity sinc, which hasto be combined with architecture rtl_SincSum.

Computing the required bitwidth.

The required bitwidth to represent an integral number 0 xinxmax is ld(xmax+1) withld(x)= log2(x) being the logarithm dualis, that can be computed from ld(x)=logB(x)/logB(2)with any basis B. Typically we compute ld(x)=ln(x)/ln(2). As a fractional bit-vector width,e.g. 2.7 bits, is difficult to realize, the result has to be rounded up, which is done with theceil(ing) function below. Try this equations forxin=0...7 andxin= 0...8:

For 0 xinxmax we need a BitWidth= ceil(ld(xmax+1)) bits,For -xmaxxinxmax we need a BitWidth= ceil(ld(xmax+1)) + 1 bits.

In this project we come with 4 bits out of the flash ADC. If we sum the last 100 samples wecould theoretically get a maximum output number of 100*15=1500 requiring 11 bits.However, the 8-comparator Flash-ADC on the DA2 board delivers a number range of 0...8, sothat 100 of those samples will be 800 and only 10 of the 11 output-bits will be used.

Realizing a sinc3filter in this project, 3 sinc filters have to be used in series. If the next sincfilter sums 100 samples with a number range 0...800 it delivers numbers in the range0...80 000 requiring 17bits to be represented and the 3rdsinc filter in the queue will have anumber range 0...8 000 000 requiring 23 bits. This doesnt make sense when we have an 8bitR2R DAC only to translate that in to an analog signal. Consequently, the output bit-length has

to be rounded to a reasonable number of bits. See for chapter Rounding and Truncation in[13].

VHDL: Show a detailed schematics drawn by hand or with any graphics program to yoursupervisor before coding this component.

Theory: (Ask your supervisor before spending too much time on theory!)

The FIR filter z-Domain representation of a is =+++==

k

i

ii

kk zazazaazH

1

110 ...)( .

Demonstratethat the sinc filter in Fig. 5.8.1(a) can be written as1

1

1

1)(

=

z

zzzH

K

.


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5.8.2 Sinc Filter in Comb Topology: SincComb

Z-1 Z-1 Z-1xin

yout

cInWidth

1 K2

Z-1

clock

enable

reset

SincIn SincOutcOutWidthcInWidth

cTapscInWidth cOutWidth

(b)(a)

sinc+ rtl_SincComb

rtl_SincComb

Fig. 5.8.2:SincComb: (a)sincfilter in combtopology. (b)Symbol of entity sinc, which hasto be combined with architecture rtl_SincComb.

VHDL: Show a detailed schematics drawn by hand or with any graphics program to your

supervisor before coding this component.

Theory: (Ask your supervisor before spending too much time on theory!)

The FIR filter z-Domain representation of the sinc filter in Fig. 5.8.1(a) is1

1

1

1)(

=

z

zzzH

K

.

(i) Demonstrate that this formula leads to the filter shown in Fig. 5.8.2.

(ii) Demonstrate that this formula leads to)(sin

)(sin)(

Fc

KFcKFH = withz=ej2FandF=fT=f/fs.

Stability:

Not that 1/(1-z-1) is an ideal integrator with a pole at zp=1 on the unit circle. Normally thiswas instable but it is stabilized by a zero zn=1 in the denominator. This pole-zerocompensation works if and only if the feedback loop works bit-accurate! Do not round oromit bits within the loop!

What is the required bit-width for the state-vector element (K+1) within the feedback loop?


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5.8.3 Accumulate-and-Dump Sinc Filter: SincAcd

Z-1

youtclock

enable1

reset

SincIn Sin-cOut

cOutWidthcInWidth

SincAcd

cInWidth cOutWidth

(d)(a)

enable2xin

(b)

t

t

fs1

fs2

(d)

Fig. 5.8.3:SincAcd: (a)sincfilter in accumulate & dump topology, (b)symbol of requiredintegrator, (c)integrator circuit, (d)symbol of component SincAcd.

The sincfilter forming the interface from the higher clock rate fs0to the lower clock rate fs1can perform down-sampling (=decimation) by summarizing R taps coming in with fs0 to asingle tap going out with fs1, when R=fs0/fs1. And this is just the optimal situation. In theexample above we haveR=4.

In this case we can reset the integrator to zero, sum Rincoming taps and give (or dump) thesum to the output just before the integrator is reset. The design has to respect the synchronousdesign rules (e.g. no asynchronous reset) while not loosing a tap of the incoming data stream.

Note that we have no constant cTaps as for the other sinc filters, because the summationperiod length adjusts automatically by the ratiofs0/fs1.


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5.8.4 SincFilter by Repeated Sampling the Same Value

(a)

t

t

fs2

fs0(b)

(c)

(d)

t

t

Fig. 5.8.4: Up-sampling fromfs2tofs1=R0fs2(hereR0=4) withsinc-filter interpolation, wherethesincfilters haveR0taps each: (a)Signal at sampling ratefs2, (b)sampling rate increased to

R0fs2by introducing zeros, (c)situation after the first and (d)secondsinc-filter.

To output a signal with a modulator the speed of the data stream has to be increased fromthe baseband-rate fs1 to a higher data rate fs2=R2fs1 as illustrated in Fig. 5.8.4(a). This isnormally done by filling the additional taps of the higher speed signal with zeros as shown inFig. part (b). If the firstsincfilter has an impulse response with R2taps, the situation at theoutputs of the first and secondsincfilters are illustrated in Figs. 5.8.4 (c) and (d) respectively.

The situation shown in Fig. part (c) can also be obtained by repeating sampling last sample ofthe incoming data rate,fs1, instead of filling new taps with zeros.

In conclusion, we can replace the effort for the fist sinc filter by simply re-sampling thevalues of the low, incoming data rate,fs1, with the higher data rate, fs2. This corresponds to aDC-amplification ofR2this firstsincfilter.

To see the interpolating effect of the 2nd, 3rd, 4th...sincfilters in Matlab it is recommended togive them in Matlab a DC amplification of 1. (The DC-amplification of a time-discrete filteris the sum of its impulse-response taps.)


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5.9 Lowpass Filters

Fig. 5.9: Symbolfilter

clock

enable

reset

FilterIn FilterOutcOutWidthcInWidth

filter

Fig. 5.9 shows the symbol for the digital filtercomponent. The many constants required arepassed to the filter by packagepk_filter.

5.9.1 Digital FIR Lowpass in 1

st

Canonic Direct Structure

z-1 z-1

aK

aK-1

a2

a1

z-1ns1

s1

nsK sK s3 s2ns2

FilterCanon1FilterIn

FilterOut

cOutWidth

cInWidth

Fig. 5.9.1:rtl_FilterCanon1: FIR filter in 1stcanonical direct structure,K=cTaps.

It is a finite impulse response (FIR) filter because there is no feedback branch. The filter iscanonic because the order of the polynomial equals the number of delay elements and it is adirect structure, because the impulse response can be directly adjusted with the coefficients.

Show a schematics to your supervisor before coding the filter with Matlab or VHDL.


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5.9.2 Digital FIR Lowpass in 2nd

Canonic Direct Structure

z-1 z-1 z-1

a1

s1

a2

a3

s2 sKns2 ns3 nsK

aKz-1s3ns1

rtl_FilterCanon2

FilterOutFilterin

Fig. 5.9.2:rtl_FilterCanon2: FIR filter in 2ndcanonic direct structure,K=cTaps.

It is a finite impulse response (FIR) filter because there is no feedback branch. The filter iscanonic because the order of the polynomial equals the number of delay elements and it is adirect structure, because the impulse response can be directly adjusted with the coefficients.

Show a schematics to your supervisor before coding the filter with Matlab or VHDL.


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5.10 Digital Quantization & Dynamic Element Matching (DEM)

5.10.1 Digital Quantization

Fig. 5.10.1-1: Symbol of the qdemmodule.

5

qdem_out(7:0)8

qdem

ctrlqd(4:0)

from_flash(7:0)

Listing 5.10.1:VHDL ENTITY qdemlocated within the digital part of the -ADC

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - Modul e : qdem- - Desi gner : Mar t i n Schuber t- - Dat e l ast modi f i ed: 12. Oct . 2010- - Pur pose : f ur t her Quant i zat i on and Dyn. El em. Matchi ng ( DEM)

- -- - Const ant s : cAdcFl ashWi dt h: POSI TI VE, Bi t Wi dt h of Fl sh ADC/ f or DAC- - cOut Bi nWi dt h: POSI TI VE, Bi t Wi dt h bi nary coded ouput- - I nput - Si gnal s : r eset : st d_l ogi c, asynchonous, doni nant r eset- - c l ock : std_l ogi c , c l ock s i gnal- - enabl e : std_l ogi c, f l i pf l ops can t oggl e i f enabl e=' 1'- - ct r l qd( 4: 0) : cont r ol s Quant i zat i on + Dyn. el em. mat chi ng- - ctr l qd( 4: 3) : quant . l evel s = 2 ctr l ( 4: 3) + 1- - ctr l qd( 2) : =' 0' / ' 1' : DAC- nonl i near i t y OFF/ ON- - ctr l qd( 1) : =' 0' / ' 1' : Quant i zer - er r or OFF/ ON- - ctr l qd( 0) : =' 0' / ' 1' : DEM i s OFF/ ON- - f r om_f l ash : st d_l ogi c_vector, f r om Fl ash- ADC, t her m. code- - Out put - Si gnal s: qdem_out : st d_l ogi c_vect or : i nput quant i zed and r andomi zed- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -LI BRARY i eee; USE i eee. st d_l ogi c_1164. ALL;

ENTI TY qdem I SPORT( r eset , cl ock, enabl e: I N st d_l ogi c;ct r l qd : I N st d_l ogi c_vect or ( 4 DOWNTO 0) ;f r om_f l ash: I N st d_l ogi c_vect or ( 7 DOWNTO 0) ;qdem_out : BUFFER st d_l ogi c_vect or ( 7 DOWNTO 0)

) ;END ENTI TY qdem;

The functionalities of component qdemcontrolled by signal ctrlqdare:

1. ctrlqd(4:3): Quantization: Further quantization is performed as illustrated in Fig. 5.10.1-3(a)-(d). The number of output levels is 9, 5, 3, 2 computed from 2ctrlqd(4:3)+1. Hint: It isrecommended to prefer CASE to IF wherever possible. Here it is possible!

2. ctrlqd(2)='1': ADC non-linearity errorby simulated non-linearity of the flash-ADC asillustrated in Fig. 5.10.1-3(e). As the ADC in the forward network of the loop, its non-linearity is suppressed by the noise-transfer function (NTF).

3. ctrlqd(1)='1':DAC non-linearity errorby simulated unbalanced grouping of the outputresistors as illustrated in Fig. 5.10.1-3(f). As the DAC in the feedback network of the loop, its non-linearity is a disaster for the accuracy of the total loop.

4. ctrlqd(0)='1': Dynamic Element Matching compensates for non-linearity error of theDAC as detailed in the next subsection.


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Fig. 5.10.1-2: Possibledistribution of thresholds(blue) for the Flash-ADC.

0 1 2 3 4 5 6 7 8 L

0

3.3 V

2.8875

2.47

2.0625

1.65

1.2375

0.825

0.4125

DAC#out #=2,3 VT(CPs)

3.09375

2.68125

2.26875

1.85625

1.44375

1.03125

0.61875

0.20625

DAC#out

from_flash(7)

from_flash(6)

from_flash(5)

from_flash(4)

from_flash(3)

from_flash(2)

from_flash(1)

from_flash(0)

DAC#out

from_flash(7)

from_flash(5)

from_flash(3)

from_flash(1)

from_flash(5)

from_flash(2)

from_flash(4) DAC#out

from_flash(7)

from_flash(5)

from_flash(3)

from_flash(1)

from_flash(7)

from_flash(5)

from_flash(2)

from_flash(1)

(a)ctrlqd(4:3)="11": 9 level (b)ctrlqd(4:1)="1000": 5 level (c)ctrlqd(4:3)="01": 3 level

(d)ctrlqd(4:3)="00": 2 level (e)ctrlqd(4:1)="1010": ADC nonlin. (f)ctrlqd(4:1)="1001": DAC nonlin.

DAC#out

Fig. 5.10.1-3: Expected output combinations as a function of the control signal ctrlqd(4:0).


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5.10.2 Dynamic Element Matching (DEM)

G2U2

G3U3

G4U4

G5U5

G6U6

G7

G1U1

G0U0

DAC#out,

#=2,3

(b) (c)

4 3 2 4 5 6

(a)

4 3 2 4 5 6

U7

Fig. 5.10.2: (a) No DEM, (b) barrel-shifter technique, (c) application points at DAC#, #=2,3.

The accuracy of the DAC within the loops feedback branch is essential for the accuracyof the total A/D conversion process. To overcome the inaccuracies of the resistors used wemay employ dynamic element matching (DEM).

Fig. 5.10.2(a)illustrates a thermometric-code sequence with 4, 3, 2, 4, 5, 6 out of 8 bits areset to '1'.

Fig. 5.10.2(b)illustrates the same sequence (4, 3, 2, 4, 5, 6 out of 8 bits are set to '1'), but thebarrel of bits rotates around the index space of the output-bit vector. This is called barrel-shifter technique. The advantage of DEM is that all bits are the same time-span ON aninaccuracies can be removed by averaging. The disadvantage of the barrel-shifter method isthat it can generate new, lower-frequency periods. E.g. when a single ON-bit circles. Betterwas to use a random generator to select the indices of the '1'-bits.


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5.11 Enable-Flags Generator

Fig. 5.11: Enable-FlagsGenerator:

(a) Single counter

(b) Enable-flags generatorbased on cascadedcounters.

engen

clock_50MHz

reset

enable envec(7:0)

8counter

clock

reset

enable

count

maxflg

cPeriod

(a) (b)

The enable-flags generator module engen receives a 50MHz clock signal (clock_50MHz), alow-active reset (reset) and an enable signal. It delivers a vector of enable signals(envec(7:0)). Signal envec(i) delivers a 1-clock wide enable signal with frequency f(i)=10iHz.Signal envec(i) comes at the same time as envec(j) for all j


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5.12 Harmonic Oscillator

(a)

OscIn 1

z-1

z

z-1

OscOut

(b)

g

oscillator

cDataWidth cDataWidth

cDataWidth

f2gFosc

clock

enable

reset

OscIn OscOut

oscillator

g

cDataWidth

cDataWidth

cDataWidth

Fig. 5.12.1:oscillator: (a)topology, (b)symbol.

First of all show which integrator, Fig. 5.12.2(a) or (b), has which z model, (c) or (d).

Compute the oscillation frequency Fosc =f(g) and g=f(Fosc) with (=fosc/fs with fs samplingfrequency) for the oscillator in Fig. 5.12.1.

Draw a detailed schematics of the oscillator and check it with your supervisor. Model it withMatlab (care about amplitudes of the integrator outputs as a function of g, particularly g0.)

After the Matlab model is understood realize the integrator with VHDL and download it intothe FPGA.

(a)

X Y

z-1X(b) 1

z-1X YY1

z

z-1z-1X

Y0

X(d)

Y

(c)

(e)W

W

Y0

Fig. 5.12.2: integrator: (a), (b) integrator types, (c), (d) respective integrator models in z,(e) integrator symbol common to (a)-(d)


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Fig. 5.12.4:oscillator:s2: black tabs + green line,s1: blue line; (a)simulation withFosc=0.1,

(b)Fosc= 0.25, (c)Fosc= 0.45.

Considerations on required bit-widths of data.

(a) If 0


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5.13 Other Stuff

5.13.1 Interface for DE2-70 Board

The laboratory is dome with the Altera / Terasic DE2 board [7], [8], [9]. Port it to otherboards, e.g. theDE2-70board [8], which is more powerful but has different signal mapping tothegpio_# (#=1,2) user headers.

5.13.2 Analyze and Display ADC- Output

The DE2-board has eight 7-segment-display digits. The should be used to display the DC-value of the signal, the AC-Amplitude and its frequency (similar like oscilloscpes do).

6 Conclusions

A complete A/D and D/A conversion system for Altera DE2 board in combination with theDA2 board of the laboratory was subdivided in modules, build and demonstrated.

7 References

[1] 1076 IEEE Standard VHDL Language Reference Manual, Revision of IEEE Std. 1076,2002 Edition.

[2] M. Schubert, VHDL Course, Regensburg University of Applied Sciences. Available:http://homepages.fh-regensburg.de/~scm39115/Offered Education Courses and

Laboratories

RED

VHDL.[3] Lehmann, Wunder, Selz, Schaltungsdesign mit VHDL, Franzis Verlag, Poing 1994.[4] Matlab, available: http://www.mathworks.com/[5] M. Schubert, Zusammenfassung von MATLAB-Befehlen, Regensburg University of

Applied Sciences. Available: http://homepages.fh-regensburg.de/~scm39115/ Offered Education Courses and Laboratories RED Matlab.

[6] A. Angermann, M. Beuschel, M. Rau, U. Wohlfarth: Matlab Simulink Stateflow,Grundlagen, Toolboxen, Beispiele, Oldenbourg Verlag, ISBN 3-486-57719-0,4. Auflage (fr Matlab Version 7.0.1, Release 14 mit Service Pack 1).

[7] Available at HSR: K:\SB\Hardware\Altera\DE2\DE2-CD\[8] Available: http://www.terasic.com.tw/en/Products FPGA Main Boards

Cyclone II Altera DE2 Board / Altera DE2-70 board.[9] Available: http://www.altera.com/[10] M. Schubert, Getting Started with DE2 and DA2 Boards, Electronic Design

Automation Course, Regensburg University of Applied Sciences, available:http://homepages.fh-regensburg.de/~scm39115/Offered Education Courses andLaboratories RED

[11] M. Schubert, FSM Design for DSP Using VHDL, Electronic Design AutomationCourse, Regensburg University of Applied Sciences, available: http://homepages.fh-regensburg.de/~scm39115/

[12] M. Schubert, FSM Design for DSP Using Matlab, Electronic Design Automation

Course, Regensburg University of Applied Sciences, available: http://homepages.fh-regensburg.de/~scm39115/Offered Education Courses and Laboratories RED


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[13] M. Schubert, FSM Design for DSP Using Fixed-Point Numbers, Electronic DesignAutomation Course, Regensburg University of Applied Sciences, available:http://homepages.fh-regensburg.de/~scm39115/Offered Education Courses andLaboratories RED

[14] ModelSim, Available: http://model.com/

[15] ModelSim Simulator, available at HSR: K:\SB\Software\[16] Quartus II 8.1, available at HSR: K:\SB\Software\[17] M. Schubert, Script Systemkonzepte, Regensburg University of Applied Sciences,

available: http://homepages.fh-regensburg.de/~scm39115/ Offered Education Courses and Laboratories SK

[18] S. R. Norsworthy, R. Schreier, G. C. Temes, Delta-Sigma Data Converters, IEEEPress, 1996, IEE Order Number PC3954, ISBN 0-7803-1045-4.

[19] J. C. Candy, G. C. Temes, 1st paper in Oversampling Delta-Sigma Data Converters,Theory, Design and Simulation, IEEE Press, IEEE Order #: PC0274-1, ISBN 0-87942-285-8, 1991.

[20] C. A. Leme, Oversampling Interfaces for IC Sensors, Physical ElectronicsLaboratory, ETH Zurich, Diss. ETH Nr. 10416.[21] Lerch,Elektrische Messtechnik, Analoge, digitale und computergettzte Verfahren,

3. Auflage, Springer Verlag, 2006.[22] E. B. Hogenauer, An economical class of digital filters for decimation and

interpolation, IEEE Transactions on Acoustics, Speech and Signal Processing,California, USA, 1981.

ADA Conversion Project Oriented Laboratory

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