Active-HDL Quick Start Guide Verilog

Active-HDL Quick Start Guide

Active-HDL Quick Start Guide Verilog version.

Table of Contents

Introduction............................................................................................................................2

Creating A New Design .........................................................................................................2

Starting from the Opening Screen......................................................................................2

Starting from the GUI ........................................................................................................2

Choosing Workspace and Design Names ..........................................................................2

Creating First Design Files ....................................................................................................3

Creating DFFR.V ...............................................................................................................3

Compiling and simulating DFFR.V ...................................................................................4

Creating the Converter (J2H.V) .........................................................................................6

Simulating the Converter ...................................................................................................6

Creating One Hot Counter (COUNTER.BDE)......................................................................7

The Diagram ......................................................................................................................7

Placing Symbols.................................................................................................................8

Wiring the Diagram ...........................................................................................................9

Simulation of the Counter ................................................................................................10

Adding The State Diagram to Our Design...........................................................................11

Creating A Top-level Diagram (TOP.BDE) ....................................................................11

Drawing The State Diagram (CONTROL.ASF)..............................................................12

Top Level Simulation...........................................................................................................14

Conclusion ...........................................................................................................................14

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Introduction This Quick Start Guide was created to help you become familiar with the basic features of Active-HDL 6.2 in the shortest possible time. No prior knowledge of HDL simulation tools is required, but elementary knowledge of Verilog will be helpful.

If you want to refresh your Verilog, you are welcome to use our Interactive Verilog Tutorial: go to the Help menu, select the Interactive Verilog Tutorial option. The same tutorial is also accessible directly from the installation CD.

While reading this Guide, you will be able to create, compile, simulate and debug a simple, but fully functional design. No special license is required (even the demo version is OK!) and there are no special files needed to complete your work.

The first part of the Guide covers HDL entry, BDE entry, IP CORE Generator, interactive simulation, testbench generation, One Hot counter built from 3 flip-flops, inverter and a Johnson to Hot One code converter.

The second part adds the FSM controlling reset of the counter created in the first part.

Creating A New Design

Starting from the Opening Screen If you double-click the Active-HDL icon on your desktop, you should see the splash-screen for a while, then the Getting Started window with the Active-HDL GUI in the background.

Right in the middle of that window you should notice a Create new workspace radio button (Figure 1). Select this button, and then click OK.

Figure 1: Create new workspace radio button.

Starting from the GUI If Active-HDL is already open (e.g. you were playing with sample designs) go to the File menu, select New, then Workspace.

Choosing Workspace and Design Names 1. When either starting from the GUI or the Getting Started window, you should see a

New Workspace window. Type the name of the workspace (MY_WORKSPACE) in the first field; keep the Add New Design to Workspace checkbox selected and click OK.

2. The New Design Wizard window appears. In this new window, select Create an empty design and click Next>.

3. In the second screen of the wizard, choose Verilog as the Default HDL language and click Next>.

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4. In the third screen of the wizard, type MY_CNTR as the design name and click Next>.

5. In the last screen of the wizard click Finish.

Your new workspace and design are ready to use!

To learn more about workspaces and designs, go to Active-HDL On-line Documentation, in the Contents tab select Active-HDL Help / Using Active-HDL / Workspaces and Designs.

Creating First Design Files

Creating DFFR.V The first source file we are going to create describes a D flip-flop with asynchronous reset. The interface of the flip-flop can be quickly created using the New Source File wizard.

1. Go to the File menu and select New, then Verilog Source.

2. Read through the first screen of the New Source File wizard, select the Add the generated file to the design checkbox and click Next>.

3. In the second screen of the wizard, type the name of the file (DFFR) in the first entry field and click Next>.

4. In the third screen of the wizard, add the following ports to the flip-flop description: CLK - clock input RESET – asynchronous reset input D – data input Q – data output

To add each port, click New, type the port name in the Name field and select the appropriate Port direction. When all ports are entered, click Finish.

Note that a new document icon was added to the Design Browser window in the Active-HDL GUI – it represents the DFFR.V file created by the wizard. (If you don’t see the icon, click the tab at the bottom of the Design Browser marked Files.) The content of the file is available for viewing/editing in the HDL Editor (upper right-hand corner of the GUI).

Instead of typing the entire functional description of our flip-flop, we can use templates from the Language Assistant.

5. Scroll down the Verilog source so that you can see the entire outline of the module of the flip-flop created by the wizard.

6. Go to the Tools menu and select Language Assistant. NOTE: There is a toolbar button that performs exactly the same operation: look for the button with the white light bulb on it.

7. In the floating Language Assistant window, expand the Synthesis templates and then the Flip-Flops in the list of categories and click D F/F with asynchronous Reset. The text of the template displays on the right-hand side of the window.

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8. Copy all template lines between the module line and endmodule line from the Language Assistant window and paste them over the lines originally created by the wizard between the module line and endmodule line in the DFFR.V file.

9. Close the Language Assistant window and save the DFFR.V file.

To learn more about the Language Assistant, go to Active-HDL On-line Documentation, then in the Contents tab select Active-HDL Help / Active-HDL Tools / Language Assistant.

Compiling and simulating DFFR.V To compile the source file in Active-HDL you have several options:

• Right-click the icon of the source file in the Design Browser and select Compile from the pop-up menu.

• While the source file is open for editing/viewing, click the Compile button ( ) on the main toolbar.

• While the source file icon is selected or the file is open, hit the F11 key on your keyboard.

Using the method you prefer, please compile the DFFR.V file.

If the compilation was successful, a green confirmation message will be displayed in the Console window at the bottom of the workspace. If you see red messages in the console, it means that errors were detected. In that case, you should read the error message carefully, double-click the text of the message in the console to highlight the offending line in the source code (the document will be opened if it wasn’t), correct the mistake and save/compile again.

A successfully compiled source file icon will have the list of the modules detected inside the file during compilation. Click the plus sign to the left of the DFFR.V icon to display the green M icon for the DFFR module detected while compiling the file.

Before you start the simulation, some module must be selected as the top level of your design. Since DFFR is the only compiled module in our design, the system should be able to select it as the top level automatically. When there are multiple modules in your design, you can select one of them from the drop-down list at the very top of the Design Browser window.

When DFFR is selected as the top level, you can start your simulation.

1. Select Simulation | Initialize Simulation from the menu; wait until the design browser switches to the Structure tab automatically.

2. Select File | New | Waveform from the menu (or click the matching icon in the main toolbar).

3. Drag the green chip icon for DFFR from the Design Browser window to the empty waveform document created in the previous step. The list of our flip-flop ports are displayed in the waveform.

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4. Right-click the CLK port name in the waveform window and select Stimulators from the pop-up menu.

5. Drag the floating Stimulators window (Figure 2) to the bottom of the screen, so that you can see both the window and all signals in the waveform.

Figure 2: Stimulators window with Clock stimulator type selected.

6. While CLK is highlighted in the Signals: list, select Clock as the stimulator in the Type: list. Adjust the clock frequency to 100MHz (clock period will adjust automatically to 10 ns) – the Stimulators window should look exactly as in Figure 2. Click Apply.

7. Without closing the Stimulators window, click the RESET port name in the waveform; the port name should be transferred to the Signals: list in the Stimulators window.

8. Select Formula as the stimulator type for RESET and type 1 0 ns, 0 10 ns in the Enter formula field (don’t skip any spaces!). Click Apply.

9. Without closing the Stimulators window, click the D port name in the waveform. Select Random as the stimulator type for D (you will have to scroll all the way down in the Type: list). Select uniform distribution, seed 0, period 10 ns, start value 0 and end value 3.

10. Click Apply and close the Stimulators window.

11. Select Simulation | Run Until… from the menu. Type 200 ns in the Run Until window. Click OK.

Analyze the results displayed in the waveform. If you are curious what is the signal value represented by a section of the waveform, click it and examine the Value field right by the signal name.

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When you are finished, select Simulation | End simulation from the menu, save the waveform as FLIP_FLOP.AWF and close the waveform window.

To learn more about simulation, go to Active-HDL On-line Documentation, in the Contents tab select Active-HDL Help / Using Active-HDL / Simulation. We will be conducting more simulations in this guide.

Creating the Converter (J2H.V) We are going to use the IP CORE Generator to create the Johnson to One Hot code converter file.

1. Select Tools | IP CORE Generator from the menu.

2. Click the Code Converters link in the Generator interface.

3. Set language to Verilog and module name to J2H.

4. Set converter type to “Johnson to Hot”, active hot to “one-‘1”’ and data width to 3.

5. Deselect checkboxes by the EN and ER ports in the converter symbol.

6. Click the Options button ( ) and select the checkboxes listed below in the IP Core Generator Configuration window: Specify the destination file, Set src design folder as root folder, Show generated HDL file after generation. Clear all other checkboxes. Click OK.

7. Click the Generate button ( ), select Compile file after generation and click OK.

8. Close generation confirmation window and examine the file.

The J2H.V file should already be compiled and ready to use, but you can modify it if you wish.

To learn more about the IP CORE Generator, click the Help button ( ) in its user interface.

Simulating the Converter Using the experience from simulation of the flip-flop, you should be able to select the top level, initialize simulation and create waveform to control the J2H.V simulation.

HINTS: Remember to set the top level correctly before initializing simulation. Use the Counter stimulator type with the count type set to “Johnson code”.

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Creating One Hot Counter (COUNTER.BDE)

The Diagram In this section we are creating a One Hot counter built from three instances of the DFFR flip-flop, one instance of the J2H converter, and an inverter. The diagram of the counter is shown in Figure 3 below.

Figure 3: Diagram for COUNTER module.

NOTE: The two circles with CLK and RESET in the diagram in Figure 3 represent global wires connecting all ports and signals in the diagram bearing the same name as the global wire.

We will start our work on the counter by invoking the New Source File Wizard.

1. Go to the File menu and select New, then Block Diagram.

2. In the first screen of the New Source File wizard, select Add the generated file to the design checkbox and click Next>.

3. In the second screen of the wizard, choose Verilog as the generated language and click Next>.

4. In the third screen of the wizard, type the name of the file (COUNTER) in the first entry field and click Next>.

5. In the fourth screen of the wizard, add the following ports to the flip-flop description: CLK - clock input RESET – asynchronous reset input Q[5:0] – data output

To add each input, click New, type the port name in the Name: field and select the appropriate Port direction: For the output port, you can type Q in the Name: field, type 5 in the first of the two Array Indexes: fields and select the output direction. When all ports are entered, click Finish.

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These steps should create a diagram sheet with two inputs and one output port symbol.

Placing Symbols NOTE: Try to place symbols as close to the layout in Figure 3 as possible.

1. Click the Show Symbol Toolbox button ( ) in the Block Diagram toolbar to display the Symbol Toolbox to the right of the diagram (Figure 4). You can also use the S key on your keyboard to show/hide the toolbox.

Figure 4: Symbol Toolbox.

2. Expand MY_COUNTER | Units without symbols sections in the upper part of the Symbol Toolbox and click the DFFR entry in the list. A symbol for the previously compiled flip-flop will appear in the lower part of the toolbox. NOTE: The section Units without symbols exists only when some modules were compiled, but not yet used in the diagram. After the first use, the symbol for the module is moved to the MY_COUNTER section.

3. Drag three instances of the DFFR from the toolbox to the diagram. (You can drag either the name of the module from the list or the symbol from the lower half of the toolbox.)

4. Drag one instance of the J2H module from the toolbox to the diagram.

5. Expand the Built-in symbols section in the toolbox and drag one instance of the inv primitive to the diagram.

6. Close the toolbox.

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7. Right-click the symbol of the inverter in the diagram and select Mirror | Horizontal from the pop-up menu.

Now our diagram is ready for wiring.

Wiring the Diagram

1. Click the Bus button ( ) in the Block Diagram toolbar.

2. To draw the connection between the converter and the output port, click the tip of the port symbol, and then click the tip of the output pin of the converter.

3. To draw the hanging bus connected to the input of the converter, click the tip of the input pin of the converter, move mouse pointer to the left so that the bus forms a straight line, and then click in the empty space (somewhere above the leftmost instance of the flip-flop).

4. Press Esc on your keyboard to return to the Select mode and double-click the hanging bus.

5. In the Bus Properties window, type I in the Segment: field and adjust Index range: to “2 downto 0”. Click OK.

6. Click the Wire button ( ) in the Block Diagram toolbar.

7. Draw two short wires connecting the outputs and inputs of flip-flops. (Click the starting pin tip, then ending pin tip.)

8. Draw wires connecting the inverter with the flip-flops.

9. Draw wires connecting the flip-flop outputs with the hanging bus ( I(2:0) ). NOTE: The wire can start in the middle of another wire and end at the bus line; an appropriate junction/bus tap will be added automatically.

10. Press Esc on your keyboard to return to the Select mode and double click the wire connecting the output of the inverter with the flip-flop input.

11. In the Wire Properties window, type feedback in the Segment: field and click OK.

12. Label bus taps by double-clicking the wires connecting the outputs of flip-flops with the bus and entering the bus member name in the Segment: field. As you can verify in Figure 3, those bus member names are I(0), I(1) and I(2).

13. Click the Global Wire button ( ) in the Block Diagram toolbar. If the button with athick, brown outline around the yellow circle appears in the toolbar instead, click the black triangle to the right of it and select the Global Wire symbol from the drop-down list.

14. Place two yellow circles in the empty area of the diagram (preferably close to the input ports).

15. Press Esc on your keyboard to return to the Select mode and double click one of the yellow circles.

16. In the Global Wire Properties window, type CLK in the Net Name: field and click OK.

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17. Using the same procedure, rename the second yellow circle to RESET.

18. Click the Generate HDL Code button ( ) in the Block Diagram toolbar. Observe messages in the console window during generation. To view the generated code, click

the View HDL Code button ( ) in the toolbar.

To learn more about the Block Diagram Editor, go to Active-HDL On-line Documentation, in the Contents tab select Active-HDL Help / Active-HDL Tools / Block Diagram Editor.

Simulation of the Counter Compile the diagram and select COUNTER as the top level. Initialize simulation, create a new waveform and drag signals from the Design Browser to the waveform – exactly the same way you have done during the last two simulation sessions.

Assign 100MHz clock stimulus to the CLK input and 1 0 ns, 0 10 ns formula stimulus to the RESET input. Simulate for 200 ns. End simulation and save the waveform as COUNTER.AWF.

To automate future simulations of the counter module (e.g. after some design modifications), you can generate a Verilog testbench automatically.

1. Right-click the green M icon marked COUNTER in the Files tab of the Design Browser and select Generate TestBench from the pop-up menu.

2. Select Simple testbench type in the first screen of the Test Bench Generator Wizard window. Click Next> when done.

3. In the second screen of the wizard, select Test vectors from file, and then click Browse.

4. Point to the COUNTER.awf waveform file saved during interactive simulation and click Open.

5. Click Next>, accept all the defaults in the next screen, click Next> again.

6. Click Finish in the last screen of the wizard.

Please note the changes in the Files view of the design browser: a new TestBench folder was created, and the wizard added two files to this folder:

• COUNTER_TB.V – complete testbench for the COUNTER module. • COUNTER_TB_RUNTEST.DO – script (macro) file controlling simulation.

Feel free to examine the contents of the testbench file. When you are done, open the script file and find the following elements inside:

• comp commands – compiling all sources required for simulation. • asim command – selecting top level and initializing simulation. • wave commands – creating a waveform window and adding signals to it. • run command – starting simulation for the specified period of time.

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If you modify any part of the counter and want to check if it still simulates correctly, the only thing you will need to do is to right-click the sprocket icon for the script file in the Design Browser and select Execute from the pop-up menu.

All changed files will be recompiled, and the entire simulation will proceed under the control of the testbench and script file.

Execute COUNTER_TB_RUNTEST.DO to see how it works.

To learn more about the automatic testbench generation, go to Active-HDL On-line Documentation, in the Contents tab select Active-HDL Help / Active-HDL Tools / Test Bench Wizard.

Adding The State Diagram to Our Design To demonstrate the ability to create a state diagram description in Active-HDL, we will add one more file to our design – a state machine that can shorten the cycle of our counter depending on the numeric value of the 3-bit input REF.

Until now, we have been using bottom-up design methodology (already created lower level modules were instantiated inside the upper level modules).

This time we will prove that top-down design methodology can also be used in Active-HDL: we will create a top-level block diagram with a black box representing the state machine before actually creating the state diagram for the machine.

Creating A Top-level Diagram (TOP.BDE) 1. Using the New Source File Wizard (File | New | Block Diagram), add a file named

TOP to our design. The generated language should be Verilog, input ports CLK, INIT and REF(2:0), output port Q(5:0).

2. When the diagram is created, open the Symbol Toolbox and drag the previously compiled COUNTER module to the diagram – place it close to the output port symbol.

3. Click the Fub button ( ) in the Block Diagram toolbar and drag your mouse in the diagram to create a light blue square located close to the input port symbols. (The square should be taller than the group of input ports – see Figure 5.)

4. Right-click the blue square, select Properties from the pop-up menu and rename the fub from Fub1 to CONTROL.

5. Switch to the Bus mode and connect the output port with the output pin of the COUNTER. While still in Bus mode, start drawing a bus at the tip of the REF(2:0) port, then click the border of the blue fub square. Notice that an input port was created in the CONTROL symbol.

6. Switch to the Wire mode and draw wires starting at the tip of the CLK or INIT and ending at the edge of the fub symbol. Two additional inputs should be created in the CONTROL symbol. Draw an additional wire segment to connect the CLK input of the COUNTER with the CLK terminal of the TOP.

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7. Draw one more wire: start at the tip of the RESET pin of the COUNTER, and then click to the left of the symbol to leave the other end unconnected.

8. Press Esc on your keyboard to return to the Select mode and double-click the wire segment drawn in the previous step. Rename the segment to RESET and click OK.

9. Drag the hanging end of the RESET wire and drop it at the right edge of the fub. A RESET output pin will be created.

10. Double click the bus connecting the COUNTER with the output terminal and rename the bus segment to Qint(5:0).

11. Switch to Bus mode and draw a bus connecting the Qint with the left edge of the blue fub symbol.

After all operations mentioned above, the diagram for TOP.BDE should look like the one in Figure 5.

Figure 5: Diagram for TOP module.

If you double-click the COUNTER symbol, the content of the symbol will be displayed. Since we have created the CONTROL symbol, it is treated as a black box and has no content.

If you double-click the CONTROL symbol, you will get a Create New Implementation window. Please select State Diagram in the Type: area and leave all remaining settings unchanged. Click OK to confirm your selection.

Drawing The State Diagram (CONTROL.ASF) As the result of requesting state diagram creation in the Create New Implementation window, you should see the CONTROL.ASF file automatically created and added to the design browser. At the beginning the diagram contains only the port symbols; our task is to make it look like the one in Figure 6.

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Figure 6: Bubble diagram for the CONTROL state machine.

1. Double-click the CLK port symbol to display Port Properties and select the Clock checkbox; click OK to confirm changes.

2. Double-click the RESET port symbol to display Port Properties and select Registered; click OK to confirm changes.

3. Select FSM | State from the menu and place two state bubbles inside the large, black, rectangular frame right below the port symbols. The second bubble should be located below the first one. The FSM Editor will label the bubbles S1 and S2. Press Esc on your keyboard to return to the Select mode. (You can drag state bubbles around while in Select mode.)

4. Select FSM | Transition from the menu and draw two transition arrows between the S1 and S2 states: click inside the state where the transition starts, then inside the state where the transition ends. Hit Esc on your keyboard to return to Select mode. (You can drag the transition line to change its shape while in Select mode.)

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5. Select FSM | Reset from the menu and click above the S1 state to place a yellow triangle representing reset; click again inside the S1 state to choose it as the reset state. Press Esc to return to Select mode.

6. Double click the white background inside the rectangular frame where you have placed the bubbles to display Machine Properties.

7. In the General tab of Machine Properties change the name of the machine to Ctrl.

8. In the Reset tab of Machine Properties, select INIT as the reset input, Asynchronous as the reset type and High as the active level. Click OK to confirm.

9. Select FSM | Action | Entry from the menu and click the S1 state bubble (black dot, not the crosshairs, is the tip of mouse pointer!). Type RESET<=1 as the action and press Ctrl+Enter on your keyboard.

10. Click the S2 state bubble, type RESET<=0 as the action and press Ctrl+Enter on your keyboard. Press Esc to return to Select mode.

11. Select FSM | Condition from the menu and click the transition from S2 to S1; type Qint[REF] as the condition text. Hit Ctrl+Enter and then Esc on your keyboard.

Your state machine is ready. You can use the Generate HDL Code and the View HDL Code buttons in the FSM Editor toolbar to convert the diagram and review the generated Verilog code.

To learn more about the State Diagram Editor, go to Active-HDL On-line Documentation, then in the Contents tab select Active-HDL Help / Active-HDL Tools / State Diagram Editor.

Top Level Simulation Compile CONTROL.ASF and TOP.BDE from the Design Browser. Select TOP as the top level. Initialize simulation and add all signals from the top level to the waveform. Add the following stimulators:

• For CLK, standard 100 MHz clock stimulus. • For INIT, formula 1 0 ns, 0 10 ns. • For REF, binary counter stimulus with ‘up’ direction, 100 ns period, initial value 1

and increment 1.

Simulate for 500 ns. Save waveform as TOP.AWF. Generate the testbench based on TOP.AWF (use the procedure introduced while simulating COUNTER.BDE).

Conclusion After completion of this Quick Start Guide you should be familiar with all of the basic procedures in Active-HDL. Feel free to investigate the on-line documentation and play with more advanced options using this newly created design!

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Active-HDL Quick Start Guide Verilog

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