ACTIVE AREA DENSITY OPTIMIZATION TECHNIQUE FOR …
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ACTIVE AREA DENSITY OPTIMIZATION TECHNIQUE FOR
HARVESTER PHOTODIODES EFFICIENCY MAXIMIZATION
E. Dallago, M. Ferri, P. Malcovati, D. Pinna Department of Electrical Engineering, University of Pavia, Via Ferrata,1 27100 Pavia
Abstract
Modern and future ultra-deep-submicron technologies [1] allow very low power consumption
Microsystems to be realized, with increasing analog functions and computational capabilities.
Despite the technology scaling, the slow growth of the battery energy density [2] limits the lifetime
and the weight reduction of portable and nomadic devices as well as of sensor network nodes.
Therefore, harvesting systems are becoming the new challenge in both research and commercial
communities. Macro solar harvesting systems represent the most developed commercial
applications. Usually, photodiodes and phototransistor [3] are used as low cost photodetectors, but,
if proprierly operated, they can be used both as a stand alone, high efficiency micro solar cell and as
solar energy source for an integrated microsystem diffused on the same silicon die.
In this paper we present several micro solar cell structures [4], implemented on the same test chip,
and the design approach to maximize the efficiency of such harvesters. The test chip is realized with
a standard 0.35um CMOS technology. In particolar, we realized several photodiodes, with different
dimensions of the n-well and of the p-diffusion geometry, featuring different density of active area.
Figure 1 shows the different geometries, while Table 1 summarizes the dimensions and the
equivalent active area for each structure.
Figure 1
Geometries of the realized
integrated solar cells.
Type Harvester
active
area
[mm ]
Harvester
active
perimeter
[ m]
Parasitic
active area
[ m ]
Parasitic
active
perimeter
[ m]
Number of
structures
on silicon
A 2.43929e-5 642546 1e-6 4000 1
B 2.89457e-7 827845 1.9826e-6 5632,2 1
C 7.24565e-8 207431 5.11719e-7 2861.65 1
D 1.78246e-7 47073 6.23e-8 998.4 4
Table 1
Realized integrated solar cell
parameters.
The presented work is focused on the characterization of the structures in terms of geometry
dependent efficiency. The equivalent circuit model for each solar structure consists of a couple of
pn junction, as shown in Figure 2. When the micro solar cell is used as stand-alone device, it is
possible to exploit the photo-generated current of both junctions, considering them as independent
photodiodes connected in parallel (when the substrate is short-circuited to the p-diffusion).
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As shown in Table 2, the most important contribution of power is given by the junction between the
n-well and the low doped p-substrate.
The most efficient solar cell is structure C, which features the highest active area density, as shown
in Figure 3. The output power of the structures has been obtained with 100W/m2 illumination,
provided by a source with a constant power spectrum, very similar to the sun.
The standard CMOS technology substrate isolation is based on the reverse biasing of the deepest
junction. Therefore, when the solar cell structure is used together with other circuits, it is necessary
to short-circuit the substrate to the n-well. Under this condition, it is not possible to neglect the
transistor effect, which reduces the total efficiency of the structure. This is due to the interaction of
the currents of the two junctions. In particular, when the junction between p-substrate and n-well is
short-circuited, it contributes negatively to the current of the harvester diode. This causes a loss of
efficiency, reducing the photo-generated current. For example, with device C, for 100W/m the
current is reduced from 10 A, obtained when the substrate is floating, to 2.5 A. To validate the
PNP transistor model, we extracted the Ebers-Moll parameters in the absence of light. When the
substrate diode is short-circuited, it is necessary to consider the transistor effects also in light
irradiation condition.
Figure 3
Power characterization of
structure C.
As all structures have been realized in standard CMOS technology, without any chance to change
the process parameters, they can be used as light sensors just in a restricted area of application
(optical switches for example).
Always referring to Table 2, it is possible to notice that the largest is the active area density high,
the lower is the output power reduction due to the transistor effect.
Type Harvester
with
floating
substrate
diode
Harvester
with short-
circuited
substrate
diode
Parasitic
with
floating
Harvester
diode
Parasitic
with short-
circuited
Harvester
diode
Harvester
and
substrate
diodes in
parallel
A 2,91 0,44 9,45 8,69 9,45
B 3,02 0,44 15,12 15,12 15,12
C 2,91 1,04 17,64 17,64 17,01
D 2,26 0,56 11,9 11,97 12,6
Table 2
Efficiency table.
REFERENCES
1. Ho, H.L.; Steigerwalt, M.D.; Walsh, B.L.; Doney, T.L.; Wildrick, D.; McFarland, P.A.; Benedict, J.; Bard, K.A.;
Pendleton, D.; Lee, J.D.; Maurer, S.L.; Corrow, B.; Sadana, D.K., “A 0.13 m high-performance SOI logic
technology with embedded DRAM for system-on-a-chip applicationI”, Electron Devices Meeting, 2001. IEDM
Technical Digest. International, 2-5 Dec. 2001 Page(s):22.3.1
2. Jian Gao; Longyun Yu, “Use of battery ohmic testing to improve network reliability and decrease battery
maintenance cost”, Telecommunications Energy Conference, 2007. INTELEC 2007. 29th International, Sept. 30
2007-Oct. 4 2007 Page(s):194 - 202
3. Moriizumi, T. , Takahashi, K. , “Theoretical analysis of heterojunction phototransistors”, Electron Devices, IEEE
Transactions on Volume 19, Issue 2, Feb 1972 Page(s):152 – 159
4. D. A. Neamen, “Semiconductor Physics and Devices”, 1992
Circuit model of realized
structures.
Figure 2
Circuit model of realized
structures.
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