Device/Circuit Interactions at 22nm Technology Node Kaushik Roy, Jaydeep P. Kulkarni and Sumeet Kumar Gupta

School of Electrical and Computer Engineering, Purdue University 465 Northwestern Avenue, West Lafayette, IN, USA 765-494-9448

kaushik@ecn.purdue.edu

ABSTRACTAs transition is being made into 22nm node, technology considerations and device architectures suitable for such scaled technologies are being explored. To design circuits and systems at scaled nodes, we believe there is a need for technology aware circuit and system design methodology that considers device architecture, and technology challenges to achieve design optimality. In this paper, we discuss the challenges of device-circuit-system design at the 22 nm node and present techniques atdifferent levels of design abstraction to meet these challenges. In particular, we discuss different device options for multi-gate FETs. Logic and memory design using multi-gate FETs is also considered. Finally, we briefly discuss process variation tolerant system design methodologies for such scaled technologies.

Categories and Subject Descriptors B.7.1 [Types and Design Styles]: Advanced Technologies

General Terms:Design

Keywords:22 nm technology node, DG MOSFETs, FinFETs, scaling, SRAM, transistor sizing

1. INTRODUCTION The past few decades have seen transistor-scaling driven evolution of semiconductor technology. With every technology generation, devices, circuits and systems are expected to achieve higher performance, lower power consumption and larger integration density. However, the characteristics of highly scaled transistors degrade due to increased short channel effects and larger susceptibility to process variations. Hence, innovative techniques are required to circumvent these problems at all levels of design abstraction. From the process technology point of view, techniques like optical proximity correction (OPC) assume significance for compensating the variations due to light interference effects in lithography. At the device level, short channel effects like DIBL (drain induced barrier lowering) may be mitigated in bulk MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) using halo implants in the channel. Other device structures like UTB SOI (Ultra-thin Body Silicon on

Insulator) MOSFETs and MUGFETs (Multi-gate FETs) such as double gate (DG) MOSFETs [1] and FinFETs [2] are attractive because of larger gate-control of channel and hence, reduced short channel effects. MUGFETs, though suitable as drop-in replacement for bulk-transistors, have different technology options that can best be utilized by a technology-aware circuit design methodology. Example of such technology characteristics and variants include: multi-fin and width quantization, use of the back-gate as an independent gate, gate-underlapping [3], and fin orientation. Bulk devices and MUGFETs are both expected to experience large variations in design parameters. At the circuit level, process variations may be countered using techniques like adaptive body biasing or designing circuits using variation-tolerant logic families. At the system level, techniques likeCRISTA [4] and RAZOR [5] may be used.

Semiconductor industry is already producing CMOS digital systems at the 45 nm technology node and considerable amount of research has been carried out for the 32 nm node. The target devices have been bulk CMOS devices or its variants such as floating body SOI. However, to meet 22 nm technology challenges, MUGFETs need to be seriously considered because of their lower short channel effects.

Let us first discuss some of the issues that the 22 nm technology node and the subsequent generations can potentially face. Since the drain will be much closer to the source, the short channel effects (even for bulk devices with halo doping or for MUGFETs), are expected to worsen, giving rise to an exponential increase in the leakage current. In order to increase the gate-control of the channel, the gate oxide needs to be scaled, however that would lead to an increase in the gate leakage current. Use of high-kdielectrics is an option and may be a potential solution to counter short channel effects in sub-32 nm technology nodes.

Due to smaller channel lengths and hence reduced volume of the active region, process variations like random dopant fluctuations (RDF), body thickness variations (for MUGFETs), and line-edge roughness (LER) will have a larger impact on the performance of the devices and circuits. Variation of threshold voltage is expected to increase and may cause timing failures for high performance circuits. A larger design margin may be required leading to lower performance and/or increased power consumption.

Along with scaling the device dimensions, voltage scaling assumes significance in order to keep the electric fields well below their critical level. However, power supply voltage (VDD)scaling is limited by the threshold voltage scaling. Lower threshold voltage leads to an increase in the sub-threshold leakage current while higher threshold voltage leads to the degradation ofON current. Hence, in order to obtain reasonable ON and OFF currents, one may not have much flexibility in scaling the threshold voltage. This results in limited VDD scaling. Due to

8.3

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Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. DAC’09, July 26-31, 2009, San Francisco, California, USA Copyright 2009 ACM 978-1-60558-497-3/09/07....10.00

increased electric fields, effects like hot carrier injection and negative bias temperature instability (NBTI) are expected to worsen.

Hence, there is a need to analyze such issues in a greater detail and explore potential solutions. This paper discusses the need for close interaction between technology, device, circuit and system level designs to meet the challenges of the 22 nm technology node and beyond.

The organization of the paper is as follows. In Section 2, we discuss the possible device structures that can be suitable for the 22 nm technology node. Section 3 discusses logic and memory design using MUGFETs. In section 4, we briefly discuss technology-independent system level design optimization techniques. Section 5 draws the conclusions.

2. POSSIBLE DEVICE STRUCTURES: FINFETs As scaling of transistor continues, leakage current increases exponentially every generation. Also with scaling, process imperfections result in significant variations in device characteristics and can have a large impact on the stability of on-chip memory cells. Due to enhanced short channel effects (SCE), scaling single gate bulk devices beyond sub-50nm node is becoming increasingly difficult. Ultra Thin Body Double-Gate MOSFET (UTB DGFET) devices are suitable in sub-50nm technologies due to their higher immunity to SCE, better scalability and increased on-current compared to single gate devices. Furthermore, DGFET has negligible junction capacitance, due to which delay of the circuit is reduced and is mainly limited by the parasitic capacitances. Moreover, the body of DGFET devices are expected to be lightly doped with threshold voltage (Vt) to be principally controlled using metal gate work-function. The lightly doped body eliminates the Vt variations due to random dopant fluctuation (RDF) (note, however, body-thickness variations [6] in ultra-thin devices may lead to threshold variations due to quantum confinement effect). DGFETs, with such attractive properties for scaled technologies, deserve analysis, especially the possibility of having different design options with such devices. Fig. 1 shows some of the technology and device options with UTB DGFETs. We shall discuss them in detail in the subsequent sections. FinFETs have emerged as one of the most suitable candidates for DGFET structure. FinFETs have quasi-planar structure, the width of the transistor is the height of the fin (Hfin). Hfin is a technology constraint and depends on the aspect ratio (Hfin:Tsi ~ 4-5). To increase the width of the transistor (in other words, the driving strength of the transistor) the number of fins has to be increased. Hence, the width increases in quanta of fin. In an SRAM cell, the stability depends upon the respective driving strengths of the transistors (β ratio). In conventional planar MOSFET based SRAM cell, β ratio is modified to improve the stability of the cell. However, because of width quantization in FinFETs the range of β ratios is limited. In FinFETs, to improve the stability and to reduce leakage, it has been shown that joint Vdd-Hfin-Vt design space and/or spacer thickness can be optimized. Multiple fin-orientation (to improve the mobility) can also be used to achieve design optimality.

2.1 Spacer Thickness Optimization As discussed previously, DG-MOSFETs have negligible junction capacitance, and hence, the drain capacitance is mainly dominated

by the overlap capacitance [7]. In order to reduce the drain capacitance, underlap between the gate and the source/drain (S/D) can be introduced (see Fig. 2). However, this also leads to degradation in the ON current. Since these factors have opposing effects on the delay of a logic gate, there exists an optimal underlap for which the delay is minimum. Introducing S/D underlap has an additional advantage of reduced DIBL due to increase in the channel length, leading to significant reduction in the sub-threshold leakage current. We obtained optimal source/drain underlap by simulating a DG-MOSFET structure using Taurus device simulator [8] for different source/drain underlap. We first start with a device (Lg=22nm, undoped body, near mid-gap work function, tsi =7nm) with no offset spacer (Lsp) while meeting a certain sub-threshold leakage target (100nA/um). We then increase Lsp to obtain the device with minimum gate delay (CV/I) (corresponding to ΔLsp=6nm on both sides – refer to Fig. 2). Comparison of the optimal device with the conventional DG-MOSFET is shown in Fig. 3. It can be seen that the sub-threshold leakage current (Isub) decreases by 98% for the optimized device. ON current (ION) degrades by 21% while total capacitance (C) improves by 44% leading to an overall improvement of 29% in the intrinsic delay (CV/ION) of the device. In addition, an improvement of 67% in DIBL and 27% in sub-threshold swing (SS) is achieved. To show the feasibility of these devices in circuit applications, we designed two 6-T SRAM cells using conventional DG-MOSFETs and those with optimal S/D underlap, respectively. The results are shown in Fig. 4. It can be seen that there is about 98% reduction in the leakage current (LEAK) for the optimal device. In addition, static noise margin (SNM) and write margin (WM) show an improvement of 22% and 9%, respectively. Access time (TAccess) is almost the same for the two devices. Considering tall cell layout for SRAM cell [9], the bit-cell area increases by 14% due to increase in the device footprint.

2.2 Fin Rotation and Fin Orientation Mobility of PMOS and NMOS devices can be improved by optimizing orientation of crystal surface, resulting in better circuit performance. For quasi-planar multiple-gate devices, such as FinFETs, surface orientation can be changed by modifying the layout of the devices (Fig. 5). This suggests that, orientation

Figure 1. Technology-device-circuit-system co-design options

for DG- MOSFETs for the 22 nm technology node and beyond

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Figure 4. Conventional vs. Optimal Gate underlap

structure: SRAM metrics comparison

Figure 6. Access time and read SNM variation for different

fin orientations

optimization can enhance the performance of FinFET logic circuits. In order to analyze the effect of fin-orientation on cell stability, performance and leakage of SRAM bit-cells, we simulated 6-T and 8-T SRAM cell configurations implemented using FinFETs with different fin orientations. Fig. 6 depicts the comparison of all (110) devices with different device orientations. The results show significant improvement in Read SNM (23-35%) and Access Time (22-33%). It is also observed that the optimized fin-orientations have a marginal impact on Write margin and Hold SNM. It has been shown that achieving (111) orientations on a (110) wafer is more feasible compared to a (100) wafer. Hence, rotated layouts can be avoided in the former, leading to less area penalty. Considering the layout feasibility and area penalty, the orientation (100) PUP (Pull-up), (110) AX (Access), (100) PD (Pull-down) gives a significant improvement in cell stability and performance However, it should be noted that such fin orientations can have detrimental effects on the sensitivity of cell stability and performance with respect to parameter variations.

2.3 Fin Thickness and Fin Ratio Optimization The impact of width quantization in FinFETs on the area and stability of an SRAM cell has been well studied. It is found that increase in the number of fins reduces the fin-to-fin variability. Hence, increasing the number of fins can reduce the device mismatch in an SRAM cell due to silicon thickness (Tsi) variation [10]. In FinFET SRAMs, different fin combinations can be realized (under iso-area constraint). Also because of width quantization in FinFETs, SRAM cell area increases in quanta of two fin pitches with increase in the number of fins. We used thin cell layout, fabricated using spacer lithography technique. In this process technology [11], two fins are fabricated in one pitch and to achieve odd number of fins, one fin can be etched away. Fig. 7 shows the layout of an SRAM cell with transistor fin ratios NP:NAX:NN = 1:1:2 (where NP, NAX and NN are the number of fins in the pull-up, access and pull-down transistors respectively). It can be seen that NAX or NP can be increased to 2 and NN reduced to 1 without increasing the cell area. Hence, under iso-area, one can have different combinations of fin ratios. For read stability, typically pull down transistor needs to be stronger than the access transistor. Also, for write stability, access transistor should be stronger than pull up transistor. This leaves only one possible combination i.e., NP:NAX:NN =1:1:2. Note that the ION of NMOS is higher than the ION of PMOS. Hence, even with same number of fins, access transistor is stronger than the pull up transistor, which enhances the write stability. For better read stability, pull-down transistor is stronger than the access transistor. Since, β ratio of the transistors also affects the cell leakage and access time, a suitable combination of fins should be determined for desired SRAM characteristics (leakage/bit, access time, area efficiency, failure probability etc.).

Figure 5. Modification of surface orientation in

FinFETs

Figure 2. Gate-Source/Drain underlap in FinFET

structures

Figure 3. Conventional vs. Optimal Gate underlap

structure: Device metrics comparison

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Figure 8. Schmitt Trigger based differential SRAM bitcell

[12]

For better stability, the following design trade-offs exist between Tsi and fin ratios: 1) increasing Tsi improves write stability 2) for small NN:NAX, read stability reduces with increase in Tsi,

however, the difference between read SNM (for increasing Tsi) diminishes as NN:NAX increases.

3) increasing NP:NN improves read SNM and write stability 4) read stability can be improved by increasing NN:NAX and write

stability can be improved by increasing NAX:NP. Considering above trade-offs, we can infer that – under iso-area condition, silicon thickness constraint can be relaxed without affecting the stability of the cell. However, increased Si fin thickness reduces the saturation current (of access transistors) impacting the access time. It has been shown that an increase in the number of fins reduces the variability (σ/μ) of device electrical parameters [10]. Extending the same analysis, one can assume that an increase in the number of fins in an SRAM cell can reduce the variation in Tsi, resulting in reduced failure probability. Relaxing the silicon thickness constraint in FinFETs improves manufacturability and reduces process variations. Thicker silicon body FinFETs reduce device mismatch among the transistors of an SRAM cell resulting in higher robustness. However, because of increased short-channel-effect in thick silicon body, inter-die variations in gate length and silicon thickness increase. .

3. CIRCUIT DESIGN USING FINFETs The effect of process variations on the system performance may need to be tackled not just at the device level, but also at higher levels of abstraction. In the previous section, we discussed the design and optimization of FinFETs. In this section, we will briefly describe certain circuit design techniques that could be useful for implementing circuits using FinFETs in 22 nm technology.

3.1 A Robust FinFET SRAM In an SRAM bitcell, the basic element for the data storage is the cross coupled inverter pair. For successful SRAM operation under PVT variations, the stability of the cross coupled inverter is important. Traditionally, device sizing has been adopted to mitigate the effects of process variations. However, device sizing may not be effective in improving the bitcell stability at very low supply voltages. We consider one bit cell configuration suitable for low-voltage FinFET SRAMs. The design approach is to incorporate built-in feedback mechanism to achieve successful low voltage SRAM operation [12]. Schmitt trigger based SRAM bitcells exhibits robust process

variation tolerance. This robust process tolerance can be an essential attribute for SRAM scaling into future nano-scaled technology nodes. The Schmitt Trigger based (ST) 10 transistor SRAM cell (Fig. 8) focuses on making the basic inverter pair of the memory cell robust. The positive feedback from NFL/NFR adaptively changes the switching threshold of the inverter depending on the direction of input transition (0 → 1 input transition). The ST bitcell utilizes differential operation and shows better noise immunity. Note that the cell can be used as a drop-in replacement for the 6T cell.

The ST bitcell gives near-ideal inverter characteristics essential for robust memory cell operation (Fig. 9). The cell has 1.56X improvement in read SNM, compared to 6T cell with ~2X larger area (layout of the ST bitcell shown in Fig. 10). Under iso-area condition, the ‘minimum area’ ST bitcell shows 1.52X read SNM than the 6T cell. Due to the absence of feedback from 1 → 0 input transition and series connected NMOS, the proposed ST bitcell shows higher write-trip-point than 6T cell. Monte-Carlo simulations (VDD = 400mV) for read and hold case show that the ST bitcell gives higher mean read/hold SNM compared to the 6T cell

Figure 7. FinFET SRAM thin-cell layout [10]

Figure 10. FinFET based Schmitt Trigger SRAM

thin cell layout [12]

Figure 9. Hold/Read mode characteristics (VDD = 400mV) [12]

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3.2 Logic Design using FinFETs Importance of proper transistor sizing in combinational circuits to achieve high circuit speed and/or low power is well understood. As discussed in the previous section, sizing of FinFETs is limited by width quantization. In other words, width of a FinFET, with both the gates tied together (3 Terminal FinFETs or 3-T FinFETs), can be increased in discrete steps of 2Hfin (where Hfin is the height of the fin), thus reducing the design options available to a circuit designer [13]. However, independent control of the front and back gates of FinFETs can potentially provide more design flexibility, since the resolution of discrete sizing step is now Hfin, half of what is obtained from the 3-T FinFETs. In this section, we discuss circuit design options using FinFETs with independently controlled front and back gates (4-Terminal FinFETs or 4-T FinFETs). In order to maximize the frequency of operation, critical path delays are required to be minimized. Since 3-T FinFETs have lower gate delays compared to 4-T FinFETs due to higher ION, critical paths can be implemented using 3-T FinFETs. However, for non-critical paths, one has more design options. Let us consider a 2-input NAND gate with input A in the non-critical path and input B in the critical path. Since, the pull down network (PDN) has two transistors in series, 4-T transistors cannot be used in PDN without affecting the critical path delay. However, in the pull-up network (PUN), the PMOS corresponding to signal A can be a 4-T FinFET with the other gate connected to VDD (Independent Gate or IG Cell) as shown in Fig. 11 (a). Now let us consider the case when both the inputs of a logic gate are in non-critical paths. Considering a 2-input NAND gate again, one can implement the PUN using just one 4-T FinFET, with the two input signals driving the independently controlled gates (Merged Gate or MG cell), as shown in Fig. 11(b). Employing 4-T FinFETs in the non-critical paths of a circuit has the following effects on the circuit performance and power: (1) load capacitance of the logic gate driving signal A (refer to Fig. 11(a)) reduces which leads to lower switching power as well as reduced delay (2) the charging time of the output node due to a transition in input A doubles due to the decrease in ION by half. Hence, the delay of the non-critical path increases by less than 50% with significant power savings. With proper design, it can be ensured that the increase in delay of the non-critical path does not increase the frequency of operation. In fact, if signal A is in the fan-out logic cone of a critical node, the corresponding critical path delay decreases (Fig. 11(c)). Similarly, one can employ 4-T FinFETs in the implementation of NOR gates as well. Since the β-ratio for a NOR gate is higher compared to a NAND gate, one can achieve more decrease in switching capacitance and hence, higher power savings in NOR gates. It may also be noted that due to the back gate contact overhead in IG cell, there is an area penalty of about 9%. However, for an MC cell, since one less transistor is used, one can achieve ~27% area savings. We now show some results validating the efficacy of the discussed technique. In order to compare the performance of IG and MC cells with 3-T FinFETs, two libraries were developed: (1) using only 3-T FinFETs and (2) with low power IG cells added to the 3-T FinFET library. A set of ISCAS85 benchmark circuits were synthesized using both the libraries and power and area savings were analyzed. Fig. 12 shows the results. It can be seen

that on an average, 18% power savings and 8% area savings were achieved. It is also important to consider the impact of process variations on the efficacy of this technique. To analyze the effect of process variations, circuits were synthesized in the worst case corner. Fig. 13 shows the power and area savings for nominal and worst case corners at iso-performance. It can be seen that even in the worst case, one can achieve power savings of about 5% and area savings of 2%.

4. SYSTEM LEVEL DESIGN ISSUES There has been a lot of interest in recent years to address variations earlier in the design cycle, namely at the architecture and system levels, where it is possible to effectively trade-off variation-tolerance, power, performance, and other metrics such as “quality of results”. RAZOR [5], is an approach to Dynamic Voltage Scaling (DVS), based on dynamic detection and correction of circuit timing errors. The key idea of RAZOR is to tune the supply voltage by monitoring the error rate during circuit operation, thereby eliminating the need for large voltage margins. A shadow latch operated with a delayed clock edge is used to detect timing errors. If timing failure is detected, the pipeline is stalled, rolled back, and recomputed with correct values from shadow latches. CRISTA [4] is another approach for low-power, variation-tolerant digital system design, which allows for aggressive voltage over-scaling with a small throughput penalty. The CRISTA design principle (a) isolates and predicts the paths that may become critical under process variations, (b) ensures that they are activated rarely, and (c) avoids possible delay failures in the critical paths by adaptively stretching the clock period to two cycles. In [14], the authors describe a variant of CRISTA called Trifecta, which is an architectural technique that completes common-case sub-critical path operations in a single cycle but uses two cycles when the critical path is exercised. Note that the system level techniques are more or less independent of the underlying technology.

Figure 11. Two low-power options for two-input NAND in IG FinFET technology.(a) Independent gate (IG-Cell) control at A: B is in critical path while A is in noncritical path. (b) Merged gate (MG-Cell): Merging two parallel devices in the pull-up network when both timing arcs are noncritical. (c) Critical path delay reduction due to reduced capacitive loading in the noncritical path [13]

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5. CONCLUSIONS Technology scaling in 22nm node would require closer interaction between process, device, circuit, and architecture. Co-optimization methodologies across different levels would help to mitigate the challenges arising due to changes in transistor topology and increased process variations. Novel device/circuit/system solutions integrated seamlessly with the EDA tools would help meet the desired yield and would help the semiconductor industry to reap the benefits of scaling economics in sub-22nm nodes.

6. ACKNOWLEDGMENTS Authors would like to thank Semiconductor Research Corporation (SRC), Focused Center Research Program (C2S2), and Intel Corporation for funding this research.

7. REFERENCES [1] K. Kim et al, “Double-gate CMOS: symmetrical- versus

asymmetrical-gate devices”, IEEE Trans. Electron Devices., vol. 48, no. 2, pp: 294-299, Feb 2001.

[2] D Hisamoto et al, “FINFET- a self-aligned double-gate MOSFET scalable to 20 nm”, IEEE Trans. Electron Devices, vol. 47, no. 12, pp: 2320-2325, Dec 2000.

[3] V. Trivedi et al, “ Nanoscale FinFET with Gate-Source/Drain Underlap”, IEEE Trans. Electron Devices, vol. 52, no. 1, pp: 56-62, Jan 2005.

[4] S. Ghosh et al., “CRISTA: A new paradigm for low-power and robust circuit synthesis under parameter variations using critical

path isolation,” IEEE Trans. Computer-Aided Design, vol. 26, no. 11, pp. 1947-1956, Nov 07.

[5] D. Ernst et al “RAZOR: A Low-Power Pipeline Based on Circuit-Level Timing Speculation” Proc. 36th Annual Int. Symp. Micro-architecture, Dec 2003.

[6] S. Xiong et al, “Sensitivity of double-gate and FinFET Devices to process variations,” IEEE Trans. Electron Devices, vol. 50, no. 11, pp: 2255-2261, Nov 2003.

[7] Aditya Bansal et al., “Device Optimization Technique for Robust and Low Power FinFET SRAM Design in Nanoscale Era” IEEE Trans. Electron Devices, vol. 54, no. 6, pp:1409-1419 , June 2007

[8] Taurus Device Simulator, Synopsys Inc., v2004.09.

[9] T. Ludwig et al, “FinFET technology for future micro-processors”, Proc. IEEE SOI Conf., pp: 33-34. 2003.

[10] D. Lekshmanan et al., “FinFET SRAM: Optimizing Silicon Fin Thickness and Fin Ratio to Improve Stabilty at iso area”, Proc. IEEE Custom Integrated Circuits Conf., pp: 623-626, 2007.

[11] Y.-K. Choi et al, “Nanoscale CMOS spacer FinFET for the terabit era”, IEEE Electron Device Letters, vol. 23, no. 1,pp: 25-27, Jan 2002.

[12] J. P. Kulkarni et al, “160mV Robust Schmitt-Trigger based Sub-threshold SRAM”, IEEE J. Solid State Circuits, vol. 42, no.10, pp. 2304-2313, Oct 2007.

[13] A Datta et al, “Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices” IEEE Trans. Computer-Aided Design., vol. 26, No 11 pp: 1957-1966, Nov 2007.

[14] P. Ndai et al., “Trifecta: A non-speculative scheme to exploit common, data-dependent subcritical paths,” IEEE Trans. VLSI Systems (to appear)

(a)

(b)

Figure 13. (a) Power and (b) area savings of ISCAS85 benchmark circuits in nominal and worst case corners

at iso-performance [13]

(a)

(b)

Figure 12. (a) Power and (b) area savings for ISCAS85 benchmark circuits using IG FinFET technology [13]

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